JP2002358537A - Device and method for generating image and device and method for processing image - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image generating device for generating a MIP mapping image with one or a plurality of resolutions in real-time by a MIP mapping processing without causing the increase of a circuit scale and also to provide an image processor and the methods for the devices. SOLUTION: The system of the present invention is provided with vertically connected line buffers 300-304 which holds data for the portion of one line of original image data and successively transfers held data in parallel, a half filter part 305 and a quarter filter part 306 which receive data for the portions of continuous three lines and five lines held in the respective line buffers, extract n×n a pixel with a prescribed pixel as a center based on the number n of input lines, weighted average a color value by a weighted coefficient, reduce the width and height of a texture through the use of a pre-set minute degree and generate MIP mapping image data and also an output circuit 313 which outputs the MIP mapping images generated by the filter parts 305 and 306 by a prescribed timing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image generating apparatus, an image processing apparatus, and a method for generating a mipmap image having one or a plurality of resolutions.

[0002]

2. Description of the Related Art In a three-dimensional graphics system, an entire image is drawn by decomposing three-dimensional coordinates into polygons such as triangles and drawing the polygons. Therefore, in this case, it can be said that the three-dimensional image is defined by a combination of polygons. By the way, the surface of an object around us often has a complex pattern of repetitive patterns. As the patterns and patterns become more complicated and finer, it becomes more difficult to model each pattern or pattern with a triangle or the like. Therefore, as a means to solve this, Texture Mapping
Is used.

[0003] Texture mapping realizes a high-reality image with a small number of vertices by attaching image data captured by a scanner or the like to the surface of an object. Define a mapping f to a coordinate system,
A mapping g from the window coordinate system to the texture coordinate system is obtained, and a texel (Texel, Texture Cell Elemen) which is a texture element corresponding to each pixel (Pixel, Picture Cell Element) in the window coordinate system is obtained.
t).

[0004] Image data used for textures is stored in a memory area called a texture memory. Therefore, if the process of updating the texture memory as needed using the moving image data is performed, the texture mapping process using the moving image can be performed.

[0005] As described above, texture mapping is performed by attaching a texture to the surface of an object. For example, as shown in FIG.
On the object coordinate system, there is one in which a texture 201 is pasted on the surface of a rectangular polygon 200. When this is rotated and displayed as shown in FIG. 11B, the original is displayed on the window coordinate system. The polygon (in this case, a rectangle) has an enlarged texture attached to the left end, and it appears as if the reduced texture is attached to the right as it goes to the right. In this case, when pasting a texture that is larger than the original image to the pixel, it is possible to deal with the original image in real time by performing a filtering process of the original image such as 4-neighbor interpolation.

[0006] However, when the texture is reduced, many texels correspond to one pixel, and the aliasing disturbance of the image becomes noticeable. Therefore, a texture pattern having various kinds of texture sizes corresponding to the size of polygons is generated in advance, and a mipmap (MIPMAP: multum in p
An arvo, many things in a small place) texture mapping method (hereinafter, referred to as a mipmap method) is known.

[0007] In the mipmap method, bitmap data (texture data) obtained by reducing the original image at various reduction rates is stored in a texture memory. For example, as shown in FIG. 12, an image in which the horizontal and vertical lengths of the original image are sequentially reduced to 1/2 (the reduction ratio is 1 /
2, 1/4, 1/8,...) Are prepared in advance and stored in the texture memory.

As for the size of each reduced image, a measure called LOD (Level of Detail) is used. The largest image is the same size as the input image, which is LOD “0”. A reduced image whose vertical and horizontal size is 1/2 (1/4 in area) is LOD "1". Similarly, an image having a vertical and horizontal size of 1/4 and 1/8 has a vertical and horizontal size of 1 such as LOD "2" and "3", respectively.
The value of LOD increases by one each time the value becomes / 2. This reduced image set theoretically needs to be prepared until the vertical and horizontal sizes become 1 × 1 pixels.

In the mipmap process, at the time of texture mapping, by selecting and pasting a reduced image having a size closest to the reduction ratio of the pixel to be processed, a processing result at high speed and without aliasing is obtained.
If higher image quality is desired, an interpolation operation is performed within the selected reduced image (bilinear processing), or reduced images of a plurality of sizes are selected, and further interpolation operations are performed between the reduced images (trilinear processing). There is a known technique. These operations take more time, but are now commonly used because of the recent advances in semiconductor technology that have enabled high-speed operations.

[0010]

In the mipmap process, it is necessary to prepare reduced images having a plurality of resolutions, and this takes a long time. It has been considered difficult to arrange a set of reduced images in real time.

In view of the above, a mipmap image generating apparatus that does not cause aliasing in a generated mipmap image has been proposed (for example, see Japanese Patent Application Laid-Open No. 7-230555). This apparatus includes, for example, a spatial transform processing unit such as a discrete cosine transform (DCT), an inverse discrete cosine transform (IDCT), or a discrete Fourier transform or an inverse Fourier transform in order to suppress aliasing noise. A filter for cutting is used.

However, in this conventional device, DC
If this is to be realized by hardware in order to perform spatial transformation processing such as T and IDCT, there is a disadvantage that the circuit scale becomes large.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a texture image (mipmap image) having one or a plurality of resolutions in real time by mipmap processing without increasing the circuit scale. It is an object of the present invention to provide an image generation apparatus capable of generating image data, an image processing apparatus capable of performing texture mapping processing with high accuracy by using them, and a method thereof.

[0014]

According to one aspect of the present invention, there is provided an image generating apparatus for receiving a texture original image data and generating a reduced mipmap image with a predetermined level of detail. And at least three cascade-connected line buffers for holding the data of one line of the original image data and sequentially transferring the held data in parallel, and for at least three continuous lines held by the line buffers. And the number of input lines n
Extracts n × n pixels centered on a predetermined pixel based on, and weights average the extracted n × n pixels with weighted coefficients, and sets the width and height of the texture in advance. It has at least one filter unit for generating desired mipmap image data by reducing the degree, and an output unit for outputting the mipmap image generated by the filter unit at a predetermined timing.

Further, the image processing apparatus of the present invention comprises: at least three cascade-connected line buffers for holding one line of image data and sequentially transferring the held data in parallel; Receiving the data of at least three consecutive lines held in step (1), extracts n × n pixels centered on predetermined pixels based on the number n of input lines, and weights the extracted n × n pixels by a weighted coefficient. At least one filter unit for generating a desired mipmap image data by reducing the width and height of the texture with a predetermined degree of detail by weighted averaging the color values in the mipmap image generated by the filter unit An output unit for outputting the original image data at a predetermined timing; and a mipmap output from the original image data and the image generation device. A storage circuit for storing the output image, and an image processing circuit for performing a texture mapping process based on the image data stored in the storage circuit to generate an output image.

Further, according to the present invention, when the filter section of the image generating apparatus and the circuit extracts n × n pixels,
Extraction is performed by overlapping adjacent n × n extracted pixels and lines.

Further, in the present invention, the output unit of the image generation device and the circuit inputs the mipmap image data generated by the filter unit in synchronization with a video clock,
It includes a buffer that outputs with a clock faster than the video clock.

Further, in the present invention, the image generating apparatus and the circuit have a plurality of filter units for generating reduced mipmap image data with different degrees of detail, and the output unit includes a mipmap by each of the filter units. Output circuits for outputting map image data at different timings are included.

Further, in the present invention, the output circuit of the image generating apparatus and the circuit switches the base pointer of the memory space of the storage circuit to be output for each output of each filter unit, and writes the output for each line. Then, the mipmap image data generated by each filter unit is selected and output.

Further, in the present invention, the line buffer of the image generating device and the circuit performs line data input and parallel transfer in synchronization with the horizontal synchronization signal.

The present invention also relates to an image generating method for generating a reduced mipmap image with a predetermined level of detail by receiving original image data of a texture. Are held for at least three lines, and n × n pixels centered on a predetermined pixel based on the number n of input lines are extracted based on the held data for at least three continuous lines, and the extracted n × n , The color value is weighted by a weighted coefficient, and the width and height of the texture are reduced with a predetermined level of detail to generate desired mipmap image data.

In the image processing method of the present invention, at least three lines of data of one line of original image data are held, and the number n of input lines is determined based on the held data of at least three consecutive lines. N × n pixels centered on a predetermined pixel based on the extracted pixel values, the extracted n × n pixels are weighted by color-weighted coefficients using weighted coefficients, and the width and height of the texture are set in detail. To generate desired mipmap image data, store the original image data and the generated mipmap image data in a storage circuit, perform a texture mapping process based on the image data stored in the storage circuit, and output an image. Generate

In the method of the present invention, when extracting n × n pixels, the extraction is performed by overlapping the line with the adjacent n × n extracted pixels.

According to the present invention, for example, original image data is input to the image generating device and the storage circuit, and the original image data is stored in a predetermined area of the storage circuit. In the image generation circuit, data of one line of original image data is held in a line buffer, and the held data is sequentially transferred in parallel. Then, continuous data of, for example, three lines held in each line buffer is supplied to the filter unit. The filter section extracts n × n (eg, 3 × 3) pixels centered on a predetermined pixel based on the number n of input lines. At this time, for example, in the case of extracting n × n pixels, adjacent n × n extracted pixels are overlapped and extracted. And the extracted n
× n pixels are weighted with color-weighted coefficients using weighted coefficients, and the width (width) and height (length) of the texture are reduced with a predetermined level of detail to generate desired mipmap image data. Output to the output unit.

The output section outputs the mipmap image data generated by the filter at a predetermined timing. In the output unit, for example, the mipmap image data generated by the filter unit is held in a buffer in synchronization with the video clock, and the held mipmap image data is output with a clock faster than the video clock. Also,
When there are a plurality of filter units, the output unit outputs mipmap image data from each filter unit at different timings by an output circuit. Specifically, for example, for each output of each filter unit, the base pointer in the memory space of the storage circuit to be output is switched, and the mipmap image data generated by each filter unit is selected so as to be written line by line. Is output. In the storage circuit, the mipmap image data from the image generation circuit is written in a predetermined area. Next, the image processing circuit reads out the image data stored in the storage circuit and performs a rendering process.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An image processing apparatus according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an overall configuration of an image processing apparatus according to the present invention, and FIG. 2 is a block diagram more specifically showing a main part of the image processing apparatus shown in FIG. 1 including a signal flow. FIG. As shown in FIGS. 1 and 2, the image processing apparatus 1 includes a video signal generation circuit 2 and a mipmap (MIP map).
MAP) processing circuit 3, texture memory 4, rendering circuit 5, frame memory 6, display 7, and control circuit 8;
Connected through.

Here, the mipmap processing circuit 3 corresponds to the image generating apparatus of the present invention, the texture memory 4 corresponds to the storage circuit of the present invention, the rendering circuit 5 corresponds to the image processing circuit of the present invention, The memory 6 corresponds to the frame memory of the present invention, and the display 7 corresponds to the display means of the present invention.

Hereinafter, the function of each component of the image processing apparatus 1 will be described.

The video signal generation circuit 2 generates a digital video signal (for example, a moving image signal) obtained from a video image pickup device or a digital video signal obtained through MPEG decoding, and converts this into a video signal S2. To the mipmap processing circuit 3 and the texture memory 4. The video signal S2 is an image signal in which the level of detail LOD (hereinafter, also referred to as LOD level) in the mipmap processing is “0”. Here, the level of detail corresponds to the resolution of the present invention.

The mipmap processing circuit 3 uses the video signal S2 input from the video signal generation circuit 2 and has LOD levels of “0”, “1”, “2”,.
The video signals S30, S31, S32,..., S3n corresponding to the texture image (mipmap image) of “n” are generated in real time and output to the texture memory 4. When k is an integer satisfying 1 ≦ k ≦ n, L
The image at the OD level “k” is a reduced image in which the height and width of the image at the LOD level “0” is に^k times. Note that the resolution of the reduced image decreases as the value of the LOD level “k” increases. In the present embodiment, the mipmap processing circuit 3 synchronizes with the input of the video signal S2,
Specifically, generation and output of the video signals S30 to S3n are performed in real time in synchronization with the horizontal synchronization signal HSYNC.

FIG. 3 is a circuit diagram showing a specific configuration example of the mipmap processing circuit 3 according to the present invention. FIG.
FIG. 4 is a diagram showing a timing chart of data input and transfer of the line buffer of FIG. 3;

The mipmap processing circuit 3 includes line buffers 300 to 304, a 1/2 filter section 305, a 1/4
Filter unit 306, buffers 307 to 309, asynchronous F
IFO (asyncronous First-In First-Out) 310-31
2 and an output circuit 313.

The video signal S generated by the video signal generation circuit 2
2 input lines, the line buffers 304, 30
3, 302, 301, and 300 are cascaded in this order.

The line buffer 304 has a so-called serial-in / parallel-out function.
As shown in (C), one line of data A of the serial video signal S2 by the video signal generation circuit 2 is sequentially input in synchronization with the horizontal synchronizing signal SYNC, and one line of data A in the h0 period And the next horizontal synchronization signal S
In synchronization with the YNC, the held data A for one line is transferred to the next line buffer 303 and the ４ filter unit 30.
6 is transferred in parallel. In parallel with this parallel transfer, the line buffer 304 synchronizes with the horizontal synchronizing signal SYNC, as shown in FIGS. 4A to 4C, and follows the serial video signal S2 by the video signal generation circuit 2. The data B for one line is sequentially input, the data B for one line is held during the period h1, and the data B for one line is held in synchronization with the next horizontal synchronization signal SYNC in the next line buffer. 303 and a 1/4 filter section 306. Thereafter, the line buffer 304 sequentially performs the same operation on the data C to G,... For one line.

The line buffer 303 is shown in FIGS.
As shown in (D), the data A of one line portion transferred in parallel in synchronization with the horizontal synchronization signal HSYNC is input and held during the period h1, and held in synchronization with the next horizontal synchronization signal SYNC. Data A for one line is transferred in parallel to the next line buffer 302 and １ ／ filter unit 306. In parallel with this parallel transfer, the line buffer 303 synchronizes with the horizontal synchronization signal SYNC as shown in FIGS. 4A to 4D, for the next one line transferred in parallel from the line buffer 304. Enter data B,
During the period h2, one line of data B is held, and the held one line of data B is transferred in parallel to the next line buffer 302 and the 1/4 filter unit 306 in synchronization with the next horizontal synchronization signal SYNC. I do. Line buffer 303
Will perform the same operation thereafter for one line of data C to G,.
・ ・ Sequentially.

The line buffer 302 is shown in FIGS.
As shown in (E), the data A of one line portion transferred in parallel in synchronization with the horizontal synchronization signal HSYNC is input and held during the period h2, and held in synchronization with the next horizontal synchronization signal SYNC. The data A for one line is transferred in parallel to the next line buffer 301, 1/2 filter unit 305, and 1/4 filter unit 306. Line buffer 30
2 is the parallel transfer shown in FIG.
As shown in (E), in synchronization with the horizontal synchronization signal SYNC, the data B for the next one line transferred in parallel from the line buffer 303 is input, and the data B for one line is held during the period h3. In synchronization with the next horizontal synchronizing signal SYNC, the held data B for one line is transferred to the next line buffer 301, 1/2 filter unit 305, and 1/4.
The data is transferred to the filter unit 306 in parallel. Line buffer 3
02 indicates that the same operation is performed for one line of data C to
G,... Are sequentially performed.

The line buffer 301 is shown in FIGS.
As shown in (F), the data A of one line portion transferred in parallel in synchronization with the horizontal synchronization signal HSYNC is input and held during the period h3, and held in synchronization with the next horizontal synchronization signal SYNC. Data A for one line is transferred in parallel to the next line buffer 300, 1/2 filter unit 305, and 1/4 filter unit 306. Line buffer 30
1 is the parallel transfer shown in FIG.
As shown in (F), in synchronization with the horizontal synchronization signal SYNC, the data B for the next one line transferred in parallel from the line buffer 302 is input, and the data B for one line is held during the period h4. In synchronization with the next horizontal synchronizing signal SYNC, the held data B for one line is transferred to the next line buffer 300, 1/2 filter unit 305, and 1/4.
The data is transferred to the filter unit 306 in parallel. Line buffer 3
01 is the same operation for one line of data C to
G,... Are sequentially performed.

The line buffer 300 is shown in FIGS.
As shown in (F), the data A of one line which is transferred in parallel in synchronization with the horizontal synchronization signal HSYNC is input and held during the period h4, and held in synchronization with the next horizontal synchronization signal SYNC. The data A for one line is input to the 1/2 filter unit 305, the 1/4 filter unit 306, and the buffer 3
07 in parallel. In parallel with this parallel transfer, the line buffer 300 synchronizes with the horizontal synchronization signal SYNC as shown in FIGS. 4A to 4F, for the next one line transferred in parallel from the line buffer 301. The data B is input, the data B for one line is held during the period h5, and the data B for one line is held in synchronization with the next horizontal synchronization signal SYNC.
The data is transferred in parallel to the four-filter unit 306 and the buffer 307. Thereafter, the line buffer 300 sequentially performs the same operation on the data C to G,... For one line.

The 1/2 filter section 305 is, for example, 3 ×
5 and 6 having a nine-point reduction filter for extracting three nine pixels and receiving three lines of data (for example, A to C) from the line buffers 302, 301, and 300. The data that has been passed through the 9-point reduction filter is held, and as shown in, for example, FIG. 6C, the color (color) value is weighted and averaged using the weighted coefficients for the held 9 points to obtain a texture. , The width (horizontal) and the height (vertical) are reduced to そ れ ぞ れ, respectively, and the reduced mipmap image data S305 is output to the buffer 308. In the example of FIG. 6C, the weighting coefficient of the nine central pixels is 1
/ 4, the weighting coefficient of the left, right, top and bottom four images is 1 /
8, the weighting coefficients of the surrounding four pixels are set to 1/16.

It should be noted that the 9-point reduction filter arranged in the 1/2 filter section 305 filters input line data so as to overlap adjacent nine points by one line. The 1/2 filter unit 305 holds the result of the reduction filter for each of the three line buffers 300 to 302 every time two lines are captured. This 1/2
In the filter unit 305, the 縮小 reduction processing is first performed for a period of 3h, and thereafter is performed once for 5h, 7h and two horizontal synchronization signals HSYNC. Then, the filtering result is output from the 1/2 filter unit 305 to the buffer 308 as the mipmap image data S305 once for every two horizontal synchronization signals HSYNC.

The 1/4 filter section 306 is, for example, 5 ×
5, a 25-point reduction filter for extracting 25 pixels,
Five lines of data from line buffers 304, 303, 302, 301, and 300 (eg, AE)
In response to this, the data that has been passed through the 25-point reduction filter as shown in FIGS. 6 and 7 is held, and for example, as shown in FIG. By weighting and averaging the color values, the width (width) and height (length) of the texture are each reduced to 1/4, and the reduced mipmap image data S306 is stored in the buffer 309.
Output to In the example of FIG. 6E, the weighting coefficient of the central pixel at 25 points is 1/9, the weighting coefficient of the left, right, up and down four images is 2/27, and the weighting coefficient of the four diagonally adjacent pixels is 4/81. The weighting coefficient of four pixels with the central pixel being one pixel vertically and horizontally is 1/27, the weighting coefficient of eight pixels above and below and left and right is 2/81, and the weighting coefficient of four surrounding pixels is 1/81. Have been.

The 25-point reduction filter arranged in the 1/4 filter section 306 performs filtering on input line data so as to overlap the adjacent 25 points by one line. The ４ filter unit 306 holds the result of the reduction filter for each of the five line buffers 300 to 304 every time two lines are fetched. This one
In the / 4 filter unit 306, the 縮小 reduction processing is
Initially, it is performed in a 2h period, and thereafter, it is performed once for 6h, 10h and 4 horizontal synchronization signals HSYNC. The filtering result from the 1/4 filter unit 306 is output to the mipmap image data S306 once every four horizontal synchronization signals HSYNC.
Is output to the buffer 309.

The buffer 307 has a so-called parallel-in / serial-out function, receives one-line data transferred in parallel from the line buffer 300 in synchronization with the low-speed video clock VCLK, and operates at a higher speed than the video clock VCLK. Clock HICL (high frequency)
Asynchronous FIFO 31 as serial data in synchronization with K
Transfer to 0.

The buffer 308 has a parallel-in / serial-out function, and has a low-speed video clock VCLK.
ミ, receives 縮小 -reduced mipmap image data S 305 (texture data) transferred in parallel from the 部 filter unit 305 in synchronization with the video clock VCLK, and synchronizes with the high-speed clock HICLK from the video clock VCLK as serial data to the asynchronous FIFO 311 Forward.

The buffer 309 has a parallel-in / serial-out function, and has a low-speed video clock VCLK.
And receives the quarter-reduced mipmap image data S306 (texture data) transferred in parallel from the quarter-filter unit 306 in synchronization with the video clock VCLK. Forward.

The asynchronous FIFO 310 has a buffer 307
, Serial data of one line transferred from the output circuit 313 is sequentially input, and is output as LOD0 data in the output circuit 313 in the input order.
Output to

The asynchronous FIFO 311 has a buffer 308
, The MIP map image data of 縮小 reduction, which is the data of LOD1 transferred as serial data from, is sequentially input and output to the input order output circuit 313.

The asynchronous FIFO 312 has a buffer 309
, Sequentially input the 1 / 4-reduced mipmap image data, which is the data of LOD2 transferred as serial data, and outputs it to the output circuit 313 in the order of input.

The output circuit 313 is connected to the asynchronous FIFO 310
1 line of serial data of LOD0, mipmap image data of 縮小 reduction of LOD1 by asynchronous FIFO 311 and L of asynchronous FIFO 312
The mipmap image data of OD21 / 4 reduction is output to the texture memory 4 at different timings, for example. For example, as shown in FIG. 8, the output circuit 313 switches the output destinations of the asynchronous FIFOs 310, 311, and 312 in which data having different levels of detail (reduction levels) are stored by switching the base pointer BP of the memory space MS to a line. Asynchronous FIFO3
Outputs 10, 311 and 312 are selected and output to the texture memory 4.

The texture memory 4 stores the video signal S2 from the video signal generation circuit 2 and the mipmap processing circuit 3
Signal (mipmap image data) from S30
S3n is stored in a predetermined area.

Next, a specific configuration example of the texture memory 4 in the image processing apparatus 1 shown in FIGS. 1 and 2 will be described.

FIG. 9 is a diagram showing a specific configuration example of the texture memory 4. As shown in FIG. 9, the texture memory 4 includes physical memories 41 and 42 and buses 43 and 44.
Having.

The physical memories 41 and 42 are dual-port memories, and can perform data writing and data reading independently. The write port of the physical memory 41 is connected to the AV bus 9 shown in FIGS. 1 and 2 and receives a video signal S2 as original image data output from the video signal generation circuit 2. The read port of the physical memory 41 is connected to the bus 44.

The write port of the physical memory 42 is the bus 4
3 and the read port of the physical memory 42 is connected to the bus 44.

The bus 43 is connected to the AV bus 9 shown in FIGS. 1 and 2 and the write port of the physical memory 42, and the mipmap image data S via the AV bus 9.
In response to 30 to S3n, these are output to the write port of the physical memory 42.

The bus 44 is connected to the read ports of the physical memories 41 and 42 and to the AV bus 9 shown in FIGS. 1 and 2, and renders the image data S 4 read from the physical memories 41 and 42 to the rendering circuit 5. Output to

In the texture memory 4 having the configuration shown in FIG. 9, the addresses in the physical memory 42 where the mipmap image data S30 to S3n are written are discontinuous in units of lines. Preferably, it is used.

[0059] rendering circuit 5, a video signal S2 stored in the texture memory 4, S3 ₁ to S3 _n of reads LOD level of the video signal S4, which is specified by the control circuit 8 from the texture memory 4, read video A rendering process is performed using the signal S4 to generate a video signal S5, which is output to the frame memory 6. In this rendering processing, texture mapping for attaching a moving image to a three-dimensional model is performed.

The frame memory 6 includes a rendering circuit 5
And outputs the stored video signal to the display 7.

The display 7 displays an image corresponding to the video signal input from the frame memory 6.

Next, the operation of the image processing apparatus 1 having the above configuration will be described.

The video signal S2 as the original image data generated by the video signal generation circuit 2 is output to the mipmap processing circuit 3 and the texture memory 4. Then, the video signal S2 is input to the write port of the physical memory 41 of the texture memory 4 via the AV bus 9, and is written to the physical memory 41.

In the mipmap processing circuit 3, data of one line of the serial video signal S2 from the video signal generation circuit 2 is sequentially input to the line buffer 304, and the data of h (0, 1,...) One line of data is held during the period, and the held one line of data is transferred in parallel to the next line buffer 303 and the フ ィ ル タ filter unit 306 in synchronization with the next horizontal synchronization signal SYNC. In the line buffer 303, the horizontal synchronization signal H
The data of one line part transferred in parallel from the line buffer 304 in synchronization with SYNC is h (1, 2,...)
Of the horizontal synchronization signal SYN
In synchronization with C, the held data for one line is transferred in parallel to the next line buffer 302 and the ４ filter unit 306. In the line buffer 302, the data of one line portion transferred in parallel from the line buffer 303 in synchronization with the horizontal synchronization signal HSYNC is h (2, 3,
..) Are input and held, and in synchronization with the next horizontal synchronizing signal SYNC, the held one line of data is transferred to the next line buffer 301, the 1/2 filter unit 305,
And are transferred in parallel to the ４ filter unit 306.
In the line buffer 301, the data of one line portion, which is transferred in parallel from the line buffer 302 in synchronization with the horizontal synchronization signal HSYNC, is input and held during a period of h (3, 4,...), And is held in the next horizontal synchronization. In synchronization with the signal SYNC, the held data for one line is transferred in parallel to the next line buffer 300, 1/2 filter unit 305, and 1/4 filter unit 306. Further, in the line buffer 300, the data A of one line portion, which is transferred in parallel from the line buffer 301 in synchronization with the horizontal synchronization signal HSYNC, is input and held during the period of h (4, 5,...). In synchronization with the horizontal synchronizing signal SYNC, the held data for one line is output to the 1/2 filter unit 305,
The data is transferred in parallel to the / 4 filter unit 306 and the buffer 307.

The 1/2 filter section 305 receives three lines of data from the line buffers 302, 301, and 300, and holds the data that has passed through the nine-point reduction filter. In the nine-point reduction filter, filtering is performed on input line data such that the one-line overlaps with nine adjacent points. And 1/2
In the filter unit 305, the color values are weighted and averaged using the weighted coefficients for the held nine points, whereby the width (horizontal) and height (vertical) of the texture are each reduced by half.
Is reduced to In the フ ィ ル タ filter unit 305, the 処理 reduction processing is first performed in a 3h period, and thereafter, is performed once for 5h, 7h and two horizontal synchronization signals HSYNC. Then, once in two horizontal synchronization signals HSYNC, 1 /
The filtering result is output from the second filter unit 305 to the buffer 308 as mipmap image data S305.

In the フ ィ ル タ filter section 306, the line buffers 304, 303, 302, 301, and 3
After receiving five lines of data from 00, the data passed through the 25-point reduction filter is held. In the 25-point reduction filter, filtering is performed on input line data so as to overlap the adjacent 25 points by one line. Then, the 1/4 filter unit 306 weights and averages the color values using the weighted coefficients for the held 25 points, whereby the width (width) and height (length) of the texture are reduced by 1/4, respectively. Is reduced to In the 1/4 filter section 306, the 1/4 reduction processing is initially performed by 2
This is performed in the h period, and thereafter, performed once for 6h, 10h, and 4 horizontal synchronization signals HSYNC. Then, the four horizontal synchronization signals H
Once in SYNC, the filtering result is output from the quarter filter unit 306 to the buffer 309 as mipmap image data S306.

In the buffer 307, data of one line portion transferred in parallel from the line buffer 300 in synchronization with the low-speed video clock VCLK is input, and the input data is converted to a high-speed clock H higher than the video clock VCLK.
Asynchronous FIFO as serial data in synchronization with ICLK
Transferred to O310. In the buffer 308, the 1/2 filter unit 30 is synchronized with the low-speed video clock VCLK.
5, the mipmap image data S305 of 縮小 reduction, which is transferred in parallel, is input, and the input data is synchronized with the high-speed HICLK, and is output as asynchronous FI serial data.
Forwarded to FO311. Similarly, in the buffer 309, １ ／ reduced mipmap image data S306 parallel-transferred from the フ ィ ル タ filter unit 306 is input in synchronization with the low-speed video clock VCLK, and the input data is used as the high-speed clock HICLK. The data is synchronously transferred to the asynchronous FIFO 312 as serial data.

Then, in the asynchronous FIFO 310,
One line of serial data transferred from the buffer 307 is sequentially input, and is output to the output circuit 313 as LOD0 data in the input order. Asynchronous FIFO
At 311, mipmap image data of １ ／ reduction, which is LOD 1 data transferred as serial data from the buffer 308, is sequentially input and output to the output circuit 313 in the input order. Similarly, in the asynchronous FIFO 312, mipmap image data of 縮小 reduction, which is LOD2 data transferred as serial data from the buffer 309, is sequentially input, and output to the output circuit 313 in the input order.

In the output circuit 313, the asynchronous FIFO 31
The base pointer BP of the memory space MS is switched between serial data of one line of LOD0 by 0, mipmap image data of 1/2 reduction of LOD1 by the asynchronous FIFO 311 and mipmap image data of LOD21 / 4 reduction by the asynchronous FIFO 312. Asynchronous FIFOs 310 and 31 are written so as to be written line by line.
Outputs 1 and 312 are selected, and the selected mipmap image data is output to the frame memory 4.

The texture memory 4 stores the mipmap image data S30 to S3n from the mipmap processing circuit 3.
Is input to the write port of the physical memory 42 via the AV bus 9 and the bus 43 of the texture memory 4,
The data is written to the physical memory 42. At this time, as described with reference to FIG.
S3n is written continuously by switching the base pointer BP in the memory space MS, without collision, for each line. Then, independently of the writing operation to the physical memories 41 and 42, in response to a request from the rendering circuit 5,
The image data (video signal) S4 stored in the physical memories 41 and 42 is read out to the rendering circuit 5 via the bus 44 and the AV bus 9.

Next, the video signals S 2, S 3 ₁ to S 3 stored in the texture memory 4 are rendered by the rendering circuit 5.
Of the S3 _n , the video signal of the LOD level specified by the control circuit 8 is read from the texture memory 4 as the video signal S4. And the rendering circuit 5
In, rendering processing is performed using the video signal S4, and the video signal S5 generated thereby is written to the frame memory 6. Then, the video signal read from the frame memory 6 is output to the display 7, and an image corresponding to the video signal is displayed on the display 7.

As described above, according to the present embodiment, the cascade-connected line buffers 300 to 304 which hold one line of original image data and sequentially transfer the held data in parallel, Receiving data for three consecutive lines and five lines held in each line buffer, n × n pixels centering on a predetermined pixel based on the number n of input lines are extracted, and the extracted n × n pixels are extracted. A 1/2 filter unit 305, a 1/4 filter that weights and averages color values with weighted coefficients to reduce the width and height of the texture with a predetermined level of detail to generate desired mipmap image data Unit 306 and filter unit 30
Since the output circuit 313 for outputting the mipmap image generated at 5,306 at a predetermined timing is provided, mipmap image data of one or more resolutions can be provided in real time by mipmap processing without increasing the circuit scale. There is an advantage that can be generated. Then, there is an advantage that texture mapping processing can be performed with high accuracy using the generated mipmap image data.

Further, the filter units 305 and 306
When n pixels are extracted, mipmap image data having one or a plurality of resolutions can be generated in more real time since the line is extracted by overlapping a line with adjacent n × n extracted pixels.

FIG. 10 is a diagram showing the degree of occurrence of aliasing noise. When the original (original) image data in which aliasing noise is generated as shown in FIG. 10A is reduced by the thinning process to the detail level LOD1 as in the related art, FIG.
As shown in (B), aliasing noise cannot be sufficiently removed. On the other hand, when the filter unit of the present invention is used, aliasing noise can be sufficiently removed as shown in FIG. Therefore, according to the image processing apparatus 1, an image obtained by the three-dimensional moving image signal generated by the rendering circuit 5 has a high quality in which aliasing at the time of reduction is suppressed.

In the mipmap processing, the reduced image may be strictly used up to the size of 1 × 1 pixel in the vertical and horizontal directions. Since it is considered that the video signal S2 is unlikely to occur, the video signal S2 is transmitted to an HDTV (High Definition).
n Television, 1920 × 1080 pixels) or SDT
V (Standard Definition Television, 720 × 525
In the case of a size of about (pixels), it is sufficient for the mipmap processing circuit 3 to generate mipmap image data of LOD levels “1”, “2”, and “3”.

[0076]

As described above, according to the present invention,
There is an advantage that mipmap image data having one or a plurality of resolutions can be generated in real time by mipmap processing without increasing the circuit scale. Then, there is an advantage that texture mapping processing can be performed with high accuracy using the generated mipmap image data.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration of an image processing system according to the present invention.

FIG. 2 is a block diagram more specifically showing a main part of the image processing apparatus shown in FIG. 1 including a flow of signals.

FIG. 3 is a diagram showing a specific configuration example of a mipmap processing circuit as the image generation device according to the present invention shown in FIGS. 1 and 2;

FIG. 4 is a timing chart for explaining an operation of a mipmap processing circuit as an image generation device according to the present invention.

FIG. 5 is a diagram for explaining processing of a 1/2 filter unit in a mipmap processing circuit as image generation according to the present invention.

FIG. 6 is a diagram for explaining processing of a フ ィ ル タ filter unit and a フ ィ ル タ filter unit in a mipmap processing circuit as image generation according to the present invention.

FIG. 7 is a diagram for explaining processing of a フ ィ ル タ filter unit in a mipmap processing circuit as image generation according to the present invention.

FIG. 8 is a diagram illustrating an example of writing mipmap image data to a texture memory in a memory space;

FIG. 9 is a diagram showing a configuration example of a texture memory shown in FIGS. 1 and 2;

FIG. 10 is a diagram illustrating a degree of occurrence of aliasing noise.

FIG. 11 is a diagram illustrating a texture mapping process.

FIG. 12 is a diagram for explaining a mipmap process.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Image processing apparatus, 2 ... Video signal generation circuit, 3 ... Mip map processing circuit, 4 ... Texture memory, 5 ... Rendering circuit, 6 ... Frame memory, 7 ... Display,
8 control circuit, 9 AV bus, 300 to 304 line buffer, 305 1/2 filter section, 306 1/4
Filter part, 307 to 309 ... buffer, 310 to 31
2. Asynchronous FIFO, 313 ... output circuit, 41, 42 ...
Physical memory, 43, 44... Bus.

 ────────────────────────────────────────────────── ─── Continued on the front page F term (reference) 5B047 AA07 AB04 EA07 EA09 EB03 5B057 AA20 CA01 CA08 CA12 CA16 CB01 CB08 CB13 CB16 CC02 CD05 CD09 CE16 CH01 CH11 DA16 5B080 CA06 FA02 GA22

Claims (22)

[Claims] 1. An image generating apparatus for receiving a textured original image data and generating a reduced mipmap image with a predetermined level of detail, comprising: data for one line of the original image data; At least three cascade-connected line buffers for sequentially transferring the held data in parallel, and receiving at least three consecutive lines of data held by each of the line buffers, a predetermined pixel based on the number n of input lines And extracting the n × n pixels centered at the center, weighting the extracted n × n pixels with weighted coefficients, and reducing the width and height of the texture with a predetermined level of detail to obtain the desired value. At least one filter unit for generating mipmap image data, and outputting at a predetermined timing the mipmap image generated by the filter unit Image generating apparatus having and. 2. The image generation apparatus according to claim 1, wherein the filter section extracts an n × n pixel by overlapping a line with an adjacent n × n extracted pixel. 3. The image according to claim 1, wherein the output unit includes a buffer that inputs the mipmap image data generated by the filter unit in synchronization with a video clock and outputs the mipmap image data with a clock faster than the video clock. Generator. 4. A filter for generating mipmap image data reduced with different degrees of detail, wherein the output unit outputs mipmap image data from the filter units at different timings. The image generating device according to claim 1, further comprising a circuit. 5. A plurality of filter units for generating reduced mipmap image data with different degrees of detail, wherein the output unit outputs the mipmap image data by the respective filter units at different timings. 3. The image generation device according to claim 2, further comprising a circuit. 6. The mip map generated by each filter unit such that the output circuit switches a base pointer in a memory space of a storage circuit to be output for each output of each filter unit, and is written for each line. 5. The image generation device according to claim 4, wherein the image data is selected and output. 7. The mip map generated by each filter unit such that the output circuit switches a base pointer in a memory space of a storage circuit to be output for each output of each filter unit, and is written for each line. 7. The image generating apparatus according to claim 6, wherein the image data is selected and output. 8. The image generation apparatus according to claim 1, wherein said line buffer inputs line data and performs parallel transfer in synchronization with a horizontal synchronization signal. 9. The image generating apparatus according to claim 2, wherein said line buffer inputs line data and performs parallel transfer in synchronization with a horizontal synchronization signal. 10. At least three cascade-connected line buffers for holding one line of image data and sequentially transferring the held data in parallel, and at least three continuous line buffers held in each line buffer. Upon receiving the data for the line, n × n pixels centered on a predetermined pixel based on the number n of input lines are extracted, and the extracted n × n pixels are extracted.
Color values are weighted averaged by weighted coefficients for n pixels,
At least one filter unit for reducing the width and height of the texture with a predetermined level of detail to generate desired mipmap image data, and an output unit for outputting the mipmap image generated by the filter unit at a predetermined timing And a storage circuit for storing the original image data and the mipmap image output from the image generation device; performing a texture mapping process based on the image data stored in the storage circuit and outputting An image processing apparatus comprising: an image processing circuit that generates an image. 11. The image generating apparatus according to claim 11, wherein
The image processing apparatus according to claim 10, wherein when extracting × n pixels, extraction is performed by overlapping a line with adjacent n × n extracted pixels. 12. The output unit of the image generation device includes a buffer that inputs the mipmap image data generated by the filter unit in synchronization with a video clock and outputs the mipmap image data with a clock faster than the video clock. The image processing apparatus according to claim 10. 13. The image generating apparatus according to claim 1, further comprising a plurality of filter units configured to generate mipmap image data reduced with different degrees of detail, wherein the output unit outputs the mipmap image data obtained by the filter units. The image processing apparatus according to claim 10, further comprising output circuits that output at different timings. 14. The image generating apparatus according to claim 1, further comprising a plurality of filter units configured to generate mipmap image data reduced with different degrees of detail, wherein the output unit outputs the mipmap image data obtained by the filter units. The image processing apparatus according to claim 11, further comprising output circuits that output at different timings. 15. The output circuit of the image generating apparatus switches the base pointer of the memory space of the storage circuit to be output for each output of each filter unit, and writes the data for each line in each filter unit. 14. The image processing apparatus according to claim 13, wherein the generated mipmap image data is selected and output. 16. The output circuit of the image generating apparatus switches a base pointer in a memory space of the storage circuit to be output for each output of each filter unit, and writes the data on a line-by-line basis in each filter unit. The image processing apparatus according to claim 14, wherein the generated mipmap image data is selected and output. 17. The image processing apparatus according to claim 10, wherein the line buffer of the image generation apparatus performs line data input and parallel transfer in synchronization with a horizontal synchronization signal. 18. The image processing apparatus according to claim 11, wherein the line buffer of the image generation apparatus performs line data input and parallel transfer in synchronization with a horizontal synchronization signal. 19. Receiving original texture image data,
An image generating method for generating a reduced mipmap image with a predetermined level of detail, wherein at least three lines of data of the original image data are
Holding n lines, extracting n × n pixels centered on predetermined pixels based on the number n of input lines based on the held data of at least three consecutive lines, and extracting the extracted n × n pixels An image generation method comprising weighted averaging of color values with weighted coefficients, reducing the width and height of a texture with a predetermined level of detail, and generating desired mipmap image data. 20. The image generating method according to claim 19, wherein, when extracting n × n pixels, the line is extracted by overlapping an adjacent n × n extracted pixel with a line. 21. At least three lines of data of one line of original image data are held, and a predetermined pixel based on the number n of input lines is centered based on the held data of at least three continuous lines. The n × n pixels are extracted, and the extracted n × n pixels are weighted averaged by a weighted coefficient, and the width and height of the texture are reduced with a predetermined degree of detail to obtain a desired mipmap image. An image processing method for generating data, storing original image data and generated mipmap image data in a storage circuit, and performing a texture mapping process based on the image data stored in the storage circuit to generate an output image. 22. The image processing method according to claim 21, wherein, when extracting n × n pixels, the line is extracted by overlapping a line with adjacent n × n extracted pixels.