JP2002350899A - Manufacturing method of liquid crystal display device - Google Patents

Abstract

(57) [Problem] To provide a manufacturing method capable of controlling the channel length by suppressing the spread of the channel length due to ashing when manufacturing using a halftone mask in the channel portion of the TFT. . A resist is formed on a channel region of a TFT using a halftone mask in the channel of the TFT.
Before removing a by ashing, the resist 8b is applied again, and then ashing is performed, so that the spread of the channel length can be suppressed. Further, by performing the ashing by anisotropic etching, it is possible to further suppress the spread of the channel length.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a thin film transistor (TFT) on an array substrate of a liquid crystal display device. In particular, TF
When forming the T portion, it can be applied when forming the channel portion using a halftone mask.

[0002]

2. Description of the Related Art In manufacturing a liquid crystal display device, an array process for regularly arranging TFTs on a glass substrate, that is, an arraying process, involves processing a glass substrate to form pixel electrodes, data signal electrodes, circuit elements (TFTs), and the like. This is a process of an array substrate configured to form each electrode on a glass substrate. This process is similar to a semiconductor manufacturing process in which a thin film transistor is formed and a semiconductor element is formed.

Conventionally, when forming a TFT, a gate insulating film and a channel active layer of a transistor are deposited after forming a gate electrode, and then a TFT region is formed by etching using a resist pattern, and then a source / drain electrode is formed. Deposition is performed, and then a mask is used twice to form source / drain electrodes by etching using a resist pattern.

In recent years, as one of the reductions in the array process,
It has been proposed to form a TFT region portion and a channel portion (separation of source / drain electrode portions) using a single mask by using halftone exposure for a channel portion when forming a source / drain portion of a TFT portion. I have.

FIG. 4A to FIG. 4D and FIG.
(D) TFT using the halftone mask
FIG. 6 is a sectional view in order of a forming process. Hereinafter, TFT formation will be described in detail with reference to FIGS.

[0006] First, the glass substrate 1
Undercoat S to prevent diffusion of impurities and the like
iO_TwoThe film 2 is deposited. Then, the SiO_TwoGame on membrane
Electrodes are deposited by sputtering, and photolithography is used.
Etching after pattern formation of gate electrode
The desired gate electrode 3 is formed (FIG. 4A). Next, before
On the gate electrode 3, a SiN film 4 as a gate insulating film and
Then, an a-Si film 5 is formed as a channel active layer. So
And n for connection with the source / drain electrodes ⁺-A-
By continuously forming the Si film 6 using the CVD method,
A cross-sectional structure as shown in FIG. In addition
n⁺−a-Si film 6 on the source film by sputtering.
A rain electrode 7 is deposited (FIG. 4C).

Thereafter, as shown in FIG. 4D, after the resist 8a is applied, the source / drain electrodes are completely exposed to light using a halftone mask (outside the TFT area).
Then, a partially exposed region (channel region between the source and drain electrodes) and a region not completely exposed (source / drain electrode region) are formed. Here, the normal mask is a mask formed by patterning a completely exposed region and a region that is not completely exposed. However, a “halftone mask” is defined as a completely exposed region and a partially exposed region. Refers to a mask that is patterned using areas that are not exposed to light.

The above description has been made by taking a positive resist as an example.

When the pattern of the TFT portion is formed in this manner, the resist 8a is partially exposed only in the resist 8a in the channel portion region between the source and drain electrodes. Become. Next, the source / drain electrode film is dry-etched using the resist pattern 8a as a mask, as shown in FIG. In this case, not only the source and drain electrode film 7 by dry etching, the n ⁺
-Etching is performed up to the a-Si film 6 and the a-Si film 5, and the SiN film 4, which is a gate insulating film, is used as a stopper. Thereafter, ashing is performed to remove the resist film on the channel portion, thereby forming a cross-sectional structure diagram as shown in FIG.

Next, in order to form a channel region of the TFT portion, a source / drain portion electrode 7 is formed by dry etching using the resist pattern 8a. At this time, in order to channel the active layer 5 is etched until the source-drain electrode 7 and the n ⁺ -a-Si film 6 by dry etching stopper, sectional view as shown in FIG. 5 (c) is formed . Finally, FIG.
As shown in (d), the resist 8a is wet-etched by removing the resist, so that the TFT 8
The formation is possible, and the number of steps can be reduced.

[0011]

In the method of forming a TFT using a halftone mask as described above, FIG.
As shown in (b), in the step of removing the resist film on the channel portion by ashing, the channel region is wider than the initial mask size in order to perform isotropic etching. Changes.

In particular, the channel length (source-drain interval) is a parameter that greatly changes the TFT performance, and it is necessary to obtain a desired channel length after dry etching. However, when the TFT is formed by the conventional method, there is a problem that the channel length is inevitably wider than the mask dimension as described above. There is a problem that the channel length cannot be formed.

According to the present invention, in order to solve the above-mentioned conventional problems, it is possible to suppress the spread of the channel length due to ashing and control the channel length when manufacturing the TFT using a halftone mask in the channel portion. It is an object of the present invention to provide a manufacturing method of a liquid crystal display device which is possible.

[0014]

In order to achieve the above object, a method of manufacturing a liquid crystal display device according to the present invention comprises the steps of: forming a thin film transistor (TFT) on an array substrate of the liquid crystal display device; And depositing a three-layer film of a gate insulating film, an a-Si film, and an N ⁺ -a-Si film on the gate electrode,
Further, a source / drain electrode is deposited on the three-layered film, and then a resist is applied, and exposure and development for forming the source / drain electrode are performed on a channel portion of the TFT using a mask using a halftone. A resist pattern for forming a drain is formed, thereafter, etching is performed to form a TFT region using a dry etching method, and then a resist is applied again, and then a resist pattern is formed by ashing for forming a channel portion of a TFT portion. It is characterized by forming.

In the above method, when the resist is applied again after the etching for forming the TFT region is performed, the resist film thickness is preferably set to 1.5 μm or less. A preferable lower limit of the resist film thickness is preferably 0.5 μm or more in consideration of uniformity of resist coating.

Further, in the above method, after performing etching for forming a TFT region, a resist is applied again, and then, when performing ashing for forming a channel portion of the TFT region, anisotropic etching is used. Is preferred.

[0017]

In the present invention, it is possible to suppress the spread of the channel length by applying a resist again before removing the resist on the channel region of the TFT portion by ashing and then performing ashing. Become.

Further, by performing the ashing by anisotropic etching, it is possible to further suppress the spread of the channel length.

Embodiments of the present invention will be described more specifically with reference to the drawings.

(Embodiment 1) FIGS. 1 to 3 are cross-sectional views in the order of steps of a manufacturing method of forming a TFT portion on an array substrate using a halftone mask according to Embodiment 1 of the present invention.

First, an undercoat S is formed on the glass substrate 1 to prevent diffusion of impurities and the like from the glass substrate 1.
It was deposited iO ₂ film 2. Thereafter, a gate electrode was deposited on the SiO ₂ film by sputtering, a pattern of the gate electrode was formed by photolithography, and then etching was performed to form a desired gate electrode 3 (FIG. 1A). Next, on the gate electrode 3, a SiN film 4 as a gate insulating film, an a-Si film 5 as a channel active layer, and n ⁺ -a-S for connection with source / drain electrodes.
By continuously forming the i-film 6 using the CVD method, a film having a cross-sectional structure as shown in FIG. 1B was formed. Further, a source / drain electrode 7 was deposited on the n ⁺ -a-Si film 6 by a sputtering method to form FIG. 1C.

Then, as shown in FIG. 1D, after the resist is applied, the source / drain electrodes are completely exposed to light using a halftone mask, and
A partially exposed region (a channel region between source / drain electrodes) and a region not completely exposed (a source / drain electrode region) were formed. Here, the halftone mask refers to a mask formed by using a region that is completely exposed, a region that is partially exposed, and a region that is not completely exposed.

In this manner, the TFT portion was formed in a pattern, and the resist 8a in the channel portion region between the source and drain electrodes was partially exposed to partially expose the resist 8a, so that the resist cross-sectional shape was reduced. The above is described as an example in the case of a positive resist.

Next, the source / drain electrode film is dry-etched using the resist pattern 8a as a mask, and a thin resist 8b is applied on the resist 8a pattern to form a sectional shape as shown in FIG. did. At this time, not only the source / drain electrode film 7 but also the n ⁺ -a-Si film 6 and the a-Si film 5 are etched by dry etching, and the SiN film 4 serving as a gate insulating film is used as a stopper. did. Here, it is desirable that the resist 8b has a resist film thickness that is side-etched when ashing is performed next.
It may be equal to or less than 1/2 of the source-drain interval. As an example, the resolution of the exposure device currently used for liquid crystal is 3 μm, and the resolution is 3 μm.
Is desirably 1.5 μm or less. Here, when a film thickness of 1.5 μm or more is applied to the pattern formed at the current exposure limit of 3 μm between the source and the drain, the resist 8a between the source and the drain produced by the halftone exposure is used as the resist. This is because the pattern is not formed because it is filled with 8b.

Thereafter, ashing is performed to remove the resist film on the channel portion.
A cross-sectional structure as shown in FIG. FIG. 2B shows a cross-sectional structure during etching where the resist 8b is just etched. Eventually,
By etching until the resist 8a on the channel region of the TFT portion disappeared, a resist shape as shown in FIG. 2C was obtained. At this time, as shown in FIG. 2C, the distance between the source and the drain is equal to the initially formed resist pattern 8a, so that it is possible to form a TFT without considering a dimensional change due to ashing.

By using anisotropic etching for the ashing, a TFT having a narrow channel length can be easily manufactured.

Next, in order to form a channel region of the TFT portion, source etching is performed by dry etching using the resist pattern 8a formed by the ashing.
The drain electrode 7 was formed. At this time, the source / drain electrodes 7 and the n ⁺ -a-
Since the etching was performed up to the Si film 6 and the channel active layer 5 was used as a stopper, a cross-sectional structure as shown in FIG. 2D was formed. Finally, as shown in FIG.
a is wet-etched by stripping the resist,
The TFT can be formed with a single mask, and the number of steps can be reduced.

[0028]

As described above, in the process reduction process using a halftone mask in the TFT channel portion of the present invention, the channel length can be formed exactly according to the mask dimension, and the TFT characteristics can be stabilized. Can be achieved. Further, the channel length can be made smaller than the exposure limit, thereby suppressing the spread of the channel length due to ashing and providing a manufacturing method capable of controlling the channel length.

[Brief description of the drawings]

FIGS. 1A to 1D are process cross-sectional views illustrating a manufacturing method according to a first embodiment of the present invention.

FIGS. 2A to 2D are process cross-sectional views illustrating a manufacturing method according to the first embodiment of the present invention;

FIG. 3 is a sectional view of a TFT array obtained by the manufacturing method according to the first embodiment of the present invention;

FIGS. 4A to 4D are process cross-sectional views showing a conventional manufacturing method.

FIGS. 5A to 5D are process cross-sectional views showing a conventional manufacturing method.

[Explanation of symbols]

1 glass substrate 2 SiO ₂ film (undercoat) 3 gate electrode 4 SiN film 5 a-Si film 6 n ⁺ -a-Si film 7 the source and drain electrodes 8a, 8b resist

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H092 JA24 JA31 JA34 KA05 MA15 MA19 NA27 NA29 5C094 AA21 AA43 BA03 BA43 CA19 DA14 DA15 EA04 EA07 EB02 FB12 FB14 FB15 5F110 AA16 BB01 CC07 DD02 DD13 EE44 FF03 GG15 GG03 HK25 HK33 HK34 QQ02 QQ04 QQ09

Claims (3)

[Claims] When forming a thin film transistor (TFT) on an array substrate of a liquid crystal display device, a gate electrode is formed on a glass substrate, and a gate insulating film, an a-Si film, A three-layer film of an N ⁺ -a-Si film is deposited, source / drain electrodes are further deposited on the three-layer film, a resist is applied, and a mask using halftone is applied to a channel portion of the TFT. Exposure and development for forming source / drain electrodes are performed using, a resist pattern for forming a source / drain is formed, and then etching for forming a TFT region is performed using a dry etching method. And forming a resist pattern by ashing for forming a channel portion of a TFT portion after the formation. Manufacturing method. 2. The method for manufacturing a liquid crystal display device according to claim 1, wherein the resist film thickness is set to 1.5 μm or less when the resist is applied again after the etching for forming the TFT region is performed. 3. The method according to claim 1, wherein after the etching for forming the TFT region is performed, a resist is applied again, and then, when performing ashing for forming a channel portion of the TFT region, anisotropic etching is used. 3. The method for manufacturing a liquid crystal display device according to item 2.