JP2002344261A - Cmos operational amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CMOS operational amplifier circuit that is suited for low voltage drive, can expand an input/output voltage range, and is capable of precise amplification. SOLUTION: The CMOS operational amplifier circuit comprises a first differential amplifier, having either a P-channel or an N-channel differential MOS transistor for receiving an input signal; a second differential amplifier having the other differential MOS transistor of either the P-channel or the N-channel for receiving the input signal; a current mirror circuit for generating a current output signal in response to the current value of each current output signal by receiving the current output signal of the first and second differential amplifiers; an output circuit for generating an output signal, in response to an input signal by receiving the current output signal in the current mirror circuit; and a switching circuit for stopping the operation of the first differential amplifier, when the first differential amplifier is in a dead zone operation region to the input signal for operating the second differential amplifier.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS operational amplifier circuit, and more particularly, to a wide range of input and output voltages in low-voltage driving, capable of high-accuracy amplification, and particularly to a comparison circuit and the like. The present invention relates to a CMOS operational amplifier circuit suitable for:

[0002]

2. Description of the Related Art A CMOS operational amplifier circuit is used for a system IC or the like in which analog signals and digital signals are mixed, and is suitable for use as a circuit for amplifying or comparing a small current on the order of μA. This type of circuit is usually
P channel MOS transistor or N channel MO
A configuration is adopted in which a differential amplifier having an S transistor as a pair is provided at the input stage, and the output current of the differential amplifier is transferred to the output side by a current mirror circuit. However, this kind of circuit
Since there is a dead zone corresponding to the threshold voltage of the source-gate of the MOS transistor with respect to the in-phase input, the input / output voltage cannot take a range from the ground GND to the power supply voltage VDD, and the dynamic range of the input / output is limited. .

To solve this kind of problem, a differential amplifier of a P-channel MOS transistor and an N-channel M
An invention in which a differential amplifier of an OS transistor is provided in an input stage is described in Japanese Patent Application Laid-Open No. 3-62712 "CMOS operational amplifier circuit". This is because a P-channel MOS transistor differential amplifier provided as an input stage and an N-channel MO
The S-transistor differential amplifier and the differential amplifier are simultaneously driven by an input signal, and their output currents are combined by a current mirror circuit. Thus, when one of the P-channel or N-channel differential amplifiers is in the dead band, the circuit obtains the output of the other differential amplifier to generate an output substantially eliminating the dead band, and Power supply voltage VDD from GND
A wide input / output dynamic range is ensured.

[0004]

A CMO that is driven simultaneously by providing such P-channel and N-channel differential amplifiers
In the S operational amplifier circuit, only the N-channel differential amplifier operates in the dead band of the P-channel differential amplifier, and conversely, only the P-channel differential amplifier operates in the dead band of the N-channel differential amplifier. Then, both differential amplifiers operate in a range excluding both dead zones. For this purpose, for example, the power supply voltage VDD is set to 1.8 V, the dead band voltage for the input signals of the N-channel and P-channel MOS transistors is set to 0.7 V, the transconductance Gm of the N-channel differential amplifier is set to GmN, and the P-channel If the transconductance Gm of the differential amplifier is Gmp,
Gm of the CMOS operational amplifier circuit is such that the voltage of the input signal is 0 to
In the range of 0.7V, Gm = Gmp, and 0.7V-
In the range of 1.1 V, Gm = GmN + GmP.
In the range of 1 V to 1.8 V, Gm = GmN, and the transconductance changes according to the voltage of the input signal. As a result, the gain bandwidth product (GB product) changes.

As described above, this CMOS operational amplifier circuit
The differential amplifier that operates according to the voltage of the input signal is different,
In addition, since the differential amplifier operates in each of the three operation ranges, a GB product (gain bandwidth product) is obtained depending on a voltage of an input signal.
Changes greatly. As a result, it is difficult to select an optimal phase compensation capacitor. If the selection of the phase compensation capacitor becomes difficult, there is a problem that the operational amplifier circuit easily oscillates. Further, the CMOS operational amplifier circuit having the above-described configuration has a problem in that a large difference in transconductance Gm occurs before and after the dead band at low power supply voltage, so that highly accurate amplification cannot be performed. SUMMARY OF THE INVENTION The present invention solves such a problem of the prior art, and provides a CMOS operational amplifier circuit suitable for low-voltage driving, capable of adopting a wide input / output voltage range, and capable of amplifying with high accuracy. The purpose is to provide.

[0006]

To achieve the above object, a CMOS operational amplifier according to a first aspect of the present invention is configured as follows.
A first differential amplifier having one of P-channel and N-channel differential MOS transistors receiving an input signal, and a second differential amplifier having one of P-channel and N-channel differential MOS transistors receiving the input signal That generates an output signal corresponding to the input signal in accordance with the output of the differential amplifier
A current mirror circuit for receiving a current output signal of each of the first and second differential amplifiers and generating a current output signal corresponding to a current value of the current output signal; An output circuit for receiving an output signal of the first differential amplifier and generating an output signal in accordance with the input signal; A switching circuit for stopping the operation of the differential amplifier and switching the operation for operating the second differential amplifier.

Further, in the configuration of the CMOS operational amplifier circuit according to the second invention, a first bias current generating circuit for supplying a first current value corresponding to a bias current value of a differential transistor of the first differential amplifier is provided. And a second bias current generating circuit that supplies a second current value corresponding to a bias current value of a differential transistor of the second differential amplifier, wherein the current mirror circuit includes a first differential amplifier. The bias current flowing through the differential transistor of the operational amplifier is flowed or sunk, and the bias current flowing through the differential transistor of the second differential amplifier is flowed or sunk, whereby the first and second bias currents flow. A current output signal of a differential amplifier is input thereto, and the switching circuit operates the first differential amplifier and outputs the second bias current from the second bias current generating circuit. The current sinks from flowing or the current mirror circuit in the current mirror circuit,
When the first differential amplifier enters or enters a dead zone operation region with respect to an input signal, the operation of the first differential amplifier and the second current value are stopped, and the second differential amplifier is stopped.
And the first bias current generating circuit allows the first current value to flow to the current mirror circuit or sinks from the current mirror circuit.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the first invention, a switching circuit is provided to operate a first differential amplifier so that the first differential amplifier enters a dead zone operation region with respect to an input signal, or Upon entering, the operation of the first differential amplifier is stopped and the second differential amplifier is operated. With this, CM
Gm of the OS operation amplification circuit becomes one of Gm, and the change of Gm with respect to the input signal is suppressed. Also,
Gm of the first and second differential amplifiers can be easily made substantially equal in design. Therefore, a change in Gm with respect to a change in the voltage of the input signal of the CMOS operational amplifier circuit having such a configuration is very small.

Further, in the second invention, first and second bias current generating circuits for generating respective bias currents of the differential transistors of the first and second differential amplifiers are provided. When the amplifier is operating, the bias current of the other differential amplifier is supplied from the bias current generation circuit to the current mirror circuit, or the bias current flows from the power supply that supplies the bias current to the current mirror circuit to the bias current generation circuit. Thus, even if the operation of the first and second differential amplifiers is switched, the bias current of the current mirror circuit hardly changes. As a result, Gm of the current mirror circuit receiving the current outputs of the first and second differential amplifiers can be kept substantially constant. Thus, the change in Gm of the CMOS operational amplifier circuit can be further suppressed. As a result, it is possible to easily realize a CMOS operational amplifier circuit that is suitable for low-voltage driving, has a wide input / output voltage range, and can amplify with high accuracy.

[0010]

FIG. 1 is a block diagram of an embodiment of a CMOS operational amplifier circuit to which the present invention is applied, and FIG.
It is a block diagram of other examples. In FIG. 1, the CMO
The S operational amplifier circuit 10 has, as input stages, a differential amplifier 1 and a differential amplifier 2 each receiving an input signal. The differential amplifier 1 has a constant current source 1a on the upstream side, and includes P-channel differential MOS transistors P1 and P2 connected to the power supply line VDD via the constant current source 1a. Differential amplifier 2
Has a constant current source 2a on the downstream side and includes N-channel differential MOS transistors N1 and N2 connected to the ground GND via the constant current source 2a. Further, the CMOS operational amplifier circuit 1
0 is a changeover switch circuit 3 and a current mirror circuit 4
a and 4b are stacked vertically in a cascode connection type current mirror circuit 4; current sources 5 and 6; current sources 5a and 5b are provided between the current mirror circuits 4b downstream of the current sources. It comprises bias circuits 7a, 7b, 7c and an output stage amplifier (AMP) 8.

Note that the output stage amplifier 8 is
Is a phase compensation capacitor, and 8a is an output terminal. The current sources 5 and 6, the current sources 5a and 5b, and the input-side transistors and the output-side transistors of the current mirror circuits 4a and 4b are paired as shown in FIG. It is subordinately connected to GND in the vertical direction. The current sources 5 and 6 and the current sources 5a and 5b are cascode-connected constant current sources stacked in two. The current sources 5 and 6 supply a bias current to the current mirror circuit 4 and A common power supply for supplying a bias current to the differential MOS transistors N1 and N2 of the differential amplifier 2 as well.

The differential amplifier 1 is a P-channel differential amplifier, which operates by receiving a bias current having a current value Io from an upstream constant current source 1a, and has a gate of a transistor P1 having a non-inverting input terminal (+ input). 11a to receive an input signal. Its operating range is from GND to (VDD-Vth1). Here, Vth1 is a threshold voltage between the source and the gate of the P-channel transistors P1 and P2. 11b is an inverting input terminal (-input), which is connected to the gate of the transistor P2. Here, the current value of the constant current source 1a is represented by I
o, the constant current source 5 connected to the power line VDD,
The current value of No. 6 is also set to be Io. The differential amplifier 2 is an N-channel differential amplifier, and when the constant current source 2a is in the operating state, the upstream constant current source 5,
6, the transistors N1 and N2 which are differential
It operates in response to a bias current of o / 2, and a bias current of a current value Io flows to the downstream constant current source 2a. The gate of the N-channel transistor N1 is a non-inverting input terminal (+ input) 1
1a receives an input signal. Its operating range is (GND
+ Vth2) to VDD. Here, Vth2 is a threshold voltage between the source and the gate of the N-channel transistor.
The gate of the transistor N2 is connected to the inverting input terminal 11
b. When the outputs of these two differential amplifiers 1 and 2 are combined by a stacked cascode-connected current mirror circuit 4, the operation range is changed from GND to VDD, and a wide dynamic range can be realized.

The current mirror circuit 4 is connected to a ground GND.
Between the current mirror circuits 4a and 4
b is a circuit stacked in this order, and the current mirror circuit 4a includes an N-channel MOS transistor N7,
Consists of N8. The current mirror circuit 4b includes N-channel MOS transistors N5 and N6. The current source 5a includes a P-channel MOS transistor P3,
The current source 5b includes a P-channel MOS transistor P4, and the bases of these transistors are commonly connected. The transistor P3 of the cascode-connected current source 5a is connected to the upstream constant current source 5 connected to the power supply line VDD.
And a bias current of Io (or Io / 2 when the differential amplifier 2 operates), the transistor P4 of the cascode-connected current source 5b is connected to the upstream constant current connected to the power supply line VDD. Current value I from source 6
o (or Io / 2 when differential amplifier 2 operates)
It operates by receiving the bias current of. The bases of the transistors P3 and P4 are commonly connected and receive a bias voltage Vb2 from the bias circuit 7b. The transistors N5 and N6 of the current mirror circuit 4b provided downstream thereof are connected to the corresponding upstream transistor P
3, the bias current is received from P4, and the current is sinked to the corresponding downstream transistors N7, N8.
The bases of these transistors N5 and N6 are commonly connected, and the bases thereof are connected to a bias voltage V from a bias circuit 7c.
b3 is given.

The gates of the transistors N7 and N8 of the current mirror circuit 4a are commonly connected, the gate is connected to the drain side of the transistor N5, and the respective drains are connected to the transistors P1 and P1 of the differential amplifier 1.
Transistors N7 and N8 are connected corresponding to the respective drains of P2 and serve as active loads of the differential amplifier 1. Therefore, when the differential amplifier 1 is operating, the bias current of the differential amplifier 1 and the bias currents from the current sources 5 and 6 flow through the transistors N7 and N8. The current mirror circuit 4b and the current source 5b form a CMOS, and the connection point between the drain of the transistor P4 of the current source 5 and the drain of the transistor N6 of the current mirror circuit 4b is connected to the output terminal 4d. Terminal 4
The output stage amplifier 8 is connected to the input of the output stage amplifier 8 via d, and is driven by the current output signal of the current mirror circuit 4. Since the differential amplifier 1 and the differential amplifier 2 perform inversion operations in opposite directions to each other with respect to an input signal, the current mirror circuit 4 also includes a pair of transistors forming a current mirror by the connection described above. , And the combined output of the differential amplifier 1 and the differential amplifier 2 is taken out from the output terminal 4d of the current mirror circuit 4.

Here, the constant current source 2a is an N-channel MO
The current mirror circuit is composed of S transistors N3 and N4. The drain of the transistor N4 on the current mirror output side is commonly connected to the sources of the transistors N1 and N2, and the transistor N3 on the current mirror input side.
Is provided with a constant current source 1a of the differential amplifier 1. The constant current source 2a receives a bias current (current value Io) from the constant current source 1a via the P-channel MOS transistor P5 when it is turned on via its source-drain. The changeover switch circuit 3 comprises this transistor P5, and its gate is connected to the bias circuit 7a.
To which a bias voltage Vb1 is applied. Thereby, the changeover switch circuit 3 performs a switching operation in accordance with the rise of the source voltage.

That is, the bias voltage Vb1 corresponds to the voltage on the output side of the constant current source 1a when the voltage of the input signal of the differential amplifier 1 becomes a dead band voltage or enters the dead band voltage. The transistor P5 is set to be turned on when the dynamic amplifier 1 enters the dead zone operation or when the dynamic amplifier 1 enters the dead zone operation. Transistor P5
Operates as a normally OFF switching element, and when the transistor P5 is OFF, the bias current Io of the current source 1a flows through the differential amplifier 1 composed of the transistors P1 and P2. On the other hand, transistor P5 is ON
When the switch is ON, the bias current Io of the current source 1a flows to the input transistor N3 of the current mirror circuit composed of the transistors N3 and N4, and the output mirror current flows through the transistors N1 and N2. The bias current of the differential amplifier 2 flows through the transistor N4 of the constant current source 2a of the differential amplifier 2,
To work. As a result, when the differential amplifier 1 enters the dead zone operation or enters the dead zone operation, the operation of the differential amplifier 1 stops, the differential amplifier 2 operates, and the operation switches. Conversely, when the voltage of the input signal of the differential amplifier 1 is no longer the dead band voltage, the transistor P5 is turned off.
Since the FF is performed, the operation of the differential amplifier 2 stops, the differential amplifier 1 operates, and the operation switches.

By switching the bias current from the differential amplifier 1 to the differential amplifier 2 or vice versa,
The transistor P5 is a switching circuit that prevents the two differential amplifiers 1 and 2 from operating at the same time and selects one of the differential amplifiers. Thus, the bias circuit 7a here may use a comparator. This comparator is a circuit for comparing a voltage of an input signal with a reference voltage of a voltage (VDD-Vth1) and generating a switching signal for turning on the transistor P5, and switches the operation from the differential amplifier 1 to the differential amplifier 2. Or, conversely, it is a circuit for generating a switching signal for switching the operation. Here, assuming that the transconductance Gm of the N-channel differential amplifier 2 is GmN and the transconductance Gm of the P-channel differential amplifier 1 is GmP, the transconductance Gm of the CMOS operational amplifier circuit 10 is equal to the voltage of the input signal. Is 0V
The differential amplifier 1 operates to reach GmP up to the voltage Vf which enters the dead zone of the P-channel differential amplifier 1, and the power supply line VD
Up to the voltage of D, the N-channel differential amplifier 2 operates to reach GmN. Here, since the difference between GmP and GmN is small, the CMOS operational amplifier circuit 10 can amplify the input signal with high accuracy, and since there is no large step difference in Gm, the optimal phase compensation capacitor Cc can be used. You can choose.

Furthermore, to make GmP of the differential amplifier 1 composed of P-channel transistors equal to GmN of the differential amplifier 2 composed of N-channel transistors,
Easy on design. Here, Gm of the differential amplifier 1
And Gm of the differential amplifier 2 are substantially equal.
Gm of the cascode connection type current mirror circuit 4 is the bias current ID of the cascode connection type current mirror circuit 4.
, The bias current ID flowing through each transistor of the current mirror pair is preferably constant. However, in the embodiment shown in FIG. 1, the bias current ID of the P-channel transistors P3 and P4 and the cascade connection type current mirror circuit 4 composed of the N-channel transistors N5, N6, N7 and N8 causes the differential amplifier 1 and It changes by switching 2. In other words, it changes according to the voltage of the input signal. As a result, the transconductance Gm of the current mirror circuit 4 changes.

This problem is solved by the CMOS operational amplifier circuit 20 of the embodiment shown in FIG. The difference from the configuration in FIG. 1 lies in that a bias current adjusting circuit 9 is newly provided for the cascode connection type current mirror circuit 4. The reason for this is that, in the embodiment of FIG. 1, the differential amplifier 1 of FIG. 1 uses the transistors N7 and N8 of the current mirror circuit 4 as loads when the differential amplifier 1 of FIG. To apply a current to the current mirror circuit 4. Thus, the differential amplifier 1 inputs a current output signal corresponding to the input signal to the current mirror circuit 4. On the other hand, when the differential amplifier 2 is operating, the operational amplifier uses the current sources 5, 6 of the current mirror circuit 4 as loads to load the transistors P3, P4 of the current sources 5a, 5b cascode-connected thereto. And a part of the current flowing through the current mirror circuit 4 is extracted. Thereby, the differential amplifier 2
Inputs a current output signal corresponding to the input signal to the current mirror circuit 4.

That is, since the current mirror circuit 4 has loads of the differential amplifiers 1 and 2 and the directions of the bias currents flowing through these loads are different, when the differential amplifier 1 is operating ( At this time, the bias current ID flowing through the current mirror circuits 4a and 4b differs between when the differential amplifier 2 does not operate) and when the differential amplifier 2 operates. In order to make the bias current ID constant, a bias current adjusting circuit 9 is provided here.
When the operation of the bias current flowing through the current mirror circuit 4 is switched from the differential amplifier 1 to the differential amplifier 2 or vice versa, the bias current ID flowing through the current mirror circuits 4a and 4b substantially decreases. Adjust so that they are equal. Bias current adjustment circuit 9
Is a dummy operation circuit 9 that operates equivalently to the differential amplifier 1.
a, a bias current generating circuit 9b that operates equivalently to the differential amplifier 2 and generates a bias current; a constant current source 9c having a current value Io equal to the constant current source 1a of the differential amplifier 1; And a switch circuit 9d that performs a switching operation substantially simultaneously to generate a bias operation current equivalent to that of the differential amplifier 1. Here, when the differential amplifier 1 is operating, the bias current adjusting circuit 9 simultaneously operates the dummy operation circuit 9 a to generate the same bias operation current as the differential amplifier 2, and outputs the bias current from the current mirror circuit 4. Sinks current for minutes. As a result, the current mirror circuit 4 is set to a state where the same bias current flows as the state where the differential amplifier 2 is operating.

When the differential amplifier circuit 1 enters the dead zone, the operation is switched to the differential amplifier 2 and the differential amplifier 2 operates.
Operates a switching switch circuit 9d for stopping the operation of the dummy operation circuit 9a (which operates the same as the switching switch circuit 3) to switch a bias current equal to the bias current of the differential amplifier 1 from the constant current source 9c. The current is supplied to the current mirror circuit 4 via the switch circuit 9d. As a result, the current mirror circuit 4 is set to a state where the same bias current flows as the state where the differential amplifier 1 is operating. The dummy operation circuit 9a includes a constant current source 9 having the same current value Io as the constant current source 1a.
The differential amplifier 11 is composed of P-channel MOS transistors P6 and P7 whose sources are commonly connected to c, and an input transistor N9 of a current mirror connection commonly provided downstream of these transistors as an active load thereof. Become. The constant current source 9c is connected to the power supply line VDD, is connected to the dummy operation circuit 9a and the changeover switch circuit 9d, and supplies the bias current Io to one of them. The gates of the transistors P6 and P7 of the dummy operation circuit 9a are connected to the non-inverting input terminal 20a and the inverting input terminal 2 similarly to the gates of the transistors P1 and P2 of the differential amplifier 1, respectively.
0b. The gates of the transistors N1 and N2 of the differential amplifier 2 are also connected to the non-inverting input terminal 20a and the inverting input terminal 20b, respectively.

The bias current generating circuit 9b includes an output-side N-channel M that is current-mirror-connected to the transistor N9.
It comprises OS transistors N10 and N11, and generates a sink current of Io / 2 by reducing the capacity ratio or W / L ratio of these transistors to 1/2 with respect to the transistor N9. The drains of the transistors N10 and N11 are connected to the current sources 5 and 6, and the respective sources are grounded. Thus, the current Io / 2 is sinked from the current sources 5 and 6 when the differential amplifier 1 is operating. This sink current value Io / 2 corresponds to the respective bias currents Io / 2 of the differential pair transistors N1 and N2 of the differential amplifier 2. That is, the dummy operation circuit 9a and the bias current generation circuit 9b generate the bias current value corresponding to the bias current value of the differential amplifier 2 when the differential amplifier 1 is operating, according to the second invention. Of the bias current generating circuit of FIG.

The switch circuit 9d is composed of P-channel MOS transistors P8 and P9, is a switch circuit similar to the transistor P5, and is formed as an equivalent transistor (pair transistor). Each gate is connected to receive the voltage Vb1 from the bias circuit 7a in the same manner as the transistor P5. Thus, the transistor P5 and the three transistors P8 and P9 are simultaneously turned on / off. The sources of the transistors P8 and P9 are
Both are connected to the constant current source 9c, the drain of the transistor P8 is connected to the drain of the transistor N7 of the current mirror circuit 4, and the drain of the transistor P9 is
It is connected to the drain of the transistor N8 of the current mirror circuit 4. Transistor P of switch circuit 9d
8, P9 are turned on simultaneously with the transistor P5 when the differential amplifier 1 operates in the dead zone. At this time, upon receiving a current value Io from the constant current source 9c provided upstream and connected to the power supply line VDD, each receives the current Io / 2 as a bias current for the transistors N7 and N8 of the current mirror circuit 4 of the downstream circuit. Spill into each. That is, here, the changeover switch circuit 9d itself is a circuit that generates the bias current Io / 2 of each of the differential pair transistors P1 and P2 of the differential amplifier 1. That is, the constant current source 9c and the switch circuit 9d constitute a first bias current generation circuit according to the second invention for generating a bias current value corresponding to the bias current value of the differential amplifier 1.

Thus, when the differential amplifier 1 is operating (the differential amplifier 2 does not operate at this time), the dummy operation circuit 9a also operates at the same time, and the bias current ID flowing through the transistor of the current mirror circuit 4 is reduced. And Io / 2 as a bias operation current from the current sources 5 and 6 is sunk by the transistors N10 and N11. Therefore, the current mirror circuits 4a and 4b have the same bias current as when the differential amplifier 2 is operating from the upstream side. Will be supplied. On the other hand, the operation of the differential amplifier 1 stops and the differential amplifier 2
Operates, the P-channel MOS transistors P8 and P9 change from OFF to ON, the operation of the dummy operation circuit 9a also stops, and Io / 2 as the bias operation current.
Is sinked by the transistors P8 and P9 from the constant current source 9c which supplies the same current as the constant current source 1a, and flows to the transistors N7 and N8 downstream of the current mirror circuit 4,
Bias operating current I when differential amplifier 1 is operating
o / 2 is supplied to the current mirror circuit 4a. As a result, the bias current ID flowing through each transistor of the current mirror pair of the current mirror circuits 4a and 4b does not change whether the differential amplifier 1 operates or the differential amplifier 2 operates.

As described above, as described above, the bias circuit 7a of this embodiment is a circuit for generating a switching signal. Therefore, the voltage of the input signal is changed to the voltage (VDD-Vth
A comparator that generates a switching signal for turning on the transistor P5 by comparing 1) with the reference voltage can be used. When this comparator is used, the switch circuit 9d of the bias current adjusting circuit 9 of the embodiment can also be operated by the switch signal of this comparator. Further, at this time, the dummy operation circuit 9a that operates equivalently to the differential amplifier 1 can be simply replaced with a bias current generation circuit that generates or sinks a bias current equivalent to the differential amplifier 1.
A first bias current generating circuit that supplies a first current value corresponding to a bias current value of the differential transistor of the first differential amplifier according to a switching signal of the comparator;
By switching between the second bias current generating circuit for supplying a second current value corresponding to the bias current value of the differential transistor of the differential amplifier 2, the switch circuit 9d becomes unnecessary.

[0026]

As described above, according to the present invention, the switching circuit is provided to operate the first differential amplifier so that the first differential amplifier enters a dead zone operating region with respect to an input signal, or Upon entering, the operation of the first differential amplifier is stopped and the second differential amplifier is operated. This allows C
Gm of the MOS operational amplifier circuit becomes one of Gm, and the change of Gm with respect to the input signal is suppressed. Also,
Gm of the first and second differential amplifiers can be easily made substantially equal in design. Therefore, a change in Gm with respect to a change in the voltage of the input signal of the CMOS operational amplifier circuit having such a configuration is very small. As a result, it is possible to easily realize a CMOS operational amplifier circuit that is suitable for low-voltage driving, has a wide input / output voltage range, and can amplify with high accuracy.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a CMOS operational amplifier circuit to which the present invention is applied.

FIG. 2 is a block diagram of another embodiment thereof.

[Explanation of symbols]

1, 2, 11 ... differential amplifier, 3 ... changeover switch circuit,
4, 4a, 4b ... current mirror circuit, 5, 6, 9c ...
Constant current source, 7a, 7b, 7c: bias circuit, 8: output stage amplifier, 9: bias current setting circuit, 9a: dummy operation circuit, 9b: bias current generation circuit, 9d: changeover switch circuit, 10, 20: CMOS Operational amplifier circuit, P1 ~
P9: P-channel transistor; N1 to N11: N-channel transistor.

Claims (16)

[Claims] A first differential amplifier having a P-channel or N-channel differential MOS transistor for receiving an input signal; and a P-channel or N-channel differential MOS for receiving the input signal. And a second differential amplifier having a transistor, wherein the first and second differential amplifiers generate an output signal corresponding to the input signal in accordance with an output of the differential amplifier. A current mirror circuit for receiving a current output signal of each of the above and generating a current output signal corresponding to the current value of each of the current output signals; and receiving an output signal of the current mirror circuit to generate an output signal corresponding to the input signal. An output circuit that generates the first differential amplifier when the first differential amplifier enters or enters a dead zone operating region with respect to the input signal. CMOS operational amplifier circuit, characterized in that it comprises a switching circuit is stopped for switching the operation for operating the second differential amplifier the operation of the differential amplifier. 2. An operation for stopping the operation of the second differential amplifier and operating the first differential amplifier when the first differential amplifier comes out of the dead zone operation region. 2. The CMOS operational amplifier circuit according to claim 1, wherein the switching is performed. 3. The differential amplifier of claim 1, wherein the first differential amplifier has a first current source for flowing an operating current of the differential MOS transistor of the first differential amplifier, and the second differential amplifier has a differential current of the own differential MOS transistor. A second current source for flowing an operating current of the transistor, wherein the switching circuit is a circuit for shunting the current of the first current source; The operation of the first differential amplifier is stopped to operate the second differential amplifier circuit, and conversely, the entire current of the first current source is caused to flow through the first differential amplifier. 1
3. The CMOS operational amplifier circuit according to claim 2, wherein the differential amplifier is operated to stop the operation of the second differential amplifier circuit. 4. The switching circuit according to claim 1, wherein the switching circuit is a MOS transistor having a gate connected to a predetermined voltage line corresponding to a voltage entering the dead zone operation region, and having a source or a drain connected to the first current source. 4. The CMOS operational amplifier circuit according to claim 3, wherein: 5. The differential MOS transistor of the first differential amplifier is a P-channel, and the differential MOS transistor of the second differential amplifier is an N-channel. Gm of the second differential amplifier is substantially equal, the first and second current sources are constant current sources, and the MOS transistor of the switching circuit is a P-channel transistor; A source is connected to the first current source, and when the first differential amplifier enters or enters a dead zone operation region with respect to the input signal, the first differential amplifier turns from OFF to ON and outputs from the first current source. The current of the first current source flows out from the drain through the source thereof, and the current of the second current source flows in accordance with the current from the drain of the MOS transistor. CMOS operational amplifier circuit according to claim 4 wherein operating the serial second differential amplifier circuit. 6. The apparatus further comprises third and fourth constant current sources,
In the current mirror circuit, a plurality of current mirrors are vertically stacked between a power supply line and a ground line,
A vertically cascaded circuit in which the input side transistor is connected to the power supply line via the third constant current source, and the output side transistor is connected to the power supply line via the fourth constant current source. And the currents of the third and fourth constant current sources are equal to the differential MO of the second differential amplifier.
6. The CMOS operational amplifier circuit according to claim 5, wherein the bias current is shunted to the S transistor as a bias current. 7. The first differential amplifier uses a current mirror on the ground line side of the plurality of current mirrors of the current mirror circuit as a load, and the second differential amplifier includes a third current amplifier. 7. The CMOS operational amplifier circuit according to claim 6, wherein the load is a load of the fourth constant current source. 8. A bias current outflow circuit for flowing out a first current value corresponding to a bias current value of a differential transistor of the first differential amplifier, and a bias current outflow circuit of the second differential amplifier. A bias current sink circuit that sinks a second current value corresponding to a bias current value, wherein the switching circuit further includes the third and fourth switching circuits when the first differential amplifier is operating. Flowing a current of the second current value from the constant current source to the bias current sink circuit;
When the first differential amplifier has stopped operating, the current of the second current value is stopped, and the current of the first current value is transferred from the bias current outflow circuit to a current mirror on the ground line side. 8. The CMOS operational amplifier circuit according to claim 7, wherein a current flows. 9. A first bias current generating circuit for supplying a first current value corresponding to a bias current value of a differential transistor of the first differential amplifier, and a differential transistor of the second differential amplifier. And a second bias current generating circuit for supplying a second current value corresponding to the bias current value of the first differential amplifier. The current mirror circuit receives a bias current flowing through a differential transistor of the first differential amplifier. Alternatively, a current output signal of the first and second differential amplifiers is input by being sunk and a bias current flowing through a differential transistor of the second differential amplifier being flown or sunk. And the switching circuit further comprises the first
When the differential amplifier operates, the second current value flows from the second bias current generating circuit to the current mirror circuit or sinks from the current mirror circuit, 2. The method according to claim 1, wherein the second current value is stopped when the operation is stopped, and the first current value is supplied from the first bias current generation circuit to the current mirror circuit or is sinked from the current mirror circuit. 2. The CMOS operational amplifier circuit according to 1. 10. An operation for stopping the operation of the second differential amplifier and operating the first differential amplifier when the first differential amplifier comes out of the dead zone operation region. 10. The CMOS operational amplifier circuit according to claim 9, wherein switching is performed. 11. The first differential amplifier has a first current source for flowing an operation current of the differential MOS transistor of the first differential amplifier, and the second differential amplifier has a differential current of the own differential MOS transistor.
A second current source for flowing an operating current of the transistor, wherein the switching circuit includes a first current source for shunting the current of the first current source;
, And a second switching circuit for selectively operating one of the first bias current generating circuit and the second bias current generating circuit, wherein the first switching circuit comprises the first current 11. The CMOS operational amplifier circuit according to claim 10, wherein the operation of the first differential amplifier is stopped and the second differential amplifier circuit is operated by flowing all the current of the source. 12. The differential MOS transistor of the second differential amplifier further comprises third and fourth constant current sources, wherein the differential MOS transistor of the first differential amplifier is a P-channel.
The transistor is N-channel, Gm of the first differential amplifier and Gm of the second differential amplifier are substantially equal, and the current mirror circuit vertically extends between a power supply line and a ground line. A plurality of current mirrors are stacked, the input side transistor is connected to the power supply line via the third constant current source, and the output side transistor is connected to the power supply line via the fourth constant current source. 12. The circuit according to claim 11, wherein the currents of the third and fourth constant current sources are shunted to a differential MOS transistor of the second differential amplifier as a bias current thereof. CMOS operational amplifier circuit. 13. The first bias current generation circuit is a current outflow circuit for flowing out a bias current to the current mirror circuit, and the second bias current generation circuit is
13. The CMOS operational amplifier circuit according to claim 12, wherein the CMOS operational amplifier circuit is a bias current sink circuit that sinks current from the third and fourth constant current sources of the current mirror circuit. 14. A fifth constant current source for generating a current value substantially equal to a current value of said first constant current source, wherein said first switching circuit comprises a first constant current source. The operation of the first differential amplifier is stopped by flowing all the current of the current source to operate the second differential amplifier circuit, and conversely, the entire current of the first constant current source is reduced to the The first differential amplifier is operated by flowing the current through a MOS transistor of a first differential amplifier to stop the operation of the second differential amplifier circuit. First
The bias current sink circuit is operated and the operation of the bias current outflow circuit is stopped by causing the current of the fifth constant current source to flow to the bias current sink circuit at substantially the same time as the switching circuit. 14. The method according to claim 13, wherein the bias current outflow circuit is operated and the operation of the bias current sink circuit is stopped by flowing all the current of the constant current source to the bias current outflow circuit. CMOS operational amplifier circuit. 15. The current mirror circuit according to claim 1, wherein
The bias current sink circuit includes a circuit connected to the fifth constant current source, which performs an equivalent dummy operation of the first differential amplifier, and a second current mirror circuit. 15. The CMOS operational amplifier circuit according to claim 14, wherein the current mirror circuit is connected to the third and fourth constant current sources. 16. The first differential amplifier, wherein, among the plurality of current mirrors of the first current mirror circuit, a current mirror on the ground line side is used as a load, and the second differential amplifier comprises: 16. The CMOS operational amplifier circuit according to claim 15, wherein said third and fourth constant current sources are loads.