JP2002343901A - CSP manufacturing method - Google Patents
CSP manufacturing methodInfo
- Publication number
- JP2002343901A JP2002343901A JP2001147781A JP2001147781A JP2002343901A JP 2002343901 A JP2002343901 A JP 2002343901A JP 2001147781 A JP2001147781 A JP 2001147781A JP 2001147781 A JP2001147781 A JP 2001147781A JP 2002343901 A JP2002343901 A JP 2002343901A
- Authority
- JP
- Japan
- Prior art keywords
- printed circuit
- circuit board
- hole
- conductive material
- csp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
(57)【要約】
【課題】 プリント回路板を積層して作製されるＣＳＰ
は各プリント回路板のスルーホール形成と該スルーホー
ルの導電性物質による充填に手間が掛かっていたため生
産性が低く、より効率的なＣＳＰの製造方法が要請され
ている。
【解決手段】 スルーホール６，７形成と該スルーホー
ルの導電性物質８による充填を、ポンチ５によるパンチ
ング等の単一の操作で行う。これにより各ユニットプリ
ント回路板12が簡便に即ち短時間で作製できて、各ユニ
ットプリント回路板作製時間の短縮分と枚数を掛け合わ
せた時間分だけ効率的にＣＳＰを製造できる。
(57) [Summary] CSP manufactured by laminating printed circuit boards
Since it is troublesome to form through holes in each printed circuit board and fill the through holes with a conductive material, there is a demand for a more efficient CSP manufacturing method with low productivity. SOLUTION: The formation of through holes 6 and 7 and the filling of the through holes with a conductive substance 8 are performed by a single operation such as punching with a punch 5. As a result, each unit printed circuit board 12 can be manufactured simply, that is, in a short time, and the CSP can be efficiently manufactured by the time obtained by multiplying the reduced number of unit printed circuit board manufacturing times by the number of sheets.
Description
【０００１】[0001]
【発明が属する技術分野】本発明は、プリント回路板を
積層して成るＣＳＰ(以下ＣＳＰという)の製造方法に関
し、より詳細には高生産性でＣＳＰを製造するための方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a CSP (hereinafter referred to as a CSP) formed by laminating printed circuit boards, and more particularly to a method for manufacturing a CSP with high productivity.
【０００２】[0002]
【従来の技術】表裏面又は一方面に配線パターンを有す
る回路板として種々のものが使用されている。具体的に
は、基板にフレキシブルなポリイミド樹脂等を用いたＴ
ＡＢ（Tape Automated Bonding) テープ、ＣＳＰ(Chip
Size Package) 、ＢＧＡ（BallGrid Array ）、ＦＰＣ
（Flexible Printed Circuit）の他に、ガラスエポキシ
等のリジッドな基板を使用した多層配線板等がある。こ
の配線パターンを有するプリント回路板は、例えば次の
ようにして製造される。2. Description of the Related Art Various types of circuit boards having a wiring pattern on the front and back surfaces or one surface are used. More specifically, T using a flexible polyimide resin or the like for the substrate
AB (Tape Automated Bonding) tape, CSP (Chip)
Size Package), BGA (BallGrid Array), FPC
In addition to (Flexible Printed Circuit), there is a multilayer wiring board using a rigid board such as glass epoxy. A printed circuit board having this wiring pattern is manufactured, for example, as follows.
【０００３】まず両面銅貼りポリイミドフィルム製テー
プの所定個所にプレスによりスプロケットホールを形成
する。次いでポリイミドテープの表面側を整面した後に
配線パターンに対応するように該フィルムの表面側にフ
ォトレジストを塗布し露光及び現像を行ってエッチング
マスクを製造し、このマスクを使用してフィルム表面の
銅のエッチングを行って配線パターンを形成する。続い
てポリイミドテープの裏面側も同様にして、整面−フォ
トレジスト塗布−露光−現像−エッチングを行って配線
パターンを形成する。このようにして配線パターンが表
裏面に形成されたポリイミドテープの所定個所にパンチ
ングプレス機によりスルーホールを開口させる。次いで
ポリイミドテープの表裏面に、例えばスズ−銀材合金や
スズ−銅合金材等の導電性材料を重ね、再度パンチング
プレスすることにより、該導電性材料を前記スルーホー
ル中に埋め込み、更にパンチングプレス機で加締めるこ
とにより表裏面の配線パターンを電気的に接続する。直
径100μｍ程度のスルーホールでは導電性材料を埋め込
むことにより、理想的な電気的接続のプリント回路板が
得られる。[0003] First, sprocket holes are formed at predetermined locations on a double-sided copper-coated polyimide film tape by pressing. Next, after adjusting the surface side of the polyimide tape, a photoresist is applied to the surface side of the film so as to correspond to the wiring pattern, and exposure and development are performed to produce an etching mask. A wiring pattern is formed by etching copper. Subsequently, a wiring pattern is formed on the back side of the polyimide tape in the same manner as described above, by performing surface adjustment, photoresist application, exposure, development, and etching. Through holes are opened at predetermined positions of the polyimide tape on which the wiring patterns are formed on the front and back surfaces by a punching press. Next, a conductive material such as a tin-silver alloy or a tin-copper alloy material is superimposed on the front and back surfaces of the polyimide tape, and the punched press is performed again to embed the conductive material in the through-holes. The wiring patterns on the front and back surfaces are electrically connected by caulking with a machine. By embedding a conductive material in a through hole having a diameter of about 100 μm, a printed circuit board with ideal electrical connection can be obtained.
【０００４】[0004]
【発明が解決しようとする課題】このようにして得られ
るプリント回路板は、電気的接続形成のために、スルー
ホールを開口する工程と開口させたスルーホールに導電
性材料を充填する工程を必要としている。このプリント
回路板は、複数個が積層されてＣＳＰが構成されること
があり、該ＣＳＰを構成するユニットプリント回路板の
製造に手間が掛かると全体のＣＳＰの製造の生産性が低
下し、ＣＳＰを構成するユニットプリント回路板の数が
大きくなるほどこの傾向が顕著になる。従って本発明
は、従来技術よりも高い生産性でＣＳＰを製造する方法
を提供することを目的とする。The printed circuit board obtained in this way requires a step of opening a through hole and a step of filling a conductive material into the opened through hole in order to form an electrical connection. And In some cases, a plurality of such printed circuit boards are stacked to form a CSP, and if it takes time to manufacture the unit printed circuit boards constituting the CSP, the productivity of the entire CSP is reduced, and the CSP is reduced. This tendency becomes more remarkable as the number of unit printed circuit boards constituting the above increases. Accordingly, an object of the present invention is to provide a method for manufacturing a CSP with higher productivity than the prior art.
【０００５】[0005]
【課題を解決するための手段】本発明に係る方法は、プ
リント回路板の基板に近接してバンプ形成用導電性材料
を位置させ、該導電性物質をパンチングして、該パンチ
ングと実質的に同時に前記基板にスルーホールを形成し
かつ該スルーホールへの前記バンプ形成用導電性材料の
充填を行って前記基板に所望数のバンプを形成してユニ
ットプリント回路板を作製し、複数の該ユニットプリン
ト回路板を接続部材を介して積層し、加熱下で圧着しチ
ップ・サイズ・パッケージを製造することを特徴とする
方法である。SUMMARY OF THE INVENTION A method according to the present invention comprises positioning a conductive material for forming bumps in close proximity to a substrate of a printed circuit board, punching the conductive material, and substantially removing the punching. At the same time, a through hole is formed in the substrate, and the bump forming conductive material is filled into the through hole to form a desired number of bumps on the substrate to produce a unit printed circuit board. This is a method characterized in that printed circuit boards are laminated via a connecting member, and pressure-bonded under heating to produce a chip size package.
【０００６】以下本発明を詳細に説明する。本発明は、
ＣＳＰを高い生産性で、換言するとより短時間で、ある
いはより簡便に製造するために方法に関する。ＣＳＰと
は、ユニットとなるプリント回路板を複数個積層して成
る半導体デバイスを意味する。本発明で使用するプリン
ト回路板は通常のプリント回路板で基板として使用され
る材質のものを制限無く使用でき、例えばポリイミド樹
脂の使用が望ましい。又配線パターンを形成する材質や
配線パターンの形成方法は特に制限されず、銅張り層を
製面し、フォトレジストの塗布によるマスキング、露
光、現像、及びエッチングによって所望の配線パターン
を作製すれば良い。必要に応じてプリント回路板の他面
にも同様にして配線パターンを形成して両面に配線パタ
ーンを有するプリント回路板とすることもできる。Hereinafter, the present invention will be described in detail. The present invention
The present invention relates to a method for producing a CSP with high productivity, in other words, in a shorter time or more easily. CSP means a semiconductor device formed by laminating a plurality of printed circuit boards as units. The printed circuit board used in the present invention can be made of any material used as a substrate in a normal printed circuit board without any limitation, and for example, it is desirable to use a polyimide resin. The material for forming the wiring pattern and the method of forming the wiring pattern are not particularly limited, and a copper-clad layer may be formed, and a desired wiring pattern may be formed by masking by applying a photoresist, exposing, developing, and etching. . If necessary, a wiring pattern may be formed on the other surface of the printed circuit board in the same manner to obtain a printed circuit board having a wiring pattern on both surfaces.
【０００７】本発明方法では、ユニットプリント回路板
へのスルーホール形成工程と、導電性材料（インプラン
ト材）による該スルーホール充填工程を実質的に同時に
行う。両工程を実質的に同時に行うには、スルーホール
を充填する導電性物質をスルーホール充填用の形状に成
形（あるいは抉り取る）し、この導電性物質と同じ形状
のスルーホールを基板を貫通して形成し、更に前記導電
性物質でスルーホールを充填するという３段階の操作が
必要になり、これは例えば形成すべきスルーホールと同
一形状のポンチを使用するパンチングにより行うことが
できる。例えば、基板の上方に板状に成型した導電性物
質を位置させ、スルーホールを形成すべき基板の対応個
所に位置する前記導電性物質にポンチを押し当てて該導
電性物質を抉り取り、更にポンチを押し下げると、ポン
チが基板に当たってスルーホールを穿設すると共にポン
チに同伴している抉り取られた導電性物質がスルーホー
ルを自動的に充填してバンプとする。なおバンプは配線
パターンを有しない側の表面から突出する形状とするこ
とが望ましく、突出長さは好ましくは10〜30μｍであ
る。In the method of the present invention, the step of forming a through hole in a unit printed circuit board and the step of filling the through hole with a conductive material (implant material) are performed substantially simultaneously. To perform both steps substantially simultaneously, a conductive material filling the through hole is formed (or cut out) into a shape for filling the through hole, and a through hole having the same shape as the conductive material is passed through the substrate. It is necessary to perform a three-stage operation of forming the through hole and filling the through hole with the conductive material. This operation can be performed by, for example, punching using a punch having the same shape as the through hole to be formed. For example, a conductive material molded into a plate shape is located above the substrate, and a punch is pressed against the conductive material located at a corresponding portion of the substrate where a through hole is to be formed, and the conductive material is gouged. When the punch is depressed, the punch hits the substrate to form a through hole, and the punched-out conductive material accompanying the punch automatically fills the through hole to form a bump. The bumps preferably have a shape protruding from the surface having no wiring pattern, and the protruding length is preferably 10 to 30 μm.
【０００８】これにより従来より簡便に導電性物質で充
填されたスルーホールを有するユニットプリント回路板
が得られる。このようにして得られたユニットプリント
回路板には集積回路を実装し、このユニットプリント回
路板を複数枚積層して得られるＣＳＰは、各ユニットプ
リント回路板作製時間の短縮分と枚数を掛け合わせた時
間分だけ効率的に製造できる。本発明方法において基板
に生成されるスルーホールの数は電気的接続を必要とす
る配線パターンの数や位置関係に依存し、その径は十分
な電気的接続が確保される範囲でなるべく小さくするこ
とが望ましい。As a result, a unit printed circuit board having through holes filled with a conductive substance can be obtained more easily than in the past. An integrated circuit is mounted on the unit printed circuit board thus obtained, and a CSP obtained by laminating a plurality of the unit printed circuit boards is obtained by multiplying the number of sheets by shortening the manufacturing time of each unit printed circuit board. It can be manufactured efficiently for the time required. In the method of the present invention, the number of through holes formed in the substrate depends on the number and positional relationship of the wiring patterns that require electrical connection, and the diameter thereof should be as small as possible within a range where sufficient electrical connection is ensured. Is desirable.
【０００９】前記スルーホールを充填する導電性物質と
しては、従来の金属銅等の他に、無酸素銅、リン脱酸銅
及びタフピッチ銅等が使用できる。ここで無酸素銅とは
水素脆化を防ぐために酸素の含有量を0.005％以下にし
たものを言う。無酸素銅は、ＯＦＨＣと称され、真空溶
解炉や還元雰囲気の誘導炉等で製造できる。リン脱酸銅
とは、酸素含有量が極端に低い銅で、酸素をP2O5などの
酸化物として脱酸し、僅かにリンが残った銅をいう。As the conductive material for filling the through holes, there can be used oxygen-free copper, phosphorous deoxidized copper, tough pitch copper, etc. in addition to conventional metallic copper. Here, oxygen-free copper refers to a material in which the oxygen content is 0.005% or less in order to prevent hydrogen embrittlement. Oxygen-free copper is called OFHC and can be manufactured in a vacuum melting furnace, an induction furnace in a reducing atmosphere, or the like. Phosphorus-deoxidized copper refers to copper having an extremely low oxygen content, which is obtained by deoxidizing oxygen as an oxide such as P 2 O 5 and leaving a small amount of phosphorus.
【００１０】更にタフピッチ銅とは、Cu2Oとして微量
（0.02〜0.05％）の酸素を含んだ銅で、電気銅を反射炉
で融解精製して酸素を0.02％程度残し、As、Sb及びＰな
どの不純物を酸化物として固溶体外に出した精製銅を言
う。これらの銅は通常０〜0.05％程度の酸素と他の若干
の不純物を含有し、従来スルーホールの充填に使用され
ていたスズ−銀合金材やスズ−銅合金材と比較して耐熱
性が高く、ハンダボール搭載時のリフロー温度である26
0℃におけるプリント回路板の耐熱性を向上させる。そ
して予め焼鈍しを行ったアニール無酸素銅、アニールリ
ン脱酸銅又はアニールタフピッチ銅を使用すると、更に
効果が増大する。Further, tough pitch copper is copper containing a small amount (0.02 to 0.05%) of oxygen as Cu 2 O. Electrolytic copper is melted and refined in a reverberatory furnace to leave about 0.02% of oxygen, and As, Sb and P It refers to purified copper in which impurities such as impurities are brought out of solid solution as oxides. These coppers usually contain about 0 to 0.05% of oxygen and some other impurities, and have a higher heat resistance than tin-silver alloy or tin-copper alloy materials conventionally used for filling through holes. High, which is the reflow temperature when solder balls are mounted 26
Improves the heat resistance of printed circuit boards at 0 ° C. Use of annealed oxygen-free copper, annealed phosphorus deoxidized copper or annealed tough pitch copper which has been annealed in advance further increases the effect.
【００１１】このように作製されたユニットプリント回
路板には接着剤層をラミネートしたり、銅、金、錫又は
これらの基合金のめっき層を形成しても良い。接着剤層
は後述するＣＳＰの製造時の各ユニットプリント回路板
と接続部材との接続に有効である。この接着剤は、完全
には硬化していない熱硬化性樹脂、いわゆるプリプレグ
であることが望ましく、この他にホットメルトタイプ即
ち熱可塑性樹脂も使用可能である。The unit printed circuit board thus manufactured may be laminated with an adhesive layer or formed with a plating layer of copper, gold, tin or a base alloy thereof. The adhesive layer is effective for connecting each unit printed circuit board and the connection member at the time of manufacturing a CSP described later. This adhesive is desirably a thermosetting resin that is not completely cured, that is, a so-called prepreg. In addition, a hot melt type, that is, a thermoplastic resin can also be used.
【００１２】次いで複数のユニットプリント回路板を接
続部材を介して積層してＣＳＰを製造する。この接続部
材はユニットプリント回路板に実装した集積回路間の絶
縁を行いながら各ユニットプリント回路板を電気的に接
続する機能を有し、集積回路の部分が開口する額縁状フ
レームや隣接するユニットプリント回路板のバンプ間を
接続するハンダボール等が使用できる。積層後に、加熱
下で圧着してＣＳＰとする。加熱条件はユニットプリン
ト回路板や接続部材に悪影響が及ばなければ特に限定さ
れず、通常は170〜180℃で行う。加熱により接着剤が溶
融して各ユニットプリント回路板及び接続部材を一体化
する。Next, a plurality of unit printed circuit boards are stacked via a connecting member to manufacture a CSP. This connection member has a function of electrically connecting each unit printed circuit board while performing insulation between the integrated circuits mounted on the unit printed circuit board. A solder ball or the like for connecting between bumps of a circuit board can be used. After lamination, it is press-bonded under heating to form a CSP. The heating condition is not particularly limited as long as it does not adversely affect the unit printed circuit board and the connecting members, and is usually at 170 to 180 ° C. The heating melts the adhesive to integrate the unit printed circuit boards and the connection members.
【００１３】[0013]
【発明の実施の形態】次に添付図面に基づいて本発明に
係るプリント回路板の製造の実施形態を説明するが、該
実施形態は本発明を限定するものではない。図１Ａ〜Ｅ
は本発明で使用できる配線基板の一連の製造工程の実施
態様を例示する縦断面図である。図１Ａに示すように、
片面に銅貼り層１が被覆されたポリイミドフィルム製基
板２の銅貼り層をパターニングして配線パターン３を形
成する（図１Ｂ）。その後、ポリイミドフィルム２の上
方に形成したスルーホールに充填するインプラント材と
同じ材質の板状の導電性物質４を位置させる。図１Ｃに
示すように、この板状物質の上方で前記スルーホールに
対応する個所に、スルーホールの断面形状と同じ断面形
状を有する複数のポンチ５を位置させ、図１Ｃに示すよ
うにこれらのポンチ５を下向きに移動させる。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a printed circuit board according to an embodiment of the present invention; 1A to 1E
1 is a longitudinal sectional view illustrating an embodiment of a series of manufacturing steps of a wiring board that can be used in the present invention. As shown in FIG. 1A,
The wiring layer 3 is formed by patterning the copper bonding layer of the polyimide film substrate 2 having one surface coated with the copper bonding layer 1 (FIG. 1B). Thereafter, a plate-shaped conductive material 4 of the same material as the implant material to be filled in the through hole formed above the polyimide film 2 is located. As shown in FIG. 1C, a plurality of punches 5 having the same cross-sectional shape as the cross-sectional shape of the through-hole are located at positions corresponding to the through-holes above the plate-like substance, and as shown in FIG. The punch 5 is moved downward.
【００１４】各ポンチ５は板状物質４を貫通して該板状
物質４をポンチの断面形状と同じ断面形状の柱状物質と
して抉り取り、この柱状物質は更にポンチ５により下方
に向けて移動する。この柱状物質と共に下方に移動する
ポンチ５は、配線パターン３及びポリイミドフィルム２
にスルーホール６及び７を穿設するとともに、これらの
スルーホール６及び７に前記柱状物質を充填し更にスル
ーホール６及び７の配線パターンを形成していない面の
下端部から突出させて導電性物質からなるバンプ８を構
成する（図１Ｄ）。この基板２の表裏面には銅めっき層
（図示略）を形成しても良く、更に該基板２の裏面側
(配線パターンを形成していない面)には、突出するバン
プ８も含めて接着剤層９をラミネートする。更にこの基
板２の配線パターン３上には多数の小ハンダ球10を介し
て集積回路11を配置してユニットプリント回路板12を構
成する。Each punch 5 penetrates the plate-shaped material 4 and cuts the plate-shaped material 4 as a columnar material having the same cross-sectional shape as that of the punch, and the columnar material is further moved downward by the punch 5. . The punch 5 that moves downward together with the columnar material includes the wiring pattern 3 and the polyimide film 2.
Through holes 6 and 7 are formed, and the through holes 6 and 7 are filled with the columnar material. The through holes 6 and 7 are projected from the lower ends of the surfaces of the through holes 6 and 7 where the wiring pattern is not formed. A bump 8 made of a material is formed (FIG. 1D). A copper plating layer (not shown) may be formed on the front and back surfaces of the substrate 2.
The adhesive layer 9 including the protruding bumps 8 is laminated on the (surface on which the wiring pattern is not formed). Further, an integrated circuit 11 is arranged on the wiring pattern 3 of the substrate 2 via a number of small solder balls 10 to form a unit printed circuit board 12.
【００１５】次にこのユニットプリント回路板を複数個
使用して成る積層ＣＳＰ（ＣＳＰ）の製法を図２及び図
３を参照して説明する。図２は図1のユニットプリント
回路板と、該ユニットプリント回路板の積層用フレーム
の相互の位置関係を示す縦断正面図、図３は４個のユニ
ットプリント回路板を３個の積層用フレームを使用して
積層したＣＳＰを示す縦断正面図である。なお図２及び
図３では、図面の簡略化のため、図１の接着剤層９を省
略している。図２の上方のユニットプリント回路板12Ａ
は集積回路を有さないこと以外は図１のユニットプリン
ト回路板12と同じ構成を有し、下方のユニットプリント
回路板12は図１と同じユニットプリント回路板である。Next, a method of manufacturing a laminated CSP (CSP) using a plurality of unit printed circuit boards will be described with reference to FIGS. FIG. 2 is a longitudinal sectional front view showing the mutual positional relationship between the unit printed circuit board of FIG. 1 and the frame for lamination of the unit printed circuit board. FIG. 3 shows four unit printed circuit boards and three laminated frames. It is a vertical front view which shows CSP laminated | stacked using. 2 and 3, the adhesive layer 9 in FIG. 1 is omitted for simplification of the drawings. Unit printed circuit board 12A in the upper part of FIG.
Has the same configuration as the unit printed circuit board 12 of FIG. 1 except that it has no integrated circuit, and the lower unit printed circuit board 12 is the same unit printed circuit board as that of FIG.
【００１６】両ユニットプリント回路板12及び12Ａ間に
は積層用フレーム13が配置されている。この積層用フレ
ーム13は全体的な輪郭は前記両ユニットプリント回路板
12及び12Ａとほぼ同一形状を有し、内方に前記集積回路
11より大きい開口14を有している。この積層用フレーム
13の前記ユニットプリント回路板12のバンプ８に対応す
る個所には該バンプ８とほぼ同一形状の導電性材料15が
充填されたスルーホール16が形成され、該導電性材料15
は前記バンプと同様に下方に向けて突出すると共に、上
面の接着剤層17を貫通している。この積層用フレームの
導電性材料15が充填されたスルーホール16の形成は図１
におけるバンプ形成と同様にしてポンチを使用して孔形
成及び材料充填を単一操作で行うことが望ましい。A laminating frame 13 is disposed between the unit printed circuit boards 12 and 12A. The overall outline of the frame 13 is the same as that of the unit printed circuit board.
It has almost the same shape as 12 and 12A, and has the integrated circuit inside
It has an opening 14 larger than 11. This frame for lamination
13 is formed at a position corresponding to the bump 8 of the unit printed circuit board 12 with a through hole 16 filled with a conductive material 15 having substantially the same shape as the bump 8.
Protrudes downward similarly to the bump, and penetrates the adhesive layer 17 on the upper surface. The formation of the through hole 16 filled with the conductive material 15 of the stacking frame is shown in FIG.
It is desirable to perform hole formation and material filling in a single operation using a punch in the same manner as in the bump formation in the above.
【００１７】最上位のユニットプリント回路板12Ａの下
に、３個の積層用フレーム13とユニットプリント回路板
12を交互に位置させ、加熱しながら上下方向から圧力を
加えると、ユニットプリント回路板12のバンプ８と積層
用フレーム13の導電性材料15が溶融一体化して縦方向に
延びる接続材料18となって各ユニットプリント回路板12
を電気的に接続し、これによりＣＳＰが完成する。本実
施態様では、一旦スルーホールを形成し次いで該スルー
ホールをめっき等で充填する従来法と異なり、ユニット
プリント回路板12のスルーホール６及び７へのバンプ充
填をポンチを使用する単一操作で行っているため、ユニ
ットプリント回路板の生産性が向上し、従ってＣＳＰの
生産性も向上する。Under the uppermost unit printed circuit board 12A, three laminated frames 13 and a unit printed circuit board
When pressure is applied from above and below while alternately arranging 12 and heating, the bumps 8 of the unit printed circuit board 12 and the conductive material 15 of the laminating frame 13 are melted and integrated to form a connecting material 18 extending in the vertical direction. Each unit printed circuit board 12
Are electrically connected, thereby completing the CSP. In this embodiment, unlike the conventional method of forming a through hole once and then filling the through hole with plating or the like, the bumps are filled into the through holes 6 and 7 of the unit printed circuit board 12 by a single operation using a punch. As a result, the productivity of the unit printed circuit board is improved, and the productivity of the CSP is also improved.
【００１８】本発明では積層用フレームの使用は必須で
はなく、例えば図4に示す通り、図２における積層用フ
レームの導電性材料15の位置に対応する数のハンダボー
ル19を設置することによりほぼ同等の効果が得られ、こ
の場合にもユニットプリント回路板12のスルーホール６
及び７へのバンプ充填をポンチを使用する単一操作で行
っているため、ユニットプリント回路板の生産性が向上
し、従ってＣＳＰの生産性も向上する。In the present invention, the use of the laminating frame is not essential. For example, as shown in FIG. 4, the number of solder balls 19 corresponding to the position of the conductive material 15 of the laminating frame in FIG. The same effect is obtained, and in this case, the through holes 6 of the unit printed circuit board 12 are also provided.
And 7 are performed in a single operation using a punch, so that the productivity of the unit printed circuit board is improved, and thus the productivity of the CSP is also improved.
【００１９】[0019]
【実施例】図１〜３に示す要領でＣＳＰを製造する実施
例及び比較例を記載するが、これら本発明を限定するも
のではない。EXAMPLES Examples and comparative examples for manufacturing a CSP in the manner shown in FIGS. 1 to 3 will be described, but these examples do not limit the present invention.
【００２０】実施例１ 片面に厚さ18μｍの銅箔を被覆した幅35mmで厚さ50μｍ
のポリイミドフィルム（新日鉄化学株式会社製の商品名
エスパネックス）基板の表面に所定の配線パターンを形
成した後、該基板の上方に板状に成形したアニール無酸
素銅を位置させた。該アニール無酸素銅の、基板へのバ
ンプ形成に対応する個所にバンプの予定直径と同じ80μ
ｍ径のポンチを位置させかつ下方に強く押圧して、板状
のアニール無酸素銅を円柱状に抉り取り、更に基板も同
様にして抉り取ってスルーホールを形成し、このスルー
ホールを直ちに抉り取ったアニール無酸素銅で充填し、
かつ充填したアニール無酸素銅の下端が配線パターンを
形成していない面から20μm突出するバンプを形成し
た。 EXAMPLE 1 A copper foil having a thickness of 18 μm was coated on one side to a width of 35 mm and a thickness of 50 μm.
After a predetermined wiring pattern was formed on the surface of a polyimide film (trade name: ESPANEX manufactured by Nippon Steel Chemical Co., Ltd.), annealed oxygen-free copper formed in a plate shape was positioned above the substrate. At the place corresponding to the bump formation on the substrate of the annealed oxygen-free copper, the same diameter as the expected diameter of the bump is 80 μm.
Position the m-diameter punch and press strongly down to cut out the plate-shaped annealed oxygen-free copper in a columnar shape, and then cut out the substrate in the same way to form a through hole, and immediately go through this through hole. Filled with annealed oxygen-free copper,
In addition, a bump was formed in which the lower end of the filled annealed oxygen-free copper protruded 20 μm from the surface on which the wiring pattern was not formed.
【００２１】次いで突出バンプを含めて配線パターンを
形成していない面に３μmの銅めっきを施し、更にニッ
ケル（1.5μｍ）−金（0.15μｍ）のめっきを行った
後、集積回路をフリップ−フラップ実装した。更にこの
面の全面に厚さ50μｍの接着剤（東レ・ダウコーニング
株式会社製）をラミネートしてユニットプリント回路板
とした。積層用フレームは次のようにして作製した。前
記基板と同じ幅35mmのエスパネックスを使用し、その中
心に前記集積回路の外径より大きい開口を形成した。前
記バンプに対応する積層用フレームの個所に接着剤を塗
布し、基板の場合と同様にして直径80μｍのスルーホー
ルを形成し直ちに該スルーホールにアニール無酸素銅を
充填しかつ下面から20μm突出させて積層用フレームと
した。次いで突出面に３μmの銅めっきを施し、更に0.5
μｍの錫めっきを行った後、突出面の全面に厚さ50μｍ
の接着剤をラミネートした。Next, the surface on which the wiring pattern is not formed including the protruding bumps is plated with 3 μm copper, and further plated with nickel (1.5 μm) -gold (0.15 μm). Implemented. Further, an adhesive (manufactured by Dow Corning Toray Co., Ltd.) having a thickness of 50 μm was laminated on the entire surface of the surface to obtain a unit printed circuit board. The laminating frame was produced as follows. An ESPANEX having the same width as that of the substrate and having a width of 35 mm was used, and an opening larger than the outer diameter of the integrated circuit was formed at the center thereof. An adhesive is applied to the portion of the laminating frame corresponding to the bump, a through hole having a diameter of 80 μm is formed in the same manner as in the case of the substrate, and the through hole is immediately filled with annealed oxygen-free copper and projected from the lower surface by 20 μm. To form a frame for lamination. Next, apply 3μm copper plating to the protruding surface,
μm tin plating, then 50μm thick
Was laminated.
【００２２】このようにして得られた４枚のユニットプ
リント回路板（及び集積回路のない１枚のユニットプリ
ント回路板）と４枚の積層用フレームを交互に積層し、
400℃の加熱下で圧着して、錫と金のよる合金形成及び
バンプ側の接着剤によりユニットプリント回路板及び積
層用フレームを接着してＣＳＰを作製した。このＣＳＰ
の作製では、レーザー加工によるスルーホール加工及び
電解銅めっきバンプ形成工程が不必要で、単独のパンチ
ングでバンプ形成ができるため、作製時間が大幅に短縮
された。The thus obtained four unit printed circuit boards (and one unit printed circuit board without integrated circuit) and four laminating frames are alternately laminated,
The CSP was produced by pressing under heating at 400 ° C., forming an alloy of tin and gold, and bonding the unit printed circuit board and the laminating frame with an adhesive on the bump side. This CSP
In the fabrication of No. 1, the through-hole processing by laser processing and the step of forming an electrolytic copper plating bump are unnecessary, and the bump can be formed by single punching, so that the manufacturing time is greatly reduced.
【００２３】比較例１ 各ユニットプリント回路板及び積層用フレームへのアニ
ール無酸素銅の充填を、ポンチを使用して、一旦基板に
スルーホールを形成した後に、該スルーホールの上方に
板状のアニール無酸素銅を位置させ、同じポンチを使用
して該アニール無酸素銅を抉り取り前記スルーホールを
充填したこと以外は実施例１と同じ操作でＣＳＰを作製
した。本比較例では、レーザー加工によるスルーホール
加工及び電解銅めっきバンプ形成工程は不必要であっ
た。実施例１と比較例１で作製したＣＳＰの機械的強度
を測定したところ両者には差異がなく、実施例１のよう
に単独のパンチングでバンプ形成を行って作製時間を大
幅に短縮しても不都合が生じないことが分かった。COMPARATIVE EXAMPLE 1 Each unit printed circuit board and the frame for lamination were filled with annealed oxygen-free copper by using a punch to form a through-hole in the substrate, and then forming a plate-like plate above the through-hole. A CSP was produced in the same manner as in Example 1 except that the annealed oxygen-free copper was positioned, the annealed oxygen-free copper was cut out using the same punch, and the through holes were filled. In this comparative example, through-hole processing by laser processing and an electrolytic copper plating bump forming step were unnecessary. When the mechanical strengths of the CSPs manufactured in Example 1 and Comparative Example 1 were measured, there was no difference between the two. Even when the bumps were formed by single punching as in Example 1, the manufacturing time was greatly reduced. It turned out that no inconvenience occurred.
【００２４】[0024]
【発明の効果】本発明は、プリント回路板の基板に近接
してバンプ形成用導電性材料を位置させ、該導電性物質
をパンチングして、該パンチングと実質的に同時に前記
基板にスルーホールを形成しかつ該スルーホールへの前
記バンプ形成用導電性材料の充填を行って前記基板に所
望数のバンプを形成してユニットプリント回路板を作製
し、複数の該ユニットプリント回路板を接続部材を介し
て積層し、加熱下で圧着しＣＳＰを製造することを特徴
とする方法（請求項１）である。この方法では、各ユニ
ットプリント回路板作製時に、従来は別個に行っていた
スルーホール形成とスルーホールへの導電性材料充填を
単一操作で行うことができる。従って各ユニットプリン
ト回路板が簡便に即ち短時間で作製できて、各ユニット
プリント回路板作製時間の短縮分と枚数を掛け合わせた
時間分だけ効率的に製造できる。According to the present invention, a conductive material for forming a bump is located in close proximity to a substrate of a printed circuit board, the conductive material is punched, and a through hole is formed in the substrate substantially simultaneously with the punching. A unit printed circuit board is formed by forming and filling the through hole with the bump forming conductive material to form a desired number of bumps on the substrate, and a plurality of the unit printed circuit boards are connected to each other by connecting members. (Claim 1). According to this method, the formation of the through-hole and the filling of the conductive material into the through-hole can be performed by a single operation, which has conventionally been performed separately at the time of manufacturing each unit printed circuit board. Therefore, each unit printed circuit board can be manufactured simply, that is, in a short time, and the unit printed circuit board can be manufactured efficiently by the time obtained by multiplying the reduced number of unit printed circuit board times by the number of sheets.
【００２５】スルーホール形成と該スルーホールへの導
電性材料の充填を実質的に同時に行うには、ポンチを使
用するパンチングを採用することにより好ましく実施で
きる（請求項２）。各ユニットプリント回路板のバンプ
を一方面に向けて突出させておくと（請求項３）、各バ
ンプと隣接する接続部材との接続が容易になる。バンプ
形成用導電性材料は、無酸素銅、リン脱酸銅及びタフピ
ッチ銅等が好ましく使用でき（請求項４）、これらの物
質を使用すると、プリント回路板の耐熱性が向上する。The formation of the through-hole and the filling of the conductive material into the through-hole substantially simultaneously can be preferably carried out by employing punching using a punch (claim 2). When the bumps of each unit printed circuit board are projected toward one surface (claim 3), connection between each bump and an adjacent connection member is facilitated. As the conductive material for forming the bumps, oxygen-free copper, phosphorus deoxidized copper, tough pitch copper, and the like can be preferably used (claim 4). When these substances are used, the heat resistance of the printed circuit board is improved.
【図１】図１Ａ〜Ｅは本発明で使用できる配線基板の一
連の製造工程の実施態様を例示する縦断面図。1A to 1E are longitudinal sectional views illustrating an embodiment of a series of manufacturing steps of a wiring board that can be used in the present invention.
【図２】図1のユニットプリント回路板と、該ユニット
プリント回路板の積層用フレームの相互の位置関係を示
す縦断正面図。FIG. 2 is a longitudinal sectional front view showing a mutual positional relationship between the unit printed circuit board of FIG. 1 and a frame for laminating the unit printed circuit board.
【図３】本発明方法に係るＣＳＰの一実施態様を示す縦
断正面図。FIG. 3 is a longitudinal sectional front view showing one embodiment of a CSP according to the method of the present invention.
【図４】本発明方法に係るＣＳＰの他の実施態様を示す
縦断正面図。FIG. 4 is a longitudinal sectional front view showing another embodiment of the CSP according to the method of the present invention.
１ 銅貼り層 ２ ポリイミドフィルム製基板 ３ 配線パターン ４ 導電性物質 ５ ポンチ ６、７ スルーホール ８ バンプ ９ 接着剤層 10 小ハンダ球 11 集積回路 12、12Ａ ユニットプリント回路板 13 積層用フレーム 14 開口 15 導電性物質 16 スルーホール 17 接着剤層 18 接続材料 19 ハンダボール DESCRIPTION OF SYMBOLS 1 Copper bonding layer 2 Polyimide film board 3 Wiring pattern 4 Conductive substance 5 Punch 6, 7 Through hole 8 Bump 9 Adhesive layer 10 Small solder ball 11 Integrated circuit 12, 12A Unit printed circuit board 13 Lamination frame 14 Opening 15 Conductive substance 16 Through hole 17 Adhesive layer 18 Connection material 19 Solder ball
Claims (4)
形成用導電性材料を位置させ、該導電性物質をパンチン
グして、該パンチングと実質的に同時に前記基板にスル
ーホールを形成しかつ該スルーホールへの前記バンプ形
成用導電性材料の充填を行って前記基板に所望数のバン
プを形成してユニットプリント回路板を作製し、複数の
該ユニットプリント回路板を接続部材を介して積層し、
加熱下で圧着しＣＳＰを製造することを特徴とする方
法。1. A conductive material for forming a bump is located in proximity to a substrate of a printed circuit board, and the conductive material is punched to form a through hole in the substrate substantially simultaneously with the punching. A desired number of bumps are formed on the substrate by filling the through hole with the bump forming conductive material to produce a unit printed circuit board, and a plurality of the unit printed circuit boards are laminated via a connecting member. ,
A method comprising producing a CSP by pressing under heating.
ルーホール形成と該スルーホールへの導電性材料の充填
を実質的に同時に行うようにした請求項１に記載の方
法。2. The method according to claim 1, wherein the forming of the through hole and the filling of the conductive material into the through hole are performed substantially simultaneously by punching using a punch.
面に向けて突出している請求項１又は２に記載の方法。3. The method according to claim 1, wherein the bumps of the unit printed circuit board project toward one side.
リン脱酸銅及びタフピッチ銅から成る群から選択される
請求項１から４までのいずれかに記載の方法。4. The method according to claim 1, wherein the conductive material for forming a bump is oxygen-free copper.
The method according to any of the preceding claims, wherein the method is selected from the group consisting of phosphorus deoxidized copper and tough pitch copper.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001147781A JP2002343901A (en) | 2001-05-17 | 2001-05-17 | CSP manufacturing method |
| EP02718637A EP1389897A1 (en) | 2001-04-24 | 2002-04-23 | Printed circuit board, its manufacturing method, and csp manufacturing methdo |
| PCT/JP2002/004016 WO2002089540A1 (en) | 2001-04-24 | 2002-04-23 | Printed circuit board, its manufacturing method, and csp manufacturing methdo |
| US10/475,707 US20040099441A1 (en) | 2001-04-24 | 2002-04-23 | Printed circuit board,its manufacturing method and csp manufacturing method |
| TW91108463A TW573452B (en) | 2001-04-24 | 2002-04-24 | Printed circuit board, its manufacturing method and the manufacturing method of CSP (chip size package) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001147781A JP2002343901A (en) | 2001-05-17 | 2001-05-17 | CSP manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002343901A true JP2002343901A (en) | 2002-11-29 |
Family
ID=18993206
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001147781A Pending JP2002343901A (en) | 2001-04-24 | 2001-05-17 | CSP manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002343901A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009031251A1 (en) * | 2007-09-05 | 2009-03-12 | Ibiden Co., Ltd. | Wiring substrate and method for manufacturing the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000196235A (en) * | 1998-10-23 | 2000-07-14 | Suzuki Co Ltd | Manufacture of resin sheet having filled via |
| JP2000332369A (en) * | 1999-05-25 | 2000-11-30 | Mitsui Mining & Smelting Co Ltd | Printed circuit board and manufacturing method thereof |
| JP2001068808A (en) * | 1999-08-24 | 2001-03-16 | Kyocera Corp | Ceramic circuit board |
-
2001
- 2001-05-17 JP JP2001147781A patent/JP2002343901A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000196235A (en) * | 1998-10-23 | 2000-07-14 | Suzuki Co Ltd | Manufacture of resin sheet having filled via |
| JP2000332369A (en) * | 1999-05-25 | 2000-11-30 | Mitsui Mining & Smelting Co Ltd | Printed circuit board and manufacturing method thereof |
| JP2001068808A (en) * | 1999-08-24 | 2001-03-16 | Kyocera Corp | Ceramic circuit board |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009031251A1 (en) * | 2007-09-05 | 2009-03-12 | Ibiden Co., Ltd. | Wiring substrate and method for manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8400776B2 (en) | Multilayered printed wiring board | |
| US5976912A (en) | Fabrication process of semiconductor package and semiconductor package | |
| US20040195002A1 (en) | Multilayer wiring board assembly, multilayer wiring board assembly component and method of manufacture thereof | |
| JP2006310541A (en) | Multilayer wiring board and its production process, multilayer wiring board structure and its production process | |
| US20090288293A1 (en) | Metal core package substrate and method for manufacturing the same | |
| US20040099441A1 (en) | Printed circuit board,its manufacturing method and csp manufacturing method | |
| WO2004017689A1 (en) | Multilayer printed wiring board and production method therefor | |
| JP2833642B2 (en) | Multilayer wiring board and method of manufacturing the same | |
| JP2002151853A (en) | Multilayer wiring board and manufacturing method thereof | |
| JP2008182039A (en) | Multilayer wiring board and manufacturing method thereof | |
| JP2002083926A (en) | Circuit board for mounting semiconductor chip, method of manufacturing the same, and multilayer circuit board | |
| JP2008124247A (en) | Component built-in substrate and manufacturing method thereof | |
| TW202112197A (en) | Circuit board, circuit board manufacturing method, and electronic equipment | |
| JP2002343901A (en) | CSP manufacturing method | |
| KR100619512B1 (en) | Substrate having a wiring layer and method of manufacturing the same | |
| JP4718890B2 (en) | MULTILAYER WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME, MULTILAYER WIRING BOARD STRUCTURE | |
| KR20100021810A (en) | Printed circuit board with electronic components embedded therein and method for fabricating the same | |
| JP3948317B2 (en) | Method for manufacturing thermally conductive substrate | |
| JP2006310543A (en) | Wiring board and its production process, wiring board with semiconductor circuit element | |
| JP2005109188A (en) | Circuit board and multilayer board, and method for manufacturing circuit board and multilayer board | |
| JP5098313B2 (en) | Wiring board | |
| JP2006049457A (en) | Wiring board with built-in parts and manufacturing method thereof | |
| JP2007027255A (en) | Semiconductor mounting substrate and manufacturing method thereof | |
| JP2002246510A (en) | Wiring board, tape carrier, and semiconductor device using the same | |
| JP2002324957A (en) | Printed circuit board and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060727 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20061116 |