JP2002231599A - Mask master, mask, method of manufacturing mask, and method of manufacturing semiconductor device - Google Patents

Abstract

[PROBLEMS] To provide a mask master, a mask, a method of manufacturing a mask, and a method of manufacturing a semiconductor device, which are capable of improving mask manufacturing efficiency and improving pattern processing accuracy. A step of forming a thin film on one surface of a substrate, a step of forming a protective layer on the thin film,
A part of the substrate is removed from the other side of the substrate, and the thin film 114 is removed.
Is locally exposed, a step of providing, on an exposed portion of the thin film 114, a transmitting portion 107 through which an electromagnetic wave of a predetermined wavelength is transmitted, and a blocking portion 103 through which the electromagnetic wave is blocked, and a step of removing the protective layer 112 A method for manufacturing a mask having
A mask master and a mask formed in the process, and a method of manufacturing a semiconductor device using the same.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a mask master for lithography, a mask, a method for manufacturing a mask, and a method for manufacturing a semiconductor device, and more particularly to a mask master, mask, and a method for manufacturing a mask for electron beam transfer lithography. And a method of manufacturing a semiconductor device including an electron beam transfer type lithography step.

[0002]

2. Description of the Related Art With the miniaturization and high integration of LSI,
Electron beam lithography (EPL)
ojection Lithography) is expected to be put to practical use. EPLs that are being put into practical use include PREVAIL (projection expos), which is jointly developed by IBM and Nikon.
ure with variable axis immersion lenses) (HC Pf
eiffer et al Journal of Vacuum Science and Technology
B17 p.2840 (1999)).

Further, SCALPEL (scattering with angular li) developed by Lucent Technology, etc.
mitation in projection electron-beam lithography)
(ST Stanton et al. Proceedings of SPIE 3676 p.194
(1999)). Furthermore, LEEPL (low ener) jointly developed by Ripple, Tokyo Seimitsu and Sony
(gy electron-beam proximity projection lithography)
(T. Utsumi, Journal of Vacuum Science and Technol
ogy B17 p.2897 (1999)).

[0004] PREVAIL and SCALPEL are:
The mask pattern is transferred onto the wafer by irradiating an electron beam of about 100 keV, while LEEPL is 2 ke
The mask pattern is transferred onto the wafer by irradiating an electron beam of about V. PREVAIL and SCALPEL are usually 4 × reduction projection systems, whereas LEEPL is a 1 × projection system.

A stencil mask and a membrane mask have been proposed as masks used for EPL. The stencil mask is a mask formed by forming holes (apertures) in a silicon thin film having a thickness of about 2 μm. On the other hand, the membrane mask is a mask in which a heavy metal such as chromium (Cr) or tungsten (W) is deposited on a silicon nitride film having a thickness of about 150 nm to form a pattern.

When electron beam lithography is performed using a stencil mask, the electron beam passes through only the aperture portion without scattering and forms an image on the resist. On the other hand, when electron beam lithography is performed using a membrane mask, an electron beam is scattered at a heavy metal portion and transmits only a portion other than the heavy metal. The resist is exposed by an electron beam transmitted through portions other than the heavy metal.

For PREVAIL and SCALPEL, both a stencil mask and a membrane mask can be used. In the case of LEEPL, on the other hand, a stencil mask is used because the energy of the electron beam is low and the electron beam does not pass through the membrane mask.

The stencil mask and the membrane mask can be formed using materials other than those described above.
For example, both a thin film portion in which a silicon nitride film is conventionally used and a scatterer in which a heavy metal is used are provided with a DL.
A membrane mask using C (Diamond Like Carbon) has been proposed (Preprint of the 61st Annual Meeting of the Japan Society of Applied Physics (2000) No.2 p.619 7a-X-5, H. Yamashita and others)
Journal of VacuumScience and Technology B18 (6) p.3
237 (2000)). A stencil mask made of diamond has also been proposed for X-ray lithography (H. Noguc).
hi et al Journal of Vacuum Science and Technology B16
p.2772 (1998)). Application of such a diamond mask to EPL is also expected.

The structure and manufacturing method of a conventional EPL mask will be described below with reference to the drawings. FIG.
10A is a schematic view of a stencil mask used for PREVAIL, and FIG. 10B is a cross-sectional view of a part (XX ′) of FIG. 10A. As shown in FIG. 10A, a stencil mask 201 is formed on an 8-inch silicon wafer 202 by, for example, 1.13 mm × 1.13 mm.
Of a plurality of thin film portions (membrane) 203 having a size of The membranes 203 are separated from each other by beams called struts 204. The width of the strut 204 is, for example, 170 μm. The strut 204 functions as a support for maintaining the mechanical strength of the stencil mask 201.

[0010] As shown in FIG.
03 is, for example, 2 μm, and the membrane 203 has an aperture 20 corresponding to an LSI mask pattern.
5 are formed. When the stencil mask 201 is formed using an 8-inch wafer, the height of the strut 204 is, for example, 725 μm. A silicon oxide film 207 is formed between the silicon layer 206 including the membrane 203 and the strut 204. Silicon oxide film 2
Reference numeral 07 is used as an etching stopper layer in the step of forming a strut 204 by etching the back surface of the silicon wafer 202.

In order to manufacture the stencil mask 201 as described above, first, as shown in FIG.
A wafer 211 is manufactured. The SOI wafer 211 has a silicon layer 206 on one surface of a silicon wafer 202 via a silicon oxide film 207 and a silicon oxide film 212 on the other side of the silicon wafer 202. SO
The I wafer 211 is, for example, SIMOX (separation by im
It can be formed by a planted oxygen) method or a bonding method.

Next, as shown in FIG.
A resist 213 is formed on the back surface of the wafer 211 in a pattern of the strut 204 (see FIG. 10). The resist 213 is formed by, for example, applying the whole surface by spin coating, and then performing exposure and development. Furthermore, SOI
From the back side of the wafer 211, dry etching is performed on the back side silicon oxide film 212 and the silicon wafer 202 using the resist 213 as a mask. Thus, a strut 204 made of silicon is formed.

Next, as shown in FIG. 11C, using the strut 204 as a mask, the silicon oxide film 20 on the front side is formed.
7 is etched. After that, the resist 213 is removed. Next, as shown in FIG.
A resist 214 having a predetermined pattern is formed on the substrate 06.
The resist 214 is formed by, for example, applying the whole surface by spin coating, and then performing exposure and development.

Next, dry etching is performed on the silicon layer 206 using the resist 214 as a mask. This allows
As shown in FIG. 10B, a membrane 203 having an aperture 205 having a predetermined pattern is formed. Then, the back-side silicon oxide film 212 and the resist 21
4 is removed. Through the above steps, the stencil mask 2
01 is formed.

FIG. 12A is a schematic view of a membrane mask used for SCALPEL, and FIG. 12B is a cross-sectional view of a part (XX ′) of FIG. 12A. Figure 1
As shown in FIG. 2A, a membrane mask 221 is formed on an 8-inch silicon wafer 202 by, for example, 1 mm ×
Multiple thin film portions (membrane) 22 having a size of 12 mm
2 The membranes 222 are separated from each other by beams called struts 204. Strut 2
The width of 04 is, for example, 300 μm. Strut 204
Functions as a support for maintaining the mechanical strength of the membrane mask 221.

As shown in FIG. 12B, the membrane 2
Reference numeral 22 denotes a part of the support layer made of, for example, the silicon nitride film 223, and the thickness of the silicon nitride film 223 is, for example, 150
nm. On the silicon nitride film 223, a scatterer 224 corresponding to an LSI mask pattern is formed.
As the scatterer 224, a heavy metal such as chromium and tungsten is used.
It is about 0 to 50 nm. When the membrane mask 221 is formed using an 8-inch wafer, the strut 204
Is 725 μm, for example.

In order to manufacture the above-described membrane mask 221, first, a silicon nitride film 223 is formed on a silicon wafer 202 as shown in FIG.
Further, a chromium layer and a tungsten layer are sequentially formed thereon, and a laminated film 225 is formed. The thickness of the chromium layer is, for example, 5 nm, and the thickness of the tungsten layer thereover is, for example, 25 nm. Although not shown, a silicon oxide film on the back side may be provided on the silicon wafer 202 as in FIG.

Next, as shown in FIG. 13B, a resist 226 is formed on the back surface of the silicon wafer 202 in a pattern of struts 204 (see FIG. 12). The resist 226 is formed by, for example, spin-coating the entire surface and then performing exposure and development. Further, dry etching is performed from the back surface side of the silicon wafer 202 using the resist 226 as a mask. Thus, a strut 204 made of silicon is formed. After that, the resist 226 is removed.

Next, as shown in FIG. 13C, a resist 2 is formed on the entire surface of the laminated film 225 by, for example, spin coating.
27 is applied. Next, as shown in FIG. 13D, the resist 227 is exposed and developed to form a resist 228 corresponding to the LSI mask pattern. next,
Dry etching is performed on the stacked film 225 using the resist 228 as a mask. Thereby, as shown in FIG. 12B, a scatterer 224 having a predetermined pattern is formed. After that, the resist 228 is removed. Through the above steps, the membrane mask 221 is formed.

FIG. 14A is a schematic view of a stencil mask used for LEEPL, and FIG.
FIG. 4A is a partial cross-sectional view of FIG. As shown in FIG. 14A, the stencil mask 231 has a thin film portion (membrane) 203 having a size of 20 mm × 20 mm on, for example, an 8-inch silicon wafer 202. The silicon wafer 202 around the membrane 203 is a strut 2
04, which functions as a support for maintaining the mechanical strength of the stencil mask 231.

As shown in FIG. 14B, the membrane 2
03 has a thickness of, for example, 500 nm,
An aperture 205 corresponding to the mask pattern of the LSI is formed in 3. When forming the stencil mask 231 using an 8-inch wafer, the strut 204
Is 725 μm, for example. A silicon oxide film 207 is formed between the silicon layer 206 including the membrane 203 and the strut 204. The silicon oxide film 207 is used as an etching stopper layer in the step of forming the struts 204 by etching the back surface of the silicon wafer 202.

To manufacture the stencil mask 231 as described above, first, as shown in FIG. 15A, an SOI wafer having a silicon layer 206 on one side of a silicon wafer 202 with a silicon oxide film 207 interposed therebetween. 211 is manufactured. Next, as shown in FIG. 15B, a pattern of the strut 204 is formed on the back side of the SOI wafer 211 (FIG. 1).
4), a resist 232 is formed. Resist 232
Is formed by, for example, applying the whole surface by spin coating, and then performing exposure and development. Furthermore, SOI wafer 2
The silicon wafer 202 is etched from the back side of the silicon wafer 202 using the resist 232 as a mask. After that, the resist 232 is removed.

The stencil mask 231 for LEEPL is an equal-size mask, and the area of the membrane 203 is large.
The struts 204 are not formed at a high density unlike the stencil mask 201 for PREVAIL shown in FIG. Therefore, the cross section of the strut 204 may be tapered, and the strut 204 can be formed by wet etching.

Next, as shown in FIG. 15C, a resist 233 is applied to the entire surface of the silicon layer 206 by, for example, spin coating. Subsequently, as shown in FIG. 15D, exposure and development are performed on the resist 233 to form a resist 234 corresponding to the mask pattern of the LSI.
Further, using the resist 234 as a mask, the silicon layer 20 is used.
6 is dry-etched. Thus, an aperture 205 having a predetermined pattern is formed. Then, FIG.
As shown in FIG. 4B, the resist 234 is removed. Through the above steps, a stencil mask 231 is formed.

[0025]

However, according to the above-described conventional method for manufacturing a mask or a method for manufacturing a semiconductor device including a mask manufacturing process in accordance therewith, the etching for forming the struts 204 on the back surface side of the wafer is performed. Takes a long time. In particular, since it takes several hours to perform etching for the thickness of the silicon wafer 202 by dry etching, the turnaround time (TAT) from the end of pattern design to the completion of the mask becomes long.

If the struts are formed by etching the back surface of the wafer before the pattern design is completed, FIG.
(C) As shown in FIG. 13 (b) or FIG. 15 (b), the mask master must be stored or transported with the thin film portions 203 and 222 between the struts 204. In the state where the thin film portions 203 and 222 are thus formed, the mechanical strength of the mask master is significantly reduced, so that the mask master is easily damaged during storage or transportation, which causes a reduction in mask yield. . In order to avoid this, the formation of the struts 204 is often started after the completion of the pattern design, which makes it difficult to shorten the TAT.

Further, according to the above-described conventional mask manufacturing method, the strut 20
4 is formed, LS is formed on the front side of the silicon wafer 202.
A resist having a mask pattern of I is formed (FIG. 11)
(D), FIG. 13 (d) or FIG. 15 (d)). Therefore, when forming a resist on the front side of the silicon wafer 202, it is necessary to perform alignment from both sides of the silicon wafer 202. It is difficult to perform such alignment from both sides with high accuracy, and the yield of the mask is likely to decrease. Also, a double-sided aligner is required.

Further, according to the above-described conventional mask manufacturing method, after the resist is applied to the surface side of the silicon wafer 202, the baking of the resist tends to be uneven. The baking is performed by placing the silicon wafer 202 on a hot plate. At this time, since the silicon wafer 202 is supported by the struts 204, the heat conduction from the hot plate becomes uneven within the wafer surface.
If the baking becomes non-uniform, the processing accuracy of the pattern decreases.

When dry etching is performed on the silicon layers 206 and 232 of the stencil masks 201 and 231 to form the aperture 205, or when the membrane mask 2
21 is subjected to dry etching to form the scatterer 2
Also when forming 24, the silicon wafer 202 is supported by the struts 204. Therefore, the thin film portion 2
A gap is formed between 03, 222 and the stage of the etching apparatus.

In the worst case, when the mechanical strength of the entire mask is reduced and the influence of heat generated during etching is applied, the mask is damaged in the worst case. Even when the mask is not damaged, if the mask is deformed due to heat generated during etching or the like, the thin film portions 203 and 222 cannot be stably supported. As a result, the processing accuracy of the pattern is reduced, and the pattern dimensions are varied.

The present invention has been made in view of the above problems, and accordingly, the present invention provides a mask master capable of improving mask manufacturing efficiency and improving pattern processing accuracy.
It is an object to provide a mask, a method for manufacturing a mask, and a method for manufacturing a semiconductor device.

[0032]

In order to achieve the above object, a mask master according to the present invention comprises a thin film for locally transmitting electromagnetic waves having a predetermined wavelength applied to a first surface to a second surface. A protective layer formed on the first surface of the thin film and capable of being removed from the thin film; and a part of the thin film on the second surface for blocking the electromagnetic waves transmitted through the thin film. And a thin film supporting portion formed so as not to support the thin film.

The mask master of the present invention is preferably characterized in that the thin film has an aperture through which the electromagnetic wave passes, and blocks the electromagnetic wave in a portion other than the aperture. The mask master of the present invention is preferably characterized in that the electromagnetic wave is an electron beam, X-ray, EUV light or ion beam.

[0034] The mask master of the present invention preferably further comprises a first etching stopper layer capable of lowering the etching rate than that of the thin film supporting portion between the second surface of the thin film and the thin film supporting portion. It is characterized by having. The mask master of the present invention preferably further comprises a second etching stopper layer capable of lowering the etching rate than the protective layer between the protective layer and the first surface of the thin film. I do.

Preferably, in the mask master according to the present invention, the thin film is formed in a portion where the thin film supporting portion is not formed.
A scatterer that scatters and blocks the electromagnetic wave is further provided on a surface, and the electromagnetic wave is transmitted through portions other than the scatterer. The mask master of the present invention is preferably
The electromagnetic wave is an electron beam, X-ray, EUV light or ion beam.

Preferably, the mask master of the present invention further comprises a first etching stopper layer capable of lowering an etching rate than that of the thin film supporting portion between the second surface of the thin film and the thin film supporting portion. It is characterized by having. The mask master of the present invention preferably further comprises a second etching stopper layer capable of lowering the etching rate than the protective layer between the protective layer and the first surface of the thin film. I do.

The mask master of the present invention is preferably characterized in that the thin film support is formed in a shape having at least one rectangular opening on the second surface of the thin film. More preferably, the mask master of the present invention is characterized in that the thin film support is formed in a shape in which a plurality of rectangular openings are arranged in a matrix on the second surface of the thin film. .

According to the mask master of the present invention, the presence of the protective layer increases the mechanical strength and prevents the mask master from being damaged even when the mask master is stored or transported before using the mask. Further, according to the mask master of the present invention, it is possible to proceed with the manufacture of the mask in a state where the mask is protected by the protective layer. Therefore, damage to the mask master during the manufacturing process is prevented, and the yield of the mask is improved.

In order to achieve the above object, a mask master of the present invention comprises a thin film, a protective layer formed on the first surface of the thin film and capable of being removed from the thin film, A thin film supporting portion formed on a part of the second surface to support the thin film. The mask master of the present invention preferably further comprises a first etching stopper layer between the second surface of the thin film and the thin film supporting portion, the first etching stopper layer being capable of lowering the etching rate than the thin film supporting portion. Features. The mask master of the present invention
Preferably, a second layer between the protective layer and the first surface of the thin film, the second layer having a lower etching rate than the protective layer.
Characterized by further comprising an etching stopper layer.

Alternatively, the mask master of the present invention preferably scatters and blocks electromagnetic waves of a predetermined wavelength formed on the second surface of the thin film where the thin film support is not formed. It is characterized by further having a barrier layer made of a material to be formed. The mask master of the present invention preferably further comprises a first etching stopper layer between the second surface of the thin film and the thin film supporting portion, the first etching stopper layer being capable of lowering the etching rate than the thin film supporting portion. Features.

Preferably, the mask master of the present invention further comprises a second etching stopper layer between the protective layer and the first surface of the thin film, the second etching stopper layer being capable of lowering the etching rate than the protective layer. It is characterized by. The mask master of the present invention is preferably characterized in that the thin film support is formed in a shape having at least one rectangular opening on the second surface of the thin film. More preferably, the mask master of the present invention is characterized in that the thin film support is formed in a shape in which a plurality of rectangular openings are arranged in a matrix on the second surface of the thin film. .

Thus, it is possible to increase the mechanical strength of the mask master in a state where the thin film supporting portion and the thin film are formed, and to keep them in stock. Therefore, the TAT for mask manufacture is reduced. In addition, the mask master whose mechanical strength is reinforced by the protective layer can be distributed.

In order to achieve the above object, a mask of the present invention comprises a thin film that locally transmits an electromagnetic wave having a predetermined wavelength irradiated on the first surface side to the second surface side, A thin film supporting portion for supporting the thin film, which is formed so as not to block the electromagnetic wave transmitted through the thin film, and the thin film supporting portion on the second surface of the thin film are formed on a part of the two surfaces. Not formed, scatter the electromagnetic waves,
And a blocking scatterer.

Accordingly, on the first surface side of the thin film of the mask,
It is easy to provide a protective layer that can be easily removed before using the mask. Therefore, it is possible to prevent the mask from being damaged in the manufacturing process of the mask, and to improve the yield of the mask.

In order to achieve the above object, a method for manufacturing a mask according to the present invention comprises the steps of forming a thin film on one surface of a substrate, forming a protective layer on the thin film, Removing a part of the substrate from the surface side to locally expose the thin film, a transmitting portion through which an electromagnetic wave of a predetermined wavelength is transmitted, and a blocking portion through which the electromagnetic wave is blocked, in the exposed portion of the thin film And a step of removing the protective layer.

The method for manufacturing a mask according to the present invention preferably comprises
The step of providing the transmitting portion and the blocking portion includes forming an aperture by removing a portion of the exposed portion of the thin film from the substrate side, and blocking the portion other than the aperture by using the aperture as the transmitting portion. It is characterized by including a step of forming a part.

In the method of manufacturing a mask according to the present invention, more preferably, the step of providing the transmitting portion and the blocking portion includes a step of spraying and applying a resist to at least an exposed portion of the thin film; Performing exposure and development, transferring a predetermined mask pattern, etching the thin film using the resist as a mask, forming the aperture, and removing the resist. .

In the method of manufacturing a mask according to the present invention, more preferably, in the step of spraying the resist, at least one of the nozzle and the substrate is moved while spraying the resist from the nozzle, and the resist is sprayed on the exposed portion. The method includes a step of performing scanning by the nozzle.

Alternatively, the method for producing a mask of the present invention
Preferably, the step of providing the transmission unit and the blocking unit includes:
A step of forming a blocking layer made of a material that scatters and blocks the electromagnetic wave on the exposed portion of the thin film, and removing a part of the blocking layer, and using the portion from which the blocking layer is removed as a transmission part, the blocking. The method includes the step of setting a remaining portion of the layer as the blocking portion.

The method for manufacturing a mask according to the present invention preferably comprises
The step of providing the transmission portion and the blocking portion includes spraying and applying a resist on the surface of the blocking layer, exposing and developing the resist, and transferring a predetermined mask pattern; and A step of etching the barrier layer using the mask as a mask, and a step of removing the resist. The method of manufacturing a mask according to the present invention, more preferably, in the step of spraying the resist, while spraying the resist from a nozzle, moving at least one of the nozzle and the substrate, and using the nozzle in the exposed portion. The method includes a step of performing a scan.

The method for manufacturing a mask according to the present invention preferably comprises
Forming the first thin film on the one surface of the substrate before forming the thin film, further comprising forming a first etching stopper layer capable of lowering an etching rate than the substrate on the one surface; Is the first substrate on the substrate.
Forming the thin film via an etching stopper layer.

The method for manufacturing a mask according to the present invention preferably comprises
Before forming a protective layer on the thin film, further comprising a step of forming a second etching stopper layer capable of lowering the etching rate than the protective layer on the thin film, the step of forming the protective layer, Forming a protective layer on the thin film via the second etching stopper layer.

The method for manufacturing a mask according to the present invention preferably comprises
The step of removing a part of the substrate includes dry etching or wet etching of the substrate. In the method of manufacturing a mask according to the present invention, preferably, the step of removing a part of the substrate includes a step of exposing the thin film in at least one rectangular shape. In the method of manufacturing a mask according to the present invention, the step of removing a part of the substrate preferably further includes a step of exposing the thin film in a plurality of rectangular shapes arranged in a matrix.

As a result, it is not necessary to perform the alignment in the photolithography process on both surfaces of the wafer, and the alignment is facilitated. Therefore, the yield of the mask can be improved. Further, according to the mask manufacturing method of the present invention, the substrate is stably supported by the entire protective layer when etching the thin film or the blocking layer. Therefore, breakage of the thin film during etching is prevented. Further, even when the resist is baked, the substrate is stably supported by the entire surface of the protective layer, so that the resist is baked uniformly and the dimensional variation of the resist pattern can be reduced.

Further, in order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a lithography mask having a predetermined mask pattern, and a step of forming an electromagnetic wave on a substrate through the lithography mask. Irradiate,
Transferring the mask pattern to the substrate, wherein the step of forming the lithography mask comprises: forming a thin film on one surface of a mask substrate; Forming a protective layer on, and removing a portion of the mask base material from the other surface side of the mask base material, the step of locally exposing the thin film,
The method includes a step of providing a transmitting portion through which an electromagnetic wave of a predetermined wavelength is transmitted, a blocking portion through which the electromagnetic wave is blocked, and a step of removing the protective layer on the exposed portion of the thin film.

As a result, the TAT in the mask manufacturing process is shortened, and the yield of the mask is improved, so that the manufacturing cost of the semiconductor device can be reduced. Further, since the mask pattern is formed with high accuracy, the transfer performance of the mask pattern is improved, and the yield of the semiconductor device can be improved.

[0057]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a mask master, a mask, a method for manufacturing a mask, and a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. (Embodiment 1) FIG. 1 (a) is a schematic view of a stencil mask for electron beam transfer type lithography manufactured by the mask manufacturing method of the present embodiment, and FIG. 1 (b) is a part of FIG. 1 (a). It is the perspective view which expanded (A). FIG. 2A shows FIG.
It is sectional drawing in XX 'of (a). The stencil mask 101 shown in FIG. 1 and FIG.
Applicable to IL.

The stencil mask 101 is formed on a silicon wafer 102 of, for example, 8 inches in size by 1.13 mm ×
1.13mm multiple thin film parts (membrane)
103. The thickness of the membrane 103 is about 2 μm. The membranes 103 are separated from each other by beams called struts 104. Strut 104
Is 170 μm, for example.

The strut 104 is a stencil mask 10
It acts as a support to maintain the mechanical strength of the first. When the stencil mask 101 is formed using an 8-inch wafer, the thickness of the strut 104 is, for example, 725 μm, but the thickness of the strut 104 can be changed as long as the membrane 103 is held.

As shown in FIG. 1B, the membrane 10
3 is a 1 mm square pattern region 10 to be irradiated with an electron beam.
5 and a margin called the skirt 106 around it. The aperture 107 shown in FIG.
It is formed in the pattern area 105 shown in FIG.

In order to manufacture the stencil mask 101 as described above, first, as shown in FIG. 2B, an SOI wafer 111 is formed, and a protective layer 112 is formed on the surface of the SOI wafer 111. The SOI wafer 111 has a silicon layer 114 on one surface of the silicon wafer 102 via a silicon oxide film 113, and has a back surface silicon oxide film 115 on the other surface of the silicon wafer 102.

The silicon oxide film 113 is formed on the silicon wafer 1
02 is used as an etching stopper layer in the step of forming struts 104 by etching the rear surface of the substrate 02. Hereinafter, in order to distinguish it from other etching stopper layers, the etching stopper layer provided for such a purpose is referred to as a first etching stopper layer for convenience.

The SOI wafer 111 can be formed by, for example, a SIMOX method or a bonding method. The thickness of the silicon wafer 102 is, for example, 725 μm, the thickness of the silicon oxide film 113 is, for example, 50 nm, and the thickness of the silicon layer 114 is, for example, 2 μm.

Although not shown, a second etching stopper layer made of, for example, ruthenium may be formed between the silicon layer 114 and the protective layer 112. This makes it possible to clarify the end point of the etching when removing the protective layer 112 from the silicon layer 114. However, for example, when the etching amount can be controlled with high accuracy by controlling the etching conditions including the etching time, or when the reaction product gas is monitored in dry etching to check the etching amount in situ, the second method is used. It is not always necessary to provide the etching stopper layer.

The backside silicon oxide film 115 is not necessarily provided. However, if dry etching is performed for the thickness of the wafer using the resist as a mask, the resist may also be etched and a pattern may not be formed. As an offset film for preventing this, for example, a silicon oxide film of about 100 nm may be formed on the back surface of the silicon wafer 102. The backside silicon oxide film 115 can be formed by, for example, chemical vapor deposition (CVD). Backside silicon oxide film 115 by CVD or the like
Is not particularly formed, a natural oxide film having a thickness of about several nm becomes the back-side silicon oxide film 115.

The protective layer 112 has a thickness of, for example, 500
A polysilicon layer of nm is formed by CVD. The material of the protective layer 112 may be an etchant in which the silicon layer 114 is not etched or a material that can be easily removed under etching conditions. Thereby, the membrane 103
After the aperture 107 is formed on the protective layer 11 without damaging the membrane 103 as shown in FIG.
2 can be removed. SiN, S instead of polysilicon layer
A layer made of a material such as iO ₂ , Al or Cr
It may be formed as 12. The thickness of the protective layer 112 may be any thickness that can sufficiently reinforce the strength of the silicon layer 114 serving as the membrane 103.

Next, as shown in FIG. 2C, a resist 116 is formed on the back surface of the silicon wafer 102. The resist 116 is formed in a pattern of the struts 104 shown in FIG. 1, that is, a pattern in which squares of 1.13 mm × 1.13 mm are arranged in a matrix at intervals of 170 μm. The resist 116 is formed by, for example, coating the entire surface by spin coating, and then performing exposure and development.

Subsequently, from the back side of the SOI wafer 111, the silicon wafer 10 is
2 is dry-etched. For this dry etching, a fluorine-based gas such as SF ₆ or NF ₃ is used as an etching gas. Thus, a strut 104 made of silicon is formed.

Next, as shown in FIG. 2D, the silicon oxide film 113 is etched using the struts 104 as a mask. This etching is, for example, wet etching using hydrofluoric acid. Thereby, the silicon oxide film 113 in the portion of the membrane 103 shown in FIG. 1 is removed. Thereafter, as shown in FIG.
Is removed. Further, the backside silicon oxide film 115 is also removed if necessary.

According to the conventional mask manufacturing method, since the mechanical strength of the mask is reduced by forming the strut, it is difficult to store or transport the mask master with the strut formed. On the other hand, according to the mask manufacturing method of the present embodiment, since the protective layer 112 is formed, the mechanical strength of the mask master is maintained even after the struts 104 are formed.

Therefore, even if the silicon wafer 102 is dry-etched to form the struts 104 before the pattern design is completed, damage during storage of the mask master is prevented. Strut 104
Since the dry etching for forming the pattern takes a long time, the TAT from the pattern design to the completion of the mask can be reduced by forming the strut 104 in advance and keeping it in stock. Further, since damage when the mask master is transported with the struts 104 formed is reduced, the mask master at the stage shown in FIG. 3E can be supplied as a product as necessary. .

Next, as shown in FIG. 3F, a resist 117 is applied to the surface of the silicon layer 114 on the strut 104 side. As the resist 117, for example, a positive resist FEP102 (manufactured by Fuji Film Ohlin) is applied. Since there are irregularities due to the struts 104 on the resist application surface, the resist cannot be applied by a method such as spin coating. Methods for applying a resist to such an uneven surface are described in, for example, Japanese Patent No. 3084339, Japanese Patent Application Laid-Open No. 10-32493, and Japanese Patent Application Laid-Open No. 8-30.
No. 6614, Japanese Unexamined Patent Publication No. 11-329938, or Proceedings of the 61st Japan Society of Applied Physics (2000)
No.2 p.593 4a-X-1.

According to the method described in Japanese Patent No. 3084339, a resist coating solution is placed on a substrate, the coating solution is spread thinly on the substrate with a scanner plate, and a slit-shaped nozzle that follows immediately after the scanner plate. The coating is evenly pressed onto the substrate by the blowing air pressure.

In the method of forming a resist film described in Japanese Patent Application Laid-Open No. 10-32493, a step of applying a resist to a substrate surface and, for example, heating a temporary surface of the substrate and cooling the upper surface to partially change the resist coating film are performed. Forming a deteriorated layer and a non-degraded layer, and removing the non-degraded layer.

According to the resist coating method described in JP-A-8-306614, the resist is applied to the entire surface of the substrate by moving the substrate or the nozzle and spraying the resist in a mist form from the nozzle. JP-A-11-32
According to the coating method described in Japanese Patent No. 9938, nozzles are provided at a plurality of positions separated by a predetermined interval, and a processing agent such as a resist coating solution is supplied from the nozzles while relatively moving the nozzles and the substrate to be processed. Supply.

In addition, in the 61st Annual Meeting of the Japan Society of Applied Physics (2000) No.2 p.593 4a-X-1, an ultrafine nozzle for dripping a resist is reciprocated in the y-direction, Describes a result of applying a resist in a thinner atmosphere in a nozzle scan coating method in which the resist is moved at a constant speed in the x direction. Whereas in a normal coating, the film thickness increases at the edge portion, when a resist is applied in a thinner atmosphere, a local increase in the film thickness is suppressed.

The strut 10 is obtained by the above method.
The resist 117 can be applied to the silicon layer 114 on which the resist layer 4 is formed with a uniform thickness. In the case of spin coating, the amount of resist scattered around the wafer and lost is larger than the amount of resist deposited on the wafer, which is disadvantageous in terms of resist cost. On the other hand, when the resist is applied using the nozzle as described above, it is possible to selectively supply the resist only to a necessary portion on the wafer, and it is possible to reduce the amount of the resist used.

Silicon layer 1 surrounded by struts 104
When applying the resist 117 on the surface 14, the strut 1
There is a case where the resist is thinly attached (about several μm in thickness) also to the side surface of the substrate 04. However, as shown in FIG. 1B, the pattern area 105 of the membrane 103 where the pattern is formed has a size of 1 mm × 1 mm, and the distance between the strut 104 and the pattern area 105 is 65 μm.
m. Therefore, the resist 117 adhering to the side surface of the strut 104 does not pose a problem in forming a mask pattern.

Next, as shown in FIG. 3G, the resist 117 is exposed and developed to form a resist 118 corresponding to the LSI mask pattern in the pattern region 105 shown in FIG. 1B. . According to the conventional mask manufacturing method, when transferring the mask pattern to the resist on the front surface side of the wafer, a double-sided aligner for aligning with the strut on the back surface side of the wafer is required. On the other hand, according to the mask manufacturing method of the present embodiment, since the resist 117 on the same side as the strut 104 is exposed,
Alignment is easy and no double-sided aligner is required.

Subsequently, using the resist 118 as a mask,
Dry etching is performed on the recon layer 114. This dry
For etching, for example, SF is used as an etching gas.₆ And
NF _Three And the like. As a result, the predetermined
Membrane 10 with patterned aperture 107
3 is formed. Thereafter, as shown in FIG.
The dist 118 is removed.

According to the mask manufacturing method of this embodiment, the etching of the silicon layer 114 is performed from the strut 104 side. Therefore, during the etching, the entire surface of the protective layer 112 is in contact with the stage of the etching apparatus, and the etched surface is stably supported. This prevents deformation of the stencil mask due to heat generation during etching and the like, and improves pattern processing accuracy.

According to the conventional mask manufacturing method,
When the aperture is formed on the membrane, there is a problem that the mechanical strength of the mask is significantly reduced, and the mask is easily damaged during storage or transportation. In contrast, according to the mask manufacturing method of the present embodiment, the membrane 10
3 after the aperture 107 is formed.
This maintains the mechanical strength of the mask.

Further, according to the mask manufacturing method of the present embodiment, the silicon layer 114 is etched
When the etching is performed from the 04 side, there is a subtle difference in the sectional shape of the aperture as compared with a conventional mask in which etching is performed from the wafer surface side. When etching is performed from the strut 104 side, the aperture tends to have a tapered cross-sectional shape in which the diameter of the aperture is larger on the back surface side (strut 104 side) than on the wafer front surface side. On the other hand, when etching is performed from the wafer surface side, on the other hand, the aperture tends to have a tapered cross-sectional shape in which the aperture diameter becomes smaller on the strut side.

When performing EPL, an electron beam is irradiated from the wafer surface side. According to the tapered shape of the aperture of the conventional stencil mask, scattering of electrons easily occurs on the side wall of the aperture. On the other hand, in the case of the mask manufactured by the manufacturing method of the present embodiment, the electron beam hardly collides with the side wall of the aperture while passing through the aperture. Therefore, the transfer performance of the mask pattern in the EPL can be improved by controlling the tapered shape of the aperture.

The protective layer 112 may be removed before the mask is used for the EPL. If necessary, the protective layer 112 can be left just before the use of the mask. Therefore, on the premise that the protective layer 112 is removed before use, it is also possible to supply a mask at the stage shown in FIG. 3H as a product.

As shown in FIG. 2A, by removing the protective layer 112, a stencil mask 201 is formed. When a polysilicon layer is formed as the protection layer 112, the protection layer 112 is formed by dry etching using Cl ₂ or SF ₆ or wet etching.
Can be removed.

According to the above-described mask manufacturing method of the present embodiment, struts can be formed on a wafer in advance before pattern design is completed. As shown in FIG. 3E, by securing the mask master at the stage where the struts 104 are formed as stock, the TAT for mask manufacturing is reduced. In addition, the mask master at the stage where the struts are formed has a mechanical strength reinforced by the protective layer 112, and thus can be distributed as a semi-finished product.

According to the mask manufacturing method of the present embodiment described above, since the resist to which the mask pattern is transferred is formed on the same side as the strut, it is not necessary to perform the alignment in the photolithography process on both sides of the wafer. Alignment is facilitated. Thereby, the yield of the mask can be improved.

According to the above-described mask manufacturing method of the present embodiment, when forming the aperture 107 on the membrane 103, the wafer is supported not by struts but by the entire surface of the protective layer 112. Therefore, the wafer is stably supported, and damage to the membrane during etching is prevented. When the resist is baked after the application of the resist 117, the wafer is supported not by struts but by the entire surface of the protective layer 112. Therefore, the temperature distribution in the wafer surface is small, and the dimensional variation of the resist pattern can be reduced.

According to the mask manufacturing method of the present embodiment, it is possible to proceed with the manufacturing of the mask in a state where the membrane 103 is protected by the protective layer 112. Therefore, damage to the mask master is prevented, and the yield of the mask is improved. Further, as shown in FIG. 3H, in a state where the aperture 107 is formed in the membrane 103 and the protective layer 112 is left, the mask has high mechanical strength and the mask is hardly damaged, so that the storage and transportation are performed. The handling of the mask containing is easy.

In the method of manufacturing a semiconductor device according to the present embodiment, a stencil mask is manufactured according to the method of manufacturing a mask according to the above-described embodiment, and the manufactured mask is, for example, PREVA.
It is used for EPL such as IL. According to the method for manufacturing a semiconductor device of the present embodiment, the TAT for manufacturing the mask is reduced, and the yield of the mask is improved, so that the manufacturing cost of the semiconductor device is reduced. Further, since the pattern processing accuracy of the mask is high, a fine pattern can be formed on the wafer with high accuracy in the EPL process.

(Embodiment 2) FIG. 4 (a) is a schematic view of an electron beam transfer type lithography membrane mask manufactured by the mask manufacturing method of the present embodiment, and FIG. 4 (b) is FIG. 4 (a). FIG. 3 is an enlarged perspective view of a part (A) of FIG. FIG.
FIG. 4A is a cross-sectional view taken along line XX ′ of FIG.
The membrane mask 121 shown in FIGS. 4 and 5 can be applied to, for example, SCALPEL.

The membrane mask 121 is formed, for example, on an 8-inch silicon wafer 102 by 1 mm × 12 mm.
And a plurality of thin film portions (membrane) 122 having a size of The thickness of the membrane 122 is, for example, about 150 nm. The membranes 122 are separated from each other by beams called struts 104. The width of the strut 104 is, for example, 300 μm.

The strut 104 is a membrane mask 12
It acts as a support to maintain the mechanical strength of the first. When the membrane mask 121 is formed using an 8-inch wafer, the thickness of the strut 104 is, for example, 725 μm, but the thickness of the strut 104 can be changed as long as the membrane 122 is held.

As shown in FIGS. 4B and 5A, the membrane 122 is made of, for example, a silicon nitride film 123.
Part of the support layer made of As shown in FIG. 5A, a scatterer 124 corresponding to the mask pattern of the LSI is formed on the surface of the silicon nitride film 123. As the scatterer 124, for example, a heavy metal such as chromium and tungsten is used, and the thickness of the scatterer 124 is 30 to 5 mm.
It is about 0 nm. Diamond, DLC, or the like can be used as the scatterer 124 in addition to heavy metals.

In the conventional membrane mask, as shown in FIG. 12, a scatterer 224 and a strut 204 are formed on opposite surfaces of a silicon nitride film 223. On the other hand, according to the membrane mask 122 of the present embodiment, the scatterer 124 and the strut 104
Formed on the same side.

By providing the scatterer 124 and the strut 104 on the same side as in this embodiment, the surface of the silicon nitride film 123 has no irregularities and the silicon nitride film 12
3 It is easy to form a protective layer on the surface or remove the protective layer. In addition, the scatterer 124 and the strut 10
In the case where the membrane mask 4 provided on the same side is used, there is no particular problem in performing the EPL as compared with the case where the conventional membrane mask is used.
PL can be performed.

In order to manufacture the above-described membrane mask 121, first, as shown in FIG. 5B, a silicon nitride film 123 is formed on the silicon wafer 102. As the silicon wafer 102, for example, an 8-inch wafer is used. The silicon nitride film 123 is formed by, for example, low-pressure CVD or the like, and has a thickness of, for example, 150 nm. Instead of the silicon nitride film 123, a layer made of silicon, silicon carbide, diamond, DLC, or the like may be formed.

A polysilicon layer having a thickness of, for example, 2 μm is formed as a protective layer 112 on the silicon nitride film 123.
The material of the protective layer 112 may be an etchant in which the support layer such as the silicon nitride film 123 is not etched or a material that can be easily removed under etching conditions. The thickness of the protective layer 112 may be any thickness as long as the membrane 122 is supported.

Although not shown, the silicon wafer 10
Between the silicon nitride film 123 and the silicon nitride film 123, a layer made of a material such as Cr, SiO ₂ or Al ₂ O ₃ may be formed as a first etching stopper layer. The material of the first etching stopper layer is not limited to the above, and the strut 1
Any material may be used as long as it does not react with an etching gas (for example, a fluorine-based gas) used for etching for processing the 04 and has little sputter product.

Although not shown, the silicon nitride film 12
A second etching stopper layer made of, for example, ruthenium may be formed between the layer 3 and the protective layer 112.
Thereby, when the protective layer 112 is removed from the silicon nitride film 123, the end point of the etching can be clarified. However, for example, when the etching amount can be controlled with high precision by controlling the etching conditions including the etching time, or when the reaction product gas is monitored in dry etching to check the etching amount in situ, the second method is used. It is not always necessary to provide the etching stopper layer.

Next, as shown in FIG. 5C, a resist 125 is formed on the back side of the silicon wafer 102 by struts 1.
04 pattern (see FIG. 4), that is, 1 mm × 12
It is formed in a pattern in which rectangles of mm are arranged in a matrix at intervals of 300 μm. The resist 125 is formed by, for example, applying the whole surface by spin coating, and then performing exposure and development. Further, dry etching is performed from the back surface side of the silicon wafer 102 using the resist 125 as a mask. For this dry etching, a fluorine-based gas such as SF ₆ or NF ₃ is used as an etching gas. Thereby, the strut 104 made of silicon is formed.
Is formed.

Thereafter, as shown in FIG. 5D, the resist 125 is removed. Next, as shown in FIG.
A chromium layer and a tungsten layer are sequentially formed on the surface of the silicon nitride film 123 on the strut 104 side, and a laminated film 126 is formed. The thickness of the chromium layer is, for example, 5 nm, and the thickness of the tungsten layer thereover is, for example, 25 nm.

According to the mask manufacturing method of the present embodiment,
By forming the protective layer 112, the mechanical strength of the mask master is maintained even after the struts 104 are formed, similarly to the mask manufacturing method of the first embodiment. Therefore,
Before the pattern design is completed, a silicon wafer 10
Even when the struts 104 are formed by performing dry etching on the mask 2, damage during storage of the mask master is prevented.

Since the dry etching for forming the strut 104 requires a long time, the strut 104 is formed in advance.
By forming 4 and keeping it in stock, it is possible to shorten the TAT from the pattern design to the completion of the mask. Further, since damage when the mask master is transported in a state where the struts 104 are formed is reduced, if necessary,
The mask master at the stage shown in FIG. 5D or FIG. 6E can be supplied as a product.

Next, as shown in FIG.
A resist 127 is applied to the surface of the substrate. Resist 12
As 7, for example, a positive resist FEP102 (manufactured by Fuji Film Ohlin) is applied. Since there are irregularities due to the struts 104 on the resist coating surface, the resist 1
27 is applied in the same manner as in the first embodiment, for example, as described in
84339, JP-A-10-321493,
JP-A-8-306614 and JP-A-11-32
938, or the method described in the 61st JSAP Academic Lecture Meeting (2000) No.2 p.593 4a-X-1.

Next, as shown in FIG. 6G, the resist 127 is exposed and developed to form a resist 128 corresponding to the LSI mask pattern on the membrane 122 shown in FIG. 4B. According to the mask manufacturing method of the present embodiment, the resist 127 on the same side as the strut 104 is used.
Since the first exposure is performed, alignment is easy as in the first embodiment, and a double-sided aligner is not required. Further, since there is a margin between the strut 104 and the region (pattern region) of the membrane 122 where the mask pattern is actually formed, the problem of misalignment in the lithography process is prevented. You.

Next, as shown in FIG. 6H, reactive ion etching (RIE; reactive ion etching) is performed on the chromium and tungsten laminated film 126 using the resist 128 as a mask.
ionetching). As an etching gas for dry etching, for example, Cl ₂ or O ₂ is used. afterwards,
The resist 128 is removed. Thereby, the membrane 122 having the scatterers 124 in a predetermined pattern is formed.

According to the mask manufacturing method of this embodiment, the etching of the laminated film 126 is performed from the strut 104 side. Thus, while the etching takes place, the protective layer 1
12, the entire surface is in contact with the stage of the etching apparatus,
The etched surface is stably supported. This prevents deformation of the membrane mask due to heat generation during etching and the like, and improves pattern processing accuracy.

Thereafter, as shown in FIG. 5A, by removing the protective layer 112, the membrane mask 121 is removed.
Is formed. When a polysilicon layer is formed as the protective layer 112, the protective layer 112 can be removed by dry etching using, for example, Cl ₂ or SF ₆ or wet etching.

The protective layer 112 may be removed before the mask is used for the EPL. If necessary, the protective layer 112 can be left just before the use of the mask. Therefore, on the premise that the protective layer 112 is removed before use, it is also possible to supply the mask at the stage shown in FIG. 6H as a product.

According to the above-described mask manufacturing method of the present embodiment, struts can be formed on a wafer in advance before pattern design is completed. As shown in FIG. 5D, the mask master at the stage where the struts are formed, or as shown in FIG.
By keeping the mask master at the stage where the layer made of the material is formed in stock, the TAT
Is shortened. In addition, the mask master on which the struts are formed can be distributed as a semi-finished product because the mechanical strength is reinforced by the protective layer 112.

According to the mask manufacturing method of the present embodiment described above, since the resist to which the mask pattern is transferred is formed on the same side as the struts, it is not necessary to perform the alignment in the photolithography process on both sides of the wafer. Alignment is facilitated. Thereby, the yield of the mask can be improved.

According to the mask manufacturing method of the present embodiment, when the laminated film 126 is etched to form the scatterer 124, the wafer is not a strut but a protective layer 112.
Supported by the whole surface. Therefore, the wafer is stably supported, and damage to the membrane 122 during etching is prevented. Also, after baking of the resist after application of the resist 127, the wafer is supported not by struts but by the entire surface of the protective layer 112. Therefore, the temperature distribution in the wafer surface is small, and the dimensional variation of the resist pattern can be reduced.

According to the mask manufacturing method of the present embodiment, it is possible to proceed with the manufacture of the mask in a state where the membrane 122 is protected by the protective layer 112. Therefore, damage to the mask master is prevented, and the yield of the mask is improved. Further, as shown in FIG. 6H, a scatterer 124 is formed on the membrane 122 and the protective layer 11 is formed.
In the state where 2 is left, the mechanical strength of the mask is high and the mask is not easily damaged, so that handling of the mask including storage and transportation becomes easy.

In the method for manufacturing a semiconductor device according to the present embodiment, a membrane mask is manufactured according to the method for manufacturing a mask according to the above-described embodiment, and the manufactured mask is, for example, SCALP.
It is used for EPL such as EL. According to the method for manufacturing a semiconductor device of the present embodiment, the TAT for manufacturing the mask is reduced, and the yield of the mask is improved, so that the manufacturing cost of the semiconductor device is reduced. Further, since the pattern processing accuracy of the mask is high, a fine pattern can be formed on the wafer with high accuracy in the EPL process.

(Embodiment 3) FIG. 7 (a) is a schematic view of a stencil mask for electron beam transfer type lithography manufactured by the mask manufacturing method of the present embodiment, and FIG. 7 (b) is FIG. 7 (a). FIG. 2 is an enlarged perspective view of a part (near the membrane 103). FIG. 8A is a cross-sectional view taken along line XX ′ of FIG. 7A. The stencil mask 131 shown in FIGS. 7 and 8 can be applied to, for example, LEEPL.

The stencil mask 131 is formed on a silicon wafer 102 of, eg, an 8-inch size by 20 mm × 20 m.
It has a thin film portion (membrane) 103 having a size of m.
The thickness of the membrane 103 is, for example, 500 nm. According to the present embodiment, one stencil mask 131 has one
Although a plurality of membranes 103 are formed, a plurality of membranes separated by struts can be formed on one mask as in the first embodiment.

Silicon wafer 1 around membrane 103
02 (strut 104) is a stencil mask 131
Acts as a support that maintains the mechanical strength of the When the stencil mask 131 is formed using an 8-inch wafer, the thickness of the strut 104 is, for example, 725 μm, but the thickness of the strut 104 can be changed as long as the membrane 103 is held.

As shown in FIG. 7B, the membrane 10
3 is a 20 mm square pattern area 1 to be irradiated with an electron beam.
05 and a margin called the skirt 106 around it. The skirt 106 is adjacent to the strut 104. The aperture 107 shown in FIG. 8A is formed in the pattern area 105.

In order to manufacture the stencil mask 131 as described above, first, as shown in FIG. 8B, an SOI wafer 111 is manufactured, and a protective layer 112 is formed on the front side of the SOI wafer 111. The SOI wafer 111 has a silicon layer 114 on one surface of the silicon wafer 102 with a silicon oxide film 113 interposed therebetween.

The silicon oxide film 113 is formed on the silicon wafer 1
02 is used as a first etching stopper layer in the step of forming a strut 104 by etching the back surface of the substrate. The thickness of the silicon wafer 102 is, for example, 725 μm, the thickness of the silicon oxide film 113 is, for example, 50 nm, and the thickness of the silicon layer 114 is, for example, 5 μm.
00 nm.

Although not shown, a second etching stopper layer made of, for example, ruthenium may be formed between the silicon layer 114 and the protective layer 112 as in the first embodiment. As a result, the protective layer 112 is
When removing from 4, the end point of the etching can be clarified. However, for example, when the etching amount can be controlled with high accuracy by controlling the etching conditions including the etching time, or when the reaction product gas is monitored in dry etching and the etching amount is confirmed in situ, the second method is used. It is not always necessary to provide the etching stopper layer.

The strut 104 is attached to the silicon wafer 102.
Embodiment 1 is formed by wet etching.
In FIG. 2, the backside silicon oxide film 115 (see FIG. 2B) used as an etching offset film may not be provided. As in the first embodiment, the SOI wafer 111 can be formed by, for example, a SIMOX method or a bonding method.

As the protective layer 112, for example, a thickness of 500
A polysilicon layer of nm is formed by CVD. The material of the protective layer 112 may be an etchant in which the silicon layer 114 is not etched or a material that can be easily removed under etching conditions. Thereby, the membrane 103
After forming the aperture 107 in the protective layer 11 without damaging the silicon layer 114 as shown in FIG.
2 can be removed. Further, the thickness of the protective layer 112 may be a thickness that can sufficiently reinforce the strength of the membrane 103.

Next, as shown in FIG. 8C, a resist 132 is formed on the back surface of the silicon wafer 102. The resist 132 is formed in the pattern of the strut 104 shown in FIG. 7, that is, a square pattern of 20 mm × 20 mm. The resist 132 is formed by, for example, spin-coating the entire surface and then performing exposure and development.

Subsequently, from the back side of the SOI wafer 111, the silicon wafer 10 is
2 is subjected to wet etching. Alternatively, dry etching may be performed using a fluorine-based gas such as SF ₆ or NF ₃ as an etching gas. Thus, a strut 104 made of silicon is formed. According to the wet etching, the strut 104 can be formed in a shorter time (usually within one hour, for example, about ten minutes) than the dry etching, but the cross section of the strut 104 is tapered. Further, the silicon oxide film 113 other than the struts 104 is removed by, for example, wet etching using hydrofluoric acid.

Next, as shown in FIG. 8D, the resist 132 is removed. According to the mask manufacturing method of the present embodiment, by forming the protective layer 112, the mechanical strength of the mask master is maintained even after the struts 104 are formed, similarly to the mask manufacturing method of the first embodiment. . Therefore, before the pattern design is completed, dry etching is performed on the silicon wafer 102 in advance to
Is formed, damage during storage of the mask master is prevented.

If the struts 104 are formed in advance and are kept in stock, the TAT from the pattern design to the completion of the mask can be reduced. Further, since damage when the mask master is transported with the struts 104 formed is reduced, the mask master at the stage shown in FIG. 8D can be supplied as a product as necessary. .

Next, as shown in FIG. 9E, a resist 133 is applied to the surface of the silicon layer 114 on the strut 104 side. As the resist 133, for example, a positive resist FEP102 (manufactured by Fuji Film Ohlin) is applied. The application of the resist 133 is performed in the same manner as in the first embodiment, for example, in Japanese Patent No. 3084339, and
493, JP-A-8-306614 and JP-A-11-329938, or Proceedings of the 61st Japan Society of Applied Physics (2000) No.2 p.593 4
It can be carried out by the method described in aX-1.

Next, as shown in FIG. 9 (f), the resist 133 is exposed and developed, and the membrane 1 shown in FIG.
03, a resist 1 corresponding to an LSI mask pattern
34 are formed. According to the mask manufacturing method of the present embodiment, since the resist 134 on the same side as the strut 104 is exposed, alignment is easy as in the first embodiment, and a double-side aligner is not required. FIG. 7 (b)
The margin (skirt 106) provided between the pattern region 105 and the strut 104 shown in FIG.

Next, as shown in FIG.
Dry etching is performed on the silicon layer 114 using the mask 134 as a mask.
Performing As an etching gas, for example, SF₆ And
NF _Three Is used. As a result,
Aperture 107 having a predetermined pattern on membrane 103
Is formed.

According to the mask manufacturing method of the present embodiment, the etching of the silicon layer 114 is performed from the strut side. Therefore, during the etching, the protective layer 11
2 is in contact with the stage of the etching apparatus, and the etched surface is stably supported. This prevents deformation of the membrane mask due to heat generation during etching and the like, and improves pattern processing accuracy.

Next, as shown in FIG. 9H, the resist 134 is removed. Then, as shown in FIG.
The protection layer 112 is removed. When a polysilicon layer is formed as the protective layer 112, the protective layer 112 can be removed by dry etching using, for example, Cl ₂ or SF ₆ or wet etching. Through the above steps,
A stencil mask 131 is formed.

The protective layer 112 may be removed before the mask is used for the EPL. If necessary, the protective layer 112 can be left just before the use of the mask. Therefore, on the premise that the protective layer 112 is removed before use, it is also possible to supply a mask at the stage shown in FIG. 9H as a product.

According to the mask manufacturing method of the present embodiment described above, it is possible to form struts on a wafer in advance before pattern design is completed. As shown in FIG. 8D, by keeping the mask master at the stage where the struts 104 are formed in stock, the TAT for mask manufacturing is reduced. Further, the mask master on which the struts 104 are formed can be distributed as a semi-processed product because the mechanical strength is reinforced by the protective layer 112.

According to the mask manufacturing method of the present embodiment described above, since the resist to which the mask pattern is transferred is formed on the same side as the struts, it is not necessary to perform the alignment in the photolithography process on both surfaces of the wafer. Alignment is facilitated. Thereby, the yield of the mask can be improved.

According to the mask manufacturing method of the present embodiment, when the silicon layer 114 is etched to form the aperture 107, the wafer is supported not by the struts 104 but by the entire surface of the protective layer 112. Therefore, the wafer is stably supported, and breakage of the membrane 103 during etching is prevented. Also, when baking is performed after the application of the resist 133, the wafer is supported not by the struts 104 but by the entire surface of the protective layer 112. Therefore, the temperature distribution in the wafer surface is small, and the dimensional variation of the resist pattern can be reduced.

According to the mask manufacturing method of the present embodiment, it is possible to proceed with the manufacture of the mask in a state where the membrane 103 is protected by the protective layer 112. Therefore, damage to the mask master is prevented, and the yield of the mask is improved. Further, as shown in FIG. 9H, in a state where the aperture 107 is formed in the membrane 103 and the protective layer 112 is left, since the mechanical strength of the mask is high and the mask is not easily damaged, the storage and transportation are performed. The handling of the mask containing is easy.

In the method for manufacturing a semiconductor device according to the present embodiment, a stencil mask is manufactured according to the method for manufacturing a mask according to the above-described embodiment, and the manufactured mask is, for example, LEEPL.
Etc. are used for EPL. According to the method for manufacturing a semiconductor device of the present embodiment, the TAT for manufacturing the mask is reduced, and the yield of the mask is improved, so that the manufacturing cost of the semiconductor device is reduced. Further, since the pattern processing accuracy of the mask is high, a fine pattern can be formed on the wafer with high accuracy in the EPL process.

The embodiments of the mask master, the mask, the method of manufacturing the mask, and the method of manufacturing the semiconductor device of the present invention are not limited to the above description. For example, the above-described method for manufacturing a mask of the present invention may be applied to X-ray lithography masks other than
The present invention can be applied to the manufacture of other masks such as a mask for line lithography, a mask for EUV light, and a mask for charged particle transfer lithography using an ion beam or the like. In addition, various changes can be made without departing from the gist of the present invention.

[0142]

According to the mask master of the present invention, breakage of the mask before using the mask is prevented. According to the mask of the present invention, it is easy to provide a protective layer for improving the mechanical strength of the mask. ADVANTAGE OF THE INVENTION According to the manufacturing method of the mask of this invention, it becomes possible to manufacture a mask to a specific manufacturing process before the end of pattern design, and the efficiency of mask manufacturing can be improved. Further, according to the mask manufacturing method of the present invention, the processing accuracy of the mask pattern is improved. According to the method for manufacturing a semiconductor device of the present invention, mask manufacturing efficiency is improved and mask pattern processing accuracy is improved, so that the manufacturing cost of the lithography process can be reduced and the yield can be improved.

[Brief description of the drawings]

FIG. 1A is a schematic view of a stencil mask manufactured by a mask manufacturing method according to a first embodiment of the present invention, and FIG. 1B is an enlarged view of a part of FIG. FIG.

FIG. 2A is a cross-sectional view of a stencil mask manufactured by the method for manufacturing a mask according to Embodiment 1 of the present invention, and FIGS. 2B to 2D are Embodiment 1 of the present invention. FIG. 6 is a cross-sectional view showing a manufacturing step of the method for manufacturing a mask according to the first embodiment.

FIGS. 3 (e) to 3 (h) are cross-sectional views showing manufacturing steps of a method for manufacturing a mask according to the first embodiment of the present invention, and show steps subsequent to FIG. 2 (d).

FIG. 4A is a schematic view of a membrane mask manufactured by a mask manufacturing method according to Embodiment 2 of the present invention, and FIG. 2B is an enlarged view of a part of FIG. 2A. FIG.

FIG. 5A is a sectional view of a membrane mask manufactured by a mask manufacturing method according to a second embodiment of the present invention, and FIGS. 5B to 5D are second embodiments of the present invention. FIG. 6 is a cross-sectional view showing a manufacturing step of the method for manufacturing a mask according to the first embodiment.

6 (e) to 6 (h) are cross-sectional views showing manufacturing steps of a method for manufacturing a mask according to Embodiment 2 of the present invention, and show steps subsequent to FIG. 5 (d).

7A is a schematic view of a stencil mask manufactured by a mask manufacturing method according to a third embodiment of the present invention, and FIG. 7B is an enlarged view of a part of FIG. 7A. FIG.

8A is a cross-sectional view of a stencil mask manufactured by a mask manufacturing method according to Embodiment 3 of the present invention, and FIGS. 8B to 8D are Embodiment 3 of the present invention. FIG. 6 is a cross-sectional view showing a manufacturing step of the method for manufacturing a mask according to the first embodiment.

9 (e) to 9 (h) are cross-sectional views showing a manufacturing process of a method for manufacturing a mask according to Embodiment 3 of the present invention, and show a process following FIG. 8 (d).

FIG. 10A is a schematic view of a stencil mask manufactured by a conventional mask manufacturing method, and FIG.
FIG. 10B is a partial cross-sectional view of FIG.

11 (a) to 11 (d) are cross-sectional views showing steps of manufacturing the stencil mask shown in FIG.

FIG. 12A is a schematic view of a membrane mask manufactured by a conventional mask manufacturing method, and FIG.
FIG. 12B is a partial cross-sectional view of FIG.

13 (a) to 13 (d) are cross-sectional views showing steps of manufacturing the membrane mask shown in FIG.

FIG. 14A is a schematic view of a stencil mask manufactured by a conventional mask manufacturing method, and FIG.
FIG. 14B is a partial cross-sectional view of FIG.

15 (a) to 15 (d) are cross-sectional views showing steps of manufacturing the stencil mask shown in FIG.

[Explanation of symbols]

101, 131, 201, 231 ... stencil mask,
102, 202: silicon wafer, 103, 203, 1
22, 222: membrane, 104, 204: strut, 105: pattern area, 106: skirt, 10
7, 205: aperture, 111, 211: SOI wafer, 112: protective layer, 113, 207: silicon oxide film, 114, 206: silicon layer, 115, 212: back side silicon oxide film, 116 to 118, 125, 12
7, 128, 132 to 134, 213, 214, 226
228, 232 to 234... Resist, 121, 221
... membrane masks, 123, 223 ... silicon nitride films, 124, 224 ... scatterers, 126, 225 ... laminated films.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/302 J

Claims (40)

[Claims] 1. A thin film that locally transmits an electromagnetic wave of a predetermined wavelength irradiated to a first surface side to a second surface side, and a thin film formed on the first surface of the thin film from the thin film. A mask having a removable protective layer, and a thin film supporting portion for supporting the thin film, which is formed on a part of the second surface of the thin film so as not to block the electromagnetic wave transmitted through the thin film. Master. 2. The mask master according to claim 1, wherein the thin film has an aperture through which the electromagnetic wave passes, and blocks the electromagnetic wave in a portion other than the aperture. 3. A mask master according to claim 2, wherein said electromagnetic wave is an electron beam. 4. The mask master according to claim 2, wherein said electromagnetic waves are X-rays. 5. The method according to claim 1, wherein the electromagnetic wave is EUV (extreme ultraviole).
3. The mask master according to claim 2, which is t) light. 6. An electromagnetic wave according to claim 2, wherein said electromagnetic wave is an ion beam.
Master mask described. 7. The mask master according to claim 2, further comprising a first etching stopper layer between the second surface of the thin film and the thin film supporting portion, the first etching stopper layer being capable of lowering an etching rate than the thin film supporting portion. 8. The mask master according to claim 2, further comprising a second etching stopper layer capable of lowering an etching rate than the protective layer, between the protective layer and the first surface of the thin film. 9. The thin film further includes a scatterer that scatters and blocks the electromagnetic wave on the second surface of the portion where the thin film support is not formed, and further includes a scatterer that blocks the electromagnetic wave in a portion other than the scatterer. The mask master according to claim 1, which transmits light. 10. The mask master according to claim 9, wherein the electromagnetic wave is an electron beam. 11. The mask master according to claim 9, wherein said electromagnetic waves are X-rays. 12. The mask master according to claim 9, wherein the electromagnetic wave is EUV light. 13. The mask master according to claim 9, wherein said electromagnetic wave is an ion beam. 14. The mask master according to claim 9, further comprising a first etching stopper layer between the second surface of the thin film and the thin film supporting portion, the first etching stopper layer being capable of lowering the etching rate than the thin film supporting portion. 15. The semiconductor device according to claim 9, further comprising a second etching stopper layer between the protective layer and the first surface of the thin film, the second etching stopper layer being capable of lowering an etching rate than the protective layer.
Master mask described. 16. The thin-film support section includes the second thin-film support section.
2. The mask master according to claim 1, wherein the mask master is formed in a shape having at least one rectangular opening on a surface. 17. The thin-film support section, wherein the second portion of the thin film is provided.
17. The mask master according to claim 16, wherein a plurality of rectangular openings are formed on the surface in a shape arranged in a matrix. 18. A thin film, a protective layer formed on the first surface of the thin film and capable of being removed from the thin film, and formed on a part of the thin film on the second surface. A mask master having a thin film supporting portion for supporting the thin film. 19. The mask master according to claim 18, further comprising a first etching stopper layer between the second surface of the thin film and the thin film supporting portion, the first etching stopper layer being capable of lowering the etching rate than the thin film supporting portion. 20. The semiconductor device according to claim 1, further comprising a second etching stopper layer between the protective layer and the first surface of the thin film, the second etching stopper layer being capable of lowering an etching rate than the protective layer.
8. The mask master according to item 8. 21. An apparatus according to claim 21, further comprising a blocking layer formed of a material for scattering and blocking electromagnetic waves having a predetermined wavelength, formed on a portion of said thin film on which said thin film supporting portion is not formed. 18. The mask master according to item 18. 22. The mask master according to claim 21, further comprising a first etching stopper layer between the second surface of the thin film and the thin film supporting portion, the first etching stopper layer being capable of lowering the etching rate than the thin film supporting portion. 23. A semiconductor device according to claim 2, further comprising a second etching stopper layer between the protective layer and the first surface of the thin film, the second etching stopper layer being capable of lowering an etching rate than the protective layer.
2. Master mask according to 2. 24. The thin-film support portion, wherein the second portion of the thin film is provided.
19. The mask master according to claim 18, wherein the mask master is formed in a shape having at least one rectangular opening on a surface. 25. The thin-film support portion, wherein the second portion of the thin film is provided.
The mask master according to claim 24, wherein a plurality of rectangular openings are formed on the surface in a shape arranged in a matrix. 26. A thin film for locally transmitting an electromagnetic wave of a predetermined wavelength irradiated on the first surface side to the second surface side, and transmitting the electromagnetic wave through a part of the thin film on the second surface. A thin film supporting portion that supports the thin film and is formed so as not to block the electromagnetic wave, and scatters the electromagnetic wave formed in a portion of the thin film where the thin film supporting portion is not formed on the second surface. And a scatterer for blocking. 27. A step of forming a thin film on one surface of a substrate, a step of forming a protective layer on the thin film, removing a part of the substrate from the other surface side of the substrate, A step of locally exposing, a step of providing, on an exposed portion of the thin film, a transmitting portion through which an electromagnetic wave of a predetermined wavelength passes, and a blocking portion through which the electromagnetic wave is blocked; and a step of removing the protective layer. Of manufacturing a mask having the same. 28. The step of providing the transmitting portion and the blocking portion includes forming an aperture by removing a part of the exposed portion of the thin film from the substrate side, and using the aperture as the transmitting portion other than the aperture. 28. The method of manufacturing a mask according to claim 27, further comprising a step of setting a portion as the blocking portion. 29. The step of providing the transmitting portion and the blocking portion includes a step of spraying and applying a resist on at least an exposed portion of the thin film, and exposing and developing the resist to transfer a predetermined mask pattern. 29. The method of manufacturing a mask according to claim 28, further comprising: performing a step of: etching the thin film using the resist as a mask to form the aperture; and removing the resist. 30. The step of spraying the resist includes a step of moving at least one of the nozzle and the substrate while spraying the resist from a nozzle, and scanning the exposed portion with the nozzle.
10. The method for manufacturing a mask according to 9. 31. The step of providing the transmitting portion and the blocking portion includes: forming a blocking layer made of a material that scatters and blocks the electromagnetic wave on an exposed portion of the thin film; 28. The method of manufacturing a mask according to claim 27, further comprising the step of removing the portion where the blocking layer has been removed and setting the portion where the blocking layer has been removed as a transmitting portion and setting the remaining portion of the blocking layer as the blocking portion. 32. The step of providing the transmission portion and the blocking portion includes spraying and applying a resist on the surface of the blocking layer, exposing and developing the resist, and transferring a predetermined mask pattern. 32. The method of manufacturing a mask according to claim 31, comprising: a step of etching the barrier layer using the resist as a mask; and removing the resist. 33. The step of spraying the resist includes a step of moving at least one of the nozzle and the substrate while spraying the resist from a nozzle, and scanning the exposed portion with the nozzle.
3. The method for manufacturing a mask according to 2. 34. The method according to claim 34, further comprising, before forming the thin film on one surface of the substrate, forming a first etching stopper layer capable of lowering an etching rate on the one surface than the substrate. 28. The method of manufacturing a mask according to claim 27, wherein the step of forming a thin film includes the step of forming the thin film on the substrate via the first etching stopper layer. 35. The method according to claim 35, further comprising, before forming the protective layer on the thin film, a step of forming a second etching stopper layer on the thin film, the etching rate being lower than that of the protective layer. 28. The method of manufacturing a mask according to claim 27, wherein the forming step includes a step of forming the protective layer on the thin film via the second etching stopper layer. 36. The method according to claim 27, wherein the step of removing a part of the substrate includes dry etching of the substrate. 37. The method according to claim 27, wherein the step of removing a part of the substrate includes wet etching of the substrate. 38. The method according to claim 27, wherein the step of removing a part of the substrate includes exposing the thin film in at least one rectangular shape. 39. The method according to claim 38, wherein the step of removing a part of the substrate includes exposing the thin film in a plurality of rectangular shapes arranged in a matrix. 40. A semiconductor device comprising: a step of forming a lithography mask having a predetermined mask pattern; and a step of irradiating an electromagnetic wave onto a substrate through the lithography mask and transferring the mask pattern to the substrate. Wherein the step of forming the lithography mask includes: forming a thin film on one surface of a mask base; forming a protective layer on the thin film; and the other of the mask base Removing a portion of the mask base material from the surface side of the thin film and locally exposing the thin film; and, in the exposed portion of the thin film, a transmitting portion through which an electromagnetic wave having a predetermined wavelength is transmitted; A method of manufacturing a semiconductor device, the method including: providing a blocking section; and removing the protective layer.