JP2002230969A - Semiconductor memory device - Google Patents

Abstract

(57) [Problem] To provide a semiconductor memory device capable of obtaining excellent charge retention characteristics by reducing a leakage current of a storage node. A memory cell is constituted by a transistor and a stacked capacitor. The gate electrode 5 of the transistor is patterned as a word line continuous in one direction. The upper electrode 23 of the capacitor is patterned as a plate line parallel to the word line. The plate line is driven by a drive voltage having the same polarity as the word line and lower than the word line in synchronization with the corresponding word line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device (DRAM) using memory cells each formed of one transistor and one capacitor.

[0002]

2. Description of the Related Art A DRAM is being miniaturized and highly integrated while securing a capacitor capacity by adopting a trench type capacitor or a stacked type capacitor structure. When the DRAM cell is miniaturized, it is important to suppress the short channel effect of the transistor. For that purpose, the impurity concentration of the p-type well in the memory cell array region is increased.

[0003]

However, when the impurity concentration of the p-type well is increased to suppress the short channel effect,
Junction leaks of storage nodes cannot be ignored, and how to maintain data retention characteristics is an important issue. At present, in a DRAM with the highest degree of integration, the storage node has about 1.8 when holding "1" data.
V. The plate electrode of the capacitor is provided commonly to all the memory cells, and a fixed potential of, for example, about 0.9 V is applied thereto. On the other hand, in order to keep the transistor at a predetermined threshold voltage, VBB = −
A negative substrate bias of about 0.5V is applied. At this time, pn between the n-type diffusion layer and the p-type well of the transistor to which the storage node is connected in the “1” data holding state
A reverse bias of about 2.3 V is applied to the junction, and the junction leakage becomes a value that cannot be ignored. The reason why a fixed potential of 0.9 V is given to the plate electrode of the capacitor is as follows.
0 V potential of the storage node in the case of “0” data retention
This is because the electric field applied to the capacitor insulating film can be minimized by using an intermediate potential of 1.8 V of the storage node in the case of holding “1” data.

The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor memory device capable of reducing leakage current of a storage node and obtaining excellent charge retention characteristics. .

[0005]

In a semiconductor memory device according to the present invention, a plurality of memory cells, which are constituted by transistors and capacitors and are arranged in a matrix, are commonly connected to the gates of the transistors of the memory cells arranged in the first direction. A plurality of word lines, a plurality of bit lines to which a first terminal of a capacitor of a memory cell arranged in a second direction is connected via a transistor, and a plurality of bit lines arranged in parallel with the respective word lines. A plurality of plate lines connected in common to the second terminals of the capacitors of the memory cells arranged in the first direction and driven in synchronization with the word lines.

In a conventional DRAM, a first terminal connected to a transistor of a capacitor is used as a storage node, and a second terminal is commonly provided as a plate electrode to all memory cells, to which a fixed potential is applied. Was. On the other hand, in the present invention, the conventional plate electrode is formed separately as a plate line parallel to each word line, and this plate line is driven in synchronization with the corresponding word line. Specifically, when the selected word line is activated, a drive voltage higher than that in the data holding state is applied to the corresponding plate line. As a result, the "H" level of the storage node in the data holding state can be made lower than before.
Junction leakage can be reduced.

In the present invention, preferably, the drive voltage when the word line of the plate line is activated is the "H" level of the first terminal at which the word line is activated and finally stabilized. The plate line is set to a second level lower than the first level while the word line is set to a first level substantially in the middle of the L ″ level and the word line is in an inactive data holding state. This makes it possible to reduce the leakage of the storage node during data retention while minimizing the electric field applied to the capacitor when the word line is activated.

In the present invention, preferably, the capacitor is a stack type capacitor formed on an interlayer insulating film covering a transistor formed on a semiconductor substrate, and an upper electrode of which is patterned as the plate line. I do. Further, in the present invention, together with a word line driving circuit provided for each word line and driving a word line selected by an address, a plate line selected by the same address as the corresponding word line is provided for each plate line. A driving plate line driving circuit is provided.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a layout of a DRAM cell array according to an embodiment of the present invention.
Is a sectional view taken along the line AA ′. DRAM cells have a stacked capacitor structure.

A p-type well 2 is formed in a DRAM cell array region of a silicon substrate 1. This silicon substrate 1 is provided with STI (Shallow Trench Iso
1), an element isolation insulating film 3 is formed, whereby a rectangular element formation region 4 is formed as shown by a broken line in FIG. Two transistors Q are formed in each element formation region, and a capacitor C connected to these transistors Q is formed as a stacked type stacked on top of the transistor Q.

The gate electrode 5 of the transistor Q is made of a laminated film of a polycrystalline silicon film and a WSi film. The gate electrode 5 is continuously patterned in the y-direction in FIG. 1 to be a word line WL. Source / drain diffusion layer 6
One of the transistors 6 a is shared by two transistors Q in one element formation region 4. The periphery of gate electrode 5 is covered with silicon nitride film 7. The surface on which the transistor Q is formed is planarized by the TEOS oxide film 9 so as to fill the space between the gate electrodes.

In the TEOS oxide film 9, a contact hole is formed in the shared diffusion layer 6a of the two transistors Q, and the strap electrode 8 is buried therein. The strap electrode 8 is embedded so as to be taken out of the element isolation region, as shown by oblique lines in FIG. 1, and bit lines (BL) 10 are continuously arranged in the x direction so as to be connected to the strap electrode 8. Is established.

A BPSG film 11a and a TEOS oxide film 1 are further formed as interlayer insulating films 11 on the surface on which the bit lines 10 are formed.
1b is formed. In this interlayer insulating film 11, a plug 12 connected to the diffusion layer 6b on the storage node side of the transistor Q is embedded. The plug 12 is, specifically,
A lower plug embedded simultaneously with the strap electrode 8,
It is formed by two-stage embedding of an upper flag which is formed by embedding a contact hole in the interlayer insulating film 11 deposited thereon. The periphery of the plug 12 is surrounded by the silicon nitride film 31.

The stack type capacitor C has an interlayer insulating film 1
1 is formed. That is, an oxide film 13 is further deposited on the interlayer insulating film 11 with the silicon nitride film 32 interposed therebetween, and a recess for exposing the plug 12 is formed in the region of the oxide film 13 corresponding to each capacitor. The lower electrode (first terminal) 21 connected to the plug 12 in the concave portion, the capacitor insulating film 2
2 and an upper electrode (second terminal) 23 are sequentially formed to form a capacitor C.

The upper electrode 23 of the capacitor C is patterned as a plate line PL parallel to the word line WL so as to be continuous in the y direction, as shown by a dashed line in FIG. That is, for a plurality of memory cells sharing a certain word line WL, a plate line PL is arranged in pairs with the corresponding word line WL so that the second terminals of the capacitors are commonly connected.

By configuring the DRAM cell array as described above,
In this embodiment, the plate line PL is driven in synchronization with the word line WL. The driving method will be described below. FIG. 3 shows an equivalent circuit including a drive circuit for one word line WL of the DRAM cell array and the corresponding plate line PL. The row address RA is level-converted to the boosted potential VPP by the level conversion circuit 301 and supplied to the word line drive circuit 302. In the word line drive circuit 302, the output of the level conversion circuit 302 is "L".
And a transfer driver including a PMOS transistor QP1 and an NMOS transistor QN1 for transferring the word line selection signal WDRV to the word line WL at the time of. The NMOS transistor QN2 is for resetting when the word line WL is in a non-selected state.

As in the case of the word line WL, the level conversion circuit 303 in which the same row address RA is input to the plate line PL.
And a plate line drive circuit 30 controlled by its output
4 are provided. These configurations are basically the same as those on the word line side, but the level conversion circuit 303 is supplied with an internal potential VPL lower than the boosted potential VPP on the word line side, and the plate line selection signal PDRV also receives the word line An internal potential lower than selection signal WDRV is used. A positive fixed potential Va slightly higher than VSS is applied to a reference potential end of the plate line driving circuit 304. Note that a substrate bias circuit 305 is provided to apply a negative substrate bias VBB to the p-type well in the cell array region.

More specifically, word lines WL and plate lines PL
Will be described with reference to FIG. here,
DRA in which the external power supply voltage is 2.5 V and the internal power supply voltage used in the cell array area is 1.8 V
In the case of M, the operation waveform at the time of the read operation is shown including the potential change of the storage node and the bit line BL. However, the bit line precharge uses a VCC / 2 precharge method.

Word line WL is at 0 V in an inactive state (data holding state), and is supplied with a select signal voltage WDRV boosted at the time of selection (at the time of active). On the other hand, prior to time t1 when the word line WL is activated, the corresponding plate line PL changes from Va = 0.5V to the intermediate voltage PDRV = 0.9V of the internal power supply voltage 1.8V at time t0.
After the word line WL is deactivated at time t3, the voltage is lowered again to 0.5V at time t4.

As a result of such capacitive coupling by driving the plate line PL in synchronization with the word line WL, the "H" level ("1" data) of the storage node becomes 1.4 V in the data holding state. On the other hand, the “L” level (data “0”) becomes −0.4 V in the data holding state.
Explaining in time, the plate line PL is raised from 0.5V to 0.9V at time t0 before the word line is activated. As a result, the potential of the storage node rises due to the capacitance coupling. Then, when the word line WL is activated at time t1, the bit line BL and the storage node are connected, and the potential of the storage node changes simultaneously with the bit line BL in accordance with the stored data "1" and "0",
Further, when the sense amplifier is activated at time t2, the storage node and the bit line BL are finally stabilized at 1.8V for "1" data and 0V for "0" data. That is, the read data is restored by the sense amplifier.

Thereafter, at time t3, the word line WL becomes inactive, and at time t4, when the plate line PL is lowered to 0.5 V, the "H" and "L" levels of the storage node are respectively changed by capacitive coupling. 1.4V,-
It will be reduced to 0.4V.

As described above, in this embodiment,
By driving the plate line PL in synchronization with the word line WL to have the same polarity as the word line WL, the “H” level of the storage node in the data holding state can be compared with the conventional case where the plate electrode is set to a fixed potential. And can be lowered. This makes it possible to reduce the leakage current of the storage node in a miniaturized DRAM. in this case,
The “L” level of the storage node is also lowered, but the level may be such that the junction of the storage node does not become forward biased. Specifically, in the above example, VBB = −0.
Since a substrate bias of 5 V is applied, the pn junction does not become forward biased.

In this embodiment, since a stacked capacitor is used, forming a plate line parallel to a word line is simple in terms of process and does not cause a penalty in area. . Further, the plate line can be formed of a metal film to be a low resistance wiring.

In the above embodiment, a DRAM having a stacked capacitor has been described, but the present invention is also applicable in principle to a DRAM having a trench capacitor. FIG. 5 shows the cell structure in that case. The capacitor C is formed by forming a trench 41 in a silicon substrate 40, forming a capacitor insulating film 42 on a side wall of the trench 41, and embedding polycrystalline silicon 43. An n-type diffusion layer 44 serving as a plate electrode is formed around the capacitor, and an n ⁺ -type diffusion layer 45 serving as a plate line PL is formed at the bottom of the trench. That is, the n ⁺ -type diffusion layer 45 becomes a plate line PL common to a plurality of memory cells continuously in a direction orthogonal to the paper surface.

The transistor Q has a gate electrode 51 and a source / drain diffusion layer 52 formed in a self-aligned manner with the gate electrode 51.
a, 52b. The gate electrode 51 is formed continuously in a direction orthogonal to the plane of the drawing and becomes a word line WL. One diffusion layer 52b of the transistor is connected to embedded polysilicon 43 of capacitor C as a storage node. Specifically, in the example shown in FIG.
The case where the diffusion layer 52b and the polycrystalline silicon 43 are connected by diffusion of impurities from the polycrystalline silicon 43 through the side surface opening of the collar insulating film 46 formed on the upper part of FIG.

The transistor Q is covered with an interlayer insulating film 53. A plug 55 connected to the other diffusion layer 52a of the transistor Q is embedded in the interlayer insulating film 53,
A bit line 54 is formed thereon.

That is, a DRAM having a trench capacitor
Also, the word line WL shared by a plurality of memory cells
Corresponding to the above, n ⁺ type diffusion layer 45
Is provided. With such a configuration, by driving the plate line in synchronization with the word line as in the previous embodiment, it becomes possible to reduce the leakage current of the storage node.

[0028]

As described above, according to the present invention, the conventional plate electrode is formed separately as a plate line parallel to each word line, and this plate line is driven in synchronization with the corresponding word line. . Specifically, when the selected word line is activated, a drive voltage higher than that in the data holding state is applied to the corresponding plate line. As a result, the "H" level of the storage node in the data holding state can be made lower than before, and junction leakage can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a layout of a DRAM cell array according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along line A-A 'of FIG.

FIG. 3 is a diagram showing an equivalent circuit of a main part of the DRAM of the embodiment.

FIG. 4 is an operation waveform diagram of the DRAM of the embodiment.

FIG. 5 is a cross-sectional view of a main part of a DRAM according to another embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... P type well, 3 ... Element isolation insulating film, 4 ... Element formation region, 5 ... Gate electrode (word line W
L), 6a, 6b: source and drain diffusion layers, 7: silicon nitride film, 8: strap electrode, 9: TEOS oxide film, 10: bit line (BL), 11: interlayer insulating film, 12
.. Plug, 13 oxide film, 21 lower electrode, 22 capacitor insulating film, 23 upper electrode (plate line PL).

Continued on the front page F term (reference) 5F083 AD17 AD24 GA06 JA35 LA12 LA16 LA19 MA06 MA17 NA01 NA08 5M024 AA06 AA40 BB02 BB08 BB30 BB35 BB36 CC13 CC23 HH01 HH11 LL04 LL20 PP03 PP05 PP07 PP10

Claims (5)

[Claims] A plurality of memory cells which are constituted by transistors and capacitors and are arranged in a matrix; a plurality of word lines to which gates of transistors of the memory cells arranged in a first direction are commonly connected; A plurality of bit lines to which the first terminals of the memory cell capacitors arranged in a row are connected via a transistor; and the second terminals of the memory cell capacitors arranged in parallel with each of the word lines and arranged in the first direction. And a plurality of plate lines, the terminals of which are connected in common and driven in synchronization with the word lines. 2. The semiconductor memory device according to claim 1, wherein each of the plate lines is driven in synchronization with a corresponding word line, to have the same polarity as the word line and at a lower voltage than the word line. 3. The drive voltage when the word line of the plate line is activated is “H” level and “L” of the first terminal at which the word line is activated and finally stabilized. The plate line is held at a second level lower than the first level while the word line is set to a first level which is substantially intermediate between the first level and the inactive data holding state. Semiconductor memory device. 4. The capacitor is a stacked capacitor formed on an interlayer insulating film covering a transistor formed on a semiconductor substrate, and has an upper electrode patterned as the plate line. The semiconductor memory device according to claim 1. 5. A word line driving circuit provided for each word line and driving a word line selected by an address, and provided for each plate line and selected by the same address as a corresponding word line. 2. The semiconductor memory device according to claim 1, further comprising a plate line driving circuit for driving a plate line.