JP2002229930A - DMA control method and media processing device - Google Patents

Abstract

(57) [PROBLEMS] To provide a DMA control method capable of executing DMA in an appropriate order and reducing the amount of input / output buffer required when processing streaming data. In a media processing apparatus 101 in which a plurality of tasks 1, 2, ..., P share a DMA controller 115, each of tasks 1, 2, ..., P sends a DMA request to a DMA controller 115 to a DMA processing unit 114. When issuing the request, a request is issued by adding a parameter relating to the DMA transfer and a parameter indicating the priority. When processing a DMA request, when there are a plurality of DMA requests to be processed, the DMA processing unit 114 selects the DMA request to be processed based on a parameter indicating the priority added to each DMA request. I do.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a DMA control method and a media processing device for efficiently performing DMA transfer of stream data in a multitask system.

[0002]

2. Description of the Related Art DMA is a technique for performing data transfer and arithmetic processing by a CPU in parallel. General DM
In the A transfer execution, (1) the CPU calculates the source and destination addresses and the transfer size, and (2) the CPU
A transfer request is issued to the A controller, and (3) (3-
1) The CPU performs a task switch to execute processing of another task, (3-2) the DMA controller executes data transfer, (4) the DMA controller generates an interrupt at the end of the DMA transfer, and (5) the CPU executes A procedure for receiving a DMA end interrupt and restoring the task that started the DMA is executed.

In a general multi-task OS, the OS manages task execution priorities, and determines the order in which tasks are started according to the priorities. Therefore, the DMA requests started by each task are started at a frequency according to the task priority, and the DMA transfer is executed in the order in which the DMA requests are generated.

FIG. 5 shows a media processing apparatus employing a conventional DMA control method. The media processing device 301 is connected to the memory 302. Media processing device 301
, P tasks, that is, task 1 (30 in the figure)
3), task 2 (318 in the figure),..., Task P (319 in the figure) are executed. Task 1 has N DMAs
There are requests 1-1 to 1-N, and task 2 has M DMAs.
There are requests 2-1 to 2-M, and task P has L DMAs.
There are requests P-1 to PL.

[0005] Task 1 is started and a DMA request 1-1 is issued.
When (304 in the figure) is executed, DMA request information of transfer source address, transfer destination address, and transfer size (305)
Is output to the DMA control unit 314 in the operating system 313 to perform a task switch.

Next, when the OS determines that the task 2 (318 in the figure) is to be started, the processing of the task 2 is performed, and the DMA request 2-1 (307 in the figure) in the middle of the processing is executed. And the DMA request information (308) of the transfer source address, the transfer destination address, and the transfer size are output to the DMA control unit 314 in the operating system 313, and task switching is performed.

Similarly, when a task P (319 in the figure) is activated and a DMA request PL (330 in the figure) is executed, a transfer source address, a transfer destination address, and a transfer size D are obtained.
The MA request information (311) is output to the DMA control unit 314 in the operating system 313 to perform a task switch.

When the DMA transfer that has been operating during the processing of the above-described task 1, task 2, and task P ends, the DMA control unit 314 issues the first DMA request among the stored unprocessed DMA requests. Request 1-1 is selected, and DM
Parameters such as a transfer source address, a transfer destination address, and a transfer size are set in the A controller 315, and the DMA controller 315 is started. When the DMA request 1-1 is a write request to the memory, the write address is output to the address bus 316, and the data read from the task 1 is transferred to the data bus 306, the DMA controller 315, and the data bus 3
17 and is written to the memory 302. When the DMA request 1-1 is a read request from the memory, the read address is output to the address bus 316, and the data read from the memory 302 is written to the task 1 via the data bus 317, the DMA controller 315, and the data bus 306. It is.

When the processing of the DMA request 1-1 is completed, the DMA requests remaining in the DMA control unit 314 are the DMA request 2-1 and the DMA request PL.

The DMA control unit 314 selects the DMA request 2-1 that has issued the request first among the unprocessed DMA requests, and sets parameters such as a transfer source address, a transfer destination address, and a transfer size to the DMA controller 315. And DM
The A controller 315 is started. When the DMA request 2-1 is a write request to the memory, the write address is output to the address bus 316, and the data read from the task 2 is transferred to the memory 302 via the data bus 312, the DMA controller 315, and the data bus 317. Is written to. When the DMA request 2-1 is a read request from the memory,
The read address is output to the address bus 316, and the data read from the memory 302 is transmitted to the data bus
The data is written to task 2 via A controller 315 and data bus 312.

When the task 1 is started during the execution of the DMA request 2-1 and the DMA request 1-N (320 in the figure) is executed, the DMA request information (source address, destination address, transfer size) 321) is output to the DMA control unit 314 in the operating system 313.

When the processing of the DMA request 2-1 is completed, the DMA requests remaining in the DMA control unit 314 are a DMA request 1-N and a DMA request PL.

The DMA control unit 314 selects the DMA request PL which issued the request first among the unprocessed DMA requests, and sets parameters such as a transfer source address, a transfer destination address, and a transfer size to the DMA controller 315. And DM
The A controller 315 is started, and the same operation is performed thereafter.

[0014]

SUMMARY OF THE INVENTION A DMA as described above
When processing stream data such as image or audio data by using the control method, the processed data is temporarily stored in a low-cost large-capacity memory (DRAM or the like), and input / output with an external device is performed. Sometimes I / O buffer (F
IFO). In order not to interrupt data input / output with the outside, it is necessary to estimate in advance the amount of data input / output during the execution of another task to secure a sufficient buffer amount.

However, if the amount of data input / output during execution of another task is estimated in advance to secure a sufficient buffer amount, there is a problem that the buffer amount increases.

The present invention has been made in consideration of the above circumstances, and has been made in consideration of the above circumstances, and performs a DMA in an appropriate order to reduce a required amount of input / output buffers when processing streaming data. It is an object to provide a processing device.

[0017]

SUMMARY OF THE INVENTION The present invention is a DMA control method in a media processing apparatus in which a plurality of tasks share a DMA controller, wherein each of the tasks issues a DMA request to the DMA controller. A request is issued by adding a parameter relating to DMA transfer and a parameter indicating priority, and when processing a DMA request to the DMA controller, if there are a plurality of DMA requests to be processed, the DMA request is added to each DMA request. Based on the parameter indicating the priority,
A DMA request to be processed is selected.

Preferably, among the DMA requests, the one to be processed with priority is determined as a special DMA request (for example, a DMA request for input processing or output processing of stream data), and the DMA request issued by the task is In the case of a special DMA request, a DMA request may be issued with a parameter indicating a higher priority than other DMA requests.

Also, the present invention provides a DMA processing method for a media processing apparatus in which a plurality of tasks share a DMA controller.
In the control method, when each of the tasks issues a DMA request to the DMA controller, it is possible to identify parameters relating to the DMA transfer and whether or not the DMA request is a special DMA request to be preferentially processed. In processing a DMA request to the DMA controller, when there are a plurality of DMA requests to be processed, if a special DMA request exists, a special DMA request is issued. Priority, and if no special DMA request exists, a special DM
It is characterized by processing a DMA request other than the A request.

It should be noted that the present invention relating to the apparatus is also realized as an invention relating to a method, and the present invention relating to a method is also realized as an invention relating to an apparatus. Further, the present invention according to an apparatus or a method has a function of causing a computer to execute a procedure corresponding to the present invention (or causing a computer to function as means corresponding to the present invention, or a computer having a function corresponding to the present invention). The present invention is also realized as a program (for example, one function of an operating system) for realizing the present invention, and is also realized as a computer-readable recording medium storing the program.

According to the present invention, when a task issues a DMA request to the DMA controller, a parameter indicating a priority is added to a parameter of the DMA transfer, and a use order of the DMA controller is determined based on the parameter indicating the priority.

Further, according to the present invention, when a task issues a DMA request to a DMA controller, a high-priority parameter is added to the DMA request for stream data input / output processing to issue a DMA request, and the stream data is input. A DMA request is issued by adding a general priority parameter to a DMA request other than the output process,
The use order of the DMA controller is determined based on these parameters.

According to the present invention, when a plurality of DMA requests occur in a multitask system, the priority of DMA execution can be executed not by the priority determined by the operating system but by the priority intended by the user. .

Further, according to the present invention, the priority of DMA transfer for performing input / output processing of stream data can be increased by an instruction from a user.
Compared with a media processing apparatus that has performed DMA processing in the order of request generation, the amount of buffer memory can be reduced, and the circuit scale can be reduced.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration example of a media processing apparatus according to the first embodiment of the present invention.

The media processing apparatus 101 is provided with a DMA controller in addition to the CPU similarly to the conventional one, and has a function for controlling execution and switching of a task and a function for performing DMA control (here, a function is provided). , These functions are realized by the operating system). Further, the media processing device 101 is connected to the memory 102.

In the media processing apparatus 101, P tasks 1 (103 in the figure), tasks 2 (118 in the figure),
.., A task P (119 in the figure) is executed.

Task 1 includes N DMA requests 1-1 to 1
−N, and task 2 has M DMA requests 2-1 to 2
-M. Similarly, the task P has L DMA requests P-1 to P-L.

First, it is assumed that task 1 is started.
When the DMA request 1-1 (104 in the figure) is executed in the task 1, the DMA request information (105) including the source address, the destination address, the transfer size, and the priority is transferred to the DMA control in the operating system 113. It is output to the unit 114. Here, a task switch is performed.

Next, task 2 is started, and DMA request 2
When -1 (107 in the figure) is executed, the DMA request information (108) including the source address, the destination address, the transfer size, and the priority is transmitted to the operating system 113.
Is output to the DMA control unit 114 in the. Where
A task switch is performed.

Similarly, when the task P is activated and the DMA request PL (110 in the figure) is executed, the DMA including the transfer source address, the transfer destination address, the transfer size, and the priority is executed.
The request information (111) is stored in the operating system 11
3 is output to the DMA control unit 114. Here, a task switch is further performed.

Here, the magnitude relationship between the priorities of the DMA requests is as follows: DMA request 1-1> DMA request PL> DMA
Request 2-1.

When the DMA transfer operating during the processing of task 1, task 2, and task P is completed, the DMA controller 114 sets the highest priority DMA among the stored unprocessed DMA requests. Request 1-1 is selected and DMA
Parameters such as a transfer source address, a transfer destination address, and a transfer size are set in the controller 115, and the DMA controller 115 is started.

When the DMA request 1-1 is a write request to the memory, the write address is output to the address bus 116,
Data read from task 1 is transferred to data bus 106
The data is written to the memory 102 via the DMA controller 115 and the data bus 117. When the DMA request 1-1 is a read request from the memory, a read address is output to the address bus 116, and the data read from the memory 102 is written to the task 1 via the data bus 117, the DMA controller 115, and the data bus 106. It is.

Subsequently, at the time when the processing of the DMA request 1-1 has been completed, the priority order of the DMA requests remaining in the DMA control unit 114 is as follows: DMA request PL> DMA request 2-1.

The DMA control unit 114 selects the DMA request PL having the highest priority among the unprocessed DMA requests,
Parameters such as a transfer source address, a transfer destination address, and a transfer size are set in the DMA controller 115, and the DMA controller 115 is activated.

When the DMA request PL is a write request to the memory, the write address is output to the address bus 116,
The data read from task P is stored in data bus 112
The data is written to the memory 102 via the DMA controller 115 and the data bus 117. When the DMA request PL is a read request from the memory, a read address is output to the address bus 116, and the data read from the memory 102 is written to the task P via the data bus 117, the DMA controller 115, and the data bus 112. It is.

Now, the task 1 is started during the execution of the DMA request PL, and the DMA request 1-N (12 in FIG.
0) is executed, the DMA request information (121) including the source address, destination address, transfer size, and priority
To the DMA control unit 114 in the operating system 113.

The priority of DMA request 1-N is DMA request 2
Assuming that the priority is higher than −1, the DMA remaining in the DMA control unit 114 at the time when the processing of the DMA request PL is completed.
Regarding the requests, the priority relationship is as follows: DMA request 1-N> DMA request 2-1.

In this case, the next DMA transfer is executed by the DMA request 1-N having a higher priority.
Parameters such as a transfer source address, a transfer destination address, and a transfer size are set in the controller 115, and the DMA controller 115 is started.

When the DMA request 1-N is a write request to the memory, the write address is output to the address bus 116,
Data read from task 1 is transferred to data bus 106
The data is written to the memory 102 via the DMA controller 115 and the data bus 117. If the DMA request 1 · N is a read request from the memory, a read address is output to the address bus 116, and the data read from the memory 102 is written to the task 1 via the data bus 117, the DMA controller 115, and the data bus 106. It is.

Similarly, when there are a plurality of DMA requests waiting for execution of the DMA transfer, the DMA transfer is started from the DMA request having the higher priority instead of the issued order (or the accepted order). Be executed.

It should be noted that the DM waiting to execute the DMA transfer
A plurality of DMA requests having the same priority among the A requests may be allowed to exist at the same time. In this case, when there are a plurality of DMA requests having the highest priority, the DMA transfer may be executed in accordance with the issued order (or the accepted order).

FIG. 2 shows an example of a procedure for selecting a DMA request by the DMA control unit 114. That is, DMA
When the request can be processed and there is a DMA request to be processed (step S1), if there is one DMA request to be processed (step S2), the DMA request is selected (step S3), and the DMA to be processed is selected. If there are a plurality of requests (step S2), a DMA request having the highest priority is selected (step S4), and a procedure necessary for executing the selected DMA request is performed (step S5). Hereinafter, this is repeated.

The procedure shown in FIG. 2 is an example, and the present invention can be implemented by another procedure.

FIG. 3 shows a configuration example of a media processing apparatus according to the second embodiment of the present invention.

The media processing device 201 has a DMA controller in addition to the CPU as in the conventional one, and has a function for controlling execution and switching of tasks and a function for performing DMA control. , These functions are realized by the operating system). Further, the media processing device 201 is connected to the memory 202.

In the media processing device 201, P tasks 1 (203 in the figure), tasks 2 (218 in the figure),
..., the task P (219 in the figure) is executed.

Task 1 includes N DMA requests 1-1 to 1
−N, and task 2 has M DMA requests 2-1 to 2
-M. Similarly, the task P has L DMA requests P-1 to P-L.

In this case, the task 1 includes an input process of stream data, temporarily buffers an external input (224) in the input memory 222, and
The request is transferred to the memory 202 by a request 1-N (220 in the figure). On the other hand, the task 2 includes the output processing of the stream data, and outputs the output to the outside (225) by the DMA.
It is assumed that data is read from the memory 202 in response to a request 2-1 (207 in the figure) and transferred to the output memory 223.

First, task 1 is started, and DMA request 1
-1 (204 in the figure), the source address, destination address, transfer size, and priority (general DMA
DMA request information (205) including the request priority) is transferred to the DMA control unit 214 in the operating system 213.
To perform a task switch.

Next, task 2 is started, and DMA request 2
When -1 is executed, the DMA request information (208) including the source address, the destination address, the transfer size, and the priority (priority of the output DMA request) is transmitted to the DMA control unit 214 in the operating system 213. Output and perform task switch.

Similarly, when the task P is activated and the DMA request PL (210 in the figure) is executed, the transfer source address, the transfer destination address, the transfer size, and the priority (general DM address)
DMA request information (211) including A request priority)
DMA control unit 21 in operating system 213
4 to perform a task switch.

Here, it is assumed that the relationship between the priorities of the general DMA requests is as follows: DMA request PL> DMA request 1-1.

The priority of a special DMA request (here, the DMA request for input / output processing (input DMA request and output DMA request)) is higher than the maximum priority of general DMA requests. I do.

When the DMA transfer that has been operating during the processing of task 1, task 2, and task P is completed, the DMA control unit 214 searches the stored unprocessed DMA requests. In this specific example, at this point, the unprocessed DM
As the A request, input DMA: none output DMA: DMA request 2-1 general DMA: DMA request PL> DMA request 1
-1.

Here, since there remains an output DMA request having a higher priority than a general DMA,
The A request 2-1 is selected, parameters such as a transfer source address, a transfer destination address, and a transfer size are set in the DMA controller 215, and the DMA controller 215 is activated.
In this case, the read address is output to the address bus 216, and the data read from the memory 202 is
17, DMA controller 215, data bus 209, and is written to output memory 223 managed by task 2.

Subsequently, when the processing of the DMA request 2-1 is completed, the remaining DMA requests in the DMA control unit 214 are: input DMA: none output DMA: none General DMA: DMA request P-L> DMA Request 1
-1.

Here, since only the general DMA remains, the DMA control unit 214 selects the DMA request PL having the highest priority among the unprocessed general DMA requests, and
Parameters such as a transfer source address, a transfer destination address, and a transfer size are set in the MA controller 215, and the DMA controller 215 is started. When the DMA request PL is a write request to the memory, the write address is output to the address bus 216, and the data read from the task P is transferred to the memory 202 via the data bus 212, the DMA controller 215, and the data bus 217. Is written to. DMA
When the request PL is a read request from the memory, the read address is output to the address bus 216, and the data read from the memory 202 is written to the task P via the data bus 217, the DMA controller 215, and the data bus 212. .

Now, when the task 1 is started during the execution of the DMA request PL and the DMA request 1-N is executed, the transfer source address, the transfer destination address, the transfer size, and the priority (input The DMA request information (221) of the DMA request priority) is
Output to MA control section 214.

When the processing of the DMA request P-L is completed, the remaining DMA requests in the DMA control unit 214 are: input DMA: DMA request 1-N output DMA: none General DMA: DMA request 1-1 Become.

When the DMA transfer in operation is completed, the DMA transfer
The control unit 214 searches for an unprocessed DMA request, selects the DMA request 1-N corresponding to the input DMA, and sends the DMA request 215 the transfer source address, the transfer destination address,
The parameters such as the transfer size are set, and the DMA controller 215 is started. In this case, the write address is output to the address bus 216, and the data read from the input memory 222 is written to the memory 202 via the data bus 206, the DMA controller 215, and the data bus 217.

When the processing of the DMA request 1-N is completed, the remaining DMA request in the DMA control unit 214 is: output DMA: none general DMA: DMA request 1-1.

Similarly, when there are a plurality of DMA requests waiting for the execution of the DMA transfer, the DMA transfer is performed not from the order in which they were issued (or the order in which they were received) but from the DMA request having the higher priority. Be executed. At this time, special DMA requests, for example, an input DMA request and an output DMA request have higher priority than the maximum value of the priority of the general DMA request, so that they are handled preferentially. be able to.

Note that a plurality of special DMA requests, for example,
When an input DMA request and an output DMA request occur, it is possible to determine the priority of both by setting the order of the requests and by using the priority parameter in the input / output DMA request. it can.

Also, a plurality of DMAs having the same priority among general DMA requests waiting for execution of DMA transfer
Requests may be allowed to exist simultaneously. In this case, when there are a plurality of DMA requests having the highest priority, the DMA transfer may be executed in accordance with the issued order (or the accepted order).

Further, it is possible to determine the priority of general DMA requests in accordance with the order of generation.

It should be noted that a parameter indicating whether the request is a special DMA request is added instead of the parameter indicating the priority, and based on this parameter, the special DMA request is added to the other general DMA requests. Can also be controlled so as to be processed preferentially.

FIG. 4 shows an example of a procedure for selecting a DMA request by the DMA control unit 214. That is, DMA
If there is a DMA request that can process the request and should be processed (step S11), and there is a special DMA request (for example, an input DMA request or an output DMA request) (step S12), a special DMA request is issued. One of the requests is selected (step S14). If there is no special DMA request (step S12), one of the general DMA requests is selected (step S13), and the selected DMA request is selected. Perform the necessary procedures for execution (step S
15). Hereinafter, this is repeated.

In this embodiment, the procedure shown in FIG. 2 can be used.

Further, it is of course possible to carry out the present invention by another procedure.

In the first and second embodiments, each time the DMA controller receives a new DMA request, the waiting DMA requests are sorted in the order in which they are to be processed, so that the DMA requests can be processed. In such a case, the sorted first DMA request may be selected as the next DMA request to be executed.

The functions of the present embodiment include a program (for example, a program for causing a computer to execute predetermined means (or for causing a computer to function as predetermined means, or for causing a computer to realize predetermined functions)). , A function of an operating system) or a computer-readable recording medium on which the program is recorded.

The configuration illustrated in the embodiment of the present invention is merely an example, and is not intended to exclude other configurations, and a part of the illustrated configuration is replaced with another one or illustrated. Another configuration obtained by omitting a part of the configuration, adding another function or element to the illustrated configuration, or combining them is also possible. Also, another configuration that is logically equivalent to the illustrated configuration,
Another configuration including a portion logically equivalent to the illustrated configuration, another configuration logically equivalent to a main part of the illustrated configuration, and the like are also possible. Further, another configuration that achieves the same or similar purpose as the illustrated configuration, another configuration that achieves the same or similar effect as the illustrated configuration, and the like are also possible. Various variations of the various components exemplified in the embodiments of the present invention can be implemented in appropriate combinations. Embodiments of the present invention relate to various aspects, steps, concepts, or categories, such as an invention as an apparatus or a program, an invention about an internal component of an apparatus or a program, or an invention of a method corresponding thereto. It encompasses and implies the invention. Therefore,
From the contents disclosed in the embodiments of the present invention, the invention can be extracted without being limited to the exemplified configuration.

The present invention is not limited to the above-described embodiments, but can be implemented with various modifications within the technical scope thereof.

[0077]

According to the present invention, the control is performed based on the priority added to the DMA request. Therefore, in a multitask system in which a plurality of DMA requests are generated, the user does not have to determine the order determined by the operating system but the user's intention. It is possible to execute the DMA request according to the given priority.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a media processing apparatus according to an embodiment of the present invention.

FIG. 2 is an exemplary flowchart illustrating an example of a DMA request selection procedure according to the embodiment.

FIG. 3 is an exemplary block diagram showing another configuration example of the media processing apparatus according to the embodiment;

FIG. 4 is a flowchart showing another example of the DMA request selection procedure according to the embodiment;

FIG. 5 is a block diagram of a conventional media processing apparatus.

[Explanation of symbols]

101, 201 ... media processing device 102, 202 ... memory 103, 118, 119, 203, 218, 219 ... task 104, 107, 110, 120, 204, 207, 2
10, 220 ... DMA request 105, 108, 111, 121, 205, 208, 2
11, 221... DMA request information 106, 109, 112, 117, 206, 209, 2
12, 217 data bus 113, 213 operating system 114, 214 DMA controller 115, 215 DMA controller 116, 216 address bus 222 input memory 223 output memory

Claims (9)

[Claims] 1. A DMA control method in a media processing device in which a plurality of tasks share a DMA controller, wherein each of the tasks has a D
When issuing an MA request, a request is issued by adding a parameter relating to DMA transfer and a parameter indicating priority. When processing a DMA request to the DMA controller, if there are a plurality of DMA requests to be processed, A DMA control method, wherein a DMA request to be processed is selected based on a parameter indicating the priority added to each DMA request. 2. The method according to claim 2, wherein the DMA request to be processed with priority is determined as a special DMA request, and the DMA request issued by the task is the special DMA request.
2. The DMA control method according to claim 1, wherein when the request is a request, a DMA request is issued with a parameter indicating higher priority than other DMA requests. 3. The DMA control method according to claim 2, wherein said special DMA request is a DMA request for input processing or output processing of stream data. 4. A DMA control method in a media processing device in which a plurality of tasks share a DMA controller, wherein each of the tasks has a D
When issuing an MA request, the parameters relating to the DMA transfer and the special DMA to be preferentially processed by the DMA request
A request is issued by adding a parameter that enables identification of whether or not the request is a request. When processing a DMA request to the DMA controller, if there are a plurality of DMA requests to be processed, a special DMA request exists. If you do, special DMA
A DMA control method characterized by processing requests preferentially and, if no special DMA request exists, processing a DMA request that is not a special DMA request. 5. When processing the special DMA request, if there are a plurality of special DMA requests, the processing is performed based on the issuing order.
2. The DMA control method according to 1. 6. A media processing device in which a plurality of tasks share a DMA controller, wherein each of the tasks is a DMA request to the DMA controller, to which a parameter relating to a DMA transfer and a parameter indicating a priority are added. Means for accepting, and when there are a plurality of unprocessed received DMA requests, selecting a DMA request to be processed based on the parameter indicating the priority added to each DMA request And a media processing device. 7. A special DMA request which is to be processed preferentially among the DMA requests, wherein the DMA request issued by the task is the special DMA request.
7. The media processing apparatus according to claim 6, wherein if the request is a request, a parameter indicating a higher priority than other DMA requests is added. 8. A media processing apparatus in which a plurality of tasks share a DMA controller, wherein each of the tasks is a DMA request to the DMA controller, and a parameter relating to DMA transfer and the DMA request should be processed preferentially. Means for receiving a DMA request to which a parameter enabling identification of whether or not the DMA request is a special DMA request; Means for selecting a DMA request to be processed based on a parameter which makes it possible to identify whether the request is a special DMA request or not. 9. A program running on a computer in which a plurality of tasks share a DMA controller, wherein each of the tasks is a DMA request to the DMA controller, the parameter indicating a DMA transfer and a parameter indicating a priority. And a function for receiving the DMA request received, and when there are a plurality of received DMA requests that have not been processed, the DMA request should be processed based on the parameter indicating the priority added to each DMA request. A program for causing a computer to implement a function of selecting a DMA request.