JP2002229864A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To save power consumption by eliminating the need of ensuring an extra area in a SRAM as a area for saving data stored in a DRAM to the SRAM during shifting to a power saving mode, in a semiconductor device provided with the DRAM and the SRAM. SOLUTION: When a power saving mode shift command is inputted, a stack saving processing portion 105 saving data stored in the DRAM 103 in a stack area 102b of the SRAM 102. After the data stored in the DRAM 103 is saved in the stack area 102b of the SRAM 102, a power saving mode shift processing portion 104 stops a refresh action of the DRAM 103, and shifts to the power saving mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device having first and second storage means, which stores data stored in the first storage means in a second mode when the mode shifts from the normal mode to the power saving mode. And saves power to the first storage means, thereby reducing power consumption.

[0002]

2. Description of the Related Art The structure and operation of a conventional semiconductor device for reducing the power consumption of the entire semiconductor device will be described. Here, for example, the case where the first storage means is a dynamic random access memory (hereinafter abbreviated as DRAM) and the second storage means is a static random access memory (hereinafter abbreviated as SRAM) is shown in FIG. This will be described with reference to FIG. FIG. 7 is a block diagram of a conventional semiconductor device having a power saving mode.
8 is a flowchart showing the operation of the semiconductor device shown in FIG.

[0003] The semiconductor device shown in FIG.
U601, an SRAM 602 having a variable area 602a and a DRAM data saving variable area 602c,
An AM 603, a power saving mode shift processing unit 604, and a variable area saving processing unit 605 are provided.

A bus 600 includes a CPU 601 and an SRAM.
602 and a common connection connecting the DRAM 603 and the like.

[0005] The CPU 601 includes an SRAM 602 and a DRA.
Data is input from the M603 via the bus 600 to perform various data processing, and the processed data is
Again in the SRAM 602 or the DRAM 603.

The SRAM 602 has a higher operating frequency and lower power consumption than the DRAM 603, but has a small storage capacity due to a high manufacturing cost per unit storage capacity. The variable area 602a of the SRAM 602 is an area for storing global variables and the like when performing various data processing during normal operation. The DRAM data saving variable area 602c of the SRAM 602 stores data stored in the DRAM 603 when the semiconductor device shifts to the power saving mode. When the semiconductor device returns to the normal mode, the data stored in the DRAM data saving variable area 602c is written back to the DRAM 603.

The DRAM 603 has a lower operating frequency and higher power consumption than the SRAM 602, but has a large storage capacity because the manufacturing cost per unit storage capacity is low.

[0008] The power saving mode shift processing unit 604 has a DRA
After the data stored in the M603 is saved in the DRAM data save variable area 602c, the refresh operation of the DRAM 603 is stopped, and the semiconductor device is shifted from the normal mode to the power saving mode.

When a command to shift to the power saving mode is input, the variable area saving processing unit 605 performs processing for saving data stored in the DRAM 603 to the DRAM data saving variable area 602c. When returning from the power saving mode, the DRAM data saving variable area 602c
A process of returning data to the RAM 603 is performed.

Hereinafter, the operation of the conventional semiconductor device configured as described above will be described with reference to FIG.

First, in step ST701, when a command to shift to the power saving mode is input to the semiconductor device, the semiconductor device starts shifting to the power saving mode. And
In step ST702, it is determined whether or not data is stored in the DRAM 603.

In step ST702, DRAM 6
If it is determined that the data stored in the DRAM 603 is stored in the DRAM data saving variable area 602c, it is determined in step ST703 whether or not there is enough free space for saving the data stored in the DRAM 603. If it is determined that there is free space in the DRAM data saving variable area 602c to save, the process proceeds to step S
At T704, the data stored in the DRAM 603 is saved in the DRAM data saving variable area 602c.
Thereafter, in step ST705, the DRAM 603
Is stopped, and the process proceeds to Step ST706. On the other hand, if it is determined that there is not enough free space to save in the DRAM data saving variable area 602c, the process proceeds to step ST706 without saving.

On the other hand, in step ST702, DR
If it is determined that no data is stored in the AM 603, the refresh operation of the DRAM 603 is stopped in step ST705. After stopping the refresh operation, the process proceeds to Step ST706.

In step ST706, processing for shifting to the power saving mode is performed.

During operation in the power saving mode, step ST7
At 07, when a return interrupt signal is input, processing for returning the operation mode of the semiconductor device from the power saving mode to the normal mode is started.

First, in step ST708, DR
It is determined whether the refresh operation of the AM 603 has been stopped. If the refresh operation has been stopped, in step ST709, the refresh operation of the DRAM 603 is restarted, and the process proceeds to step ST710.
On the other hand, when the refresh operation has not been stopped, the process directly proceeds to step ST710.

In step ST710, it is determined whether or not data has been saved in the DRAM data saving variable area 602c. Variable area 60 for saving DRAM data
If the data has been saved to 2c, step ST7
11, the DRAM data saving variable area 602c
Is returned to the DRAM 603, and the process proceeds to step ST712. On the other hand, if the data has not been saved in the DRAM data saving variable area 602c, the process directly proceeds to step ST712.

In step ST712, a process for returning from the power saving mode to the normal mode is performed.

As described above, in the conventional semiconductor device having the power saving mode, when an extra variable area for saving DRAM data is secured in the SRAM and the normal mode is shifted to the power saving mode, the data is stored in the DRAM. Data
Save to the DRAM data save variable area of the RAM,
Stop the refresh operation of the RAM. As a result, the power consumption of the entire semiconductor device has been reduced.

[0020]

However, in the above-described conventional configuration, when shifting from the normal mode to the power saving mode,
As an area for saving data stored in the DRAM to the SRAM, it is necessary to secure an extra storage area for saving the DRAM data in the variable area of the SRAM. For this reason,
There is a problem that the storage capacity increases and the LSI scale increases. In addition, since the SRAM is more expensive than the DRAM, there is a problem that the manufacturing cost is increased.

Accordingly, in view of these problems, the present invention provides:
The data stored in the first storage means such as a DRAM is
An object of the present invention is to provide a semiconductor device capable of reducing power consumption without reserving an extra area in the second storage means when saving to a second storage means such as a RAM.

[0022]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a first storage unit;
A second storage unit having a stack area, a stack evacuation control unit for performing control to save data stored in the first storage unit to the stack area when a power saving mode shift instruction is input, After the data stored in the storage unit is saved in the stack area, the operation of the first storage unit is stopped, and the control unit shifts to the power saving mode.

According to this, by storing the data stored in the first storage means in the stack area of the second storage means, it is necessary to secure an extra storage area for data saving in the second storage means. Disappears. Therefore, power consumption of the semiconductor device as a whole can be reduced without increasing the storage capacity and without increasing the manufacturing cost.

According to another aspect of the present invention, the first storage means is a dynamic random access memory, and the second storage means is:
A static random access memory, wherein the power saving mode transition control means stops the refresh operation of the dynamic random access memory and stops the operation of the dynamic random access memory.

According to a third aspect of the present invention, in the semiconductor device according to the third aspect, the first storage means stores data and tag data corresponding to the data. When input, the tag data is saved in the stack area, and when returning from the power saving mode, data corresponding to the tag data is acquired using the tag data, and the acquired data is restored in the first storage means. It further comprises data restoration control means for performing control.

According to this, if the tag data stored in the first storage means is used, the data corresponding to the tag data can be restored, so that the tag data corresponding to the tag data stored in the first storage means can be restored. Even when the data amount is larger than the capacity of the free area of the stack area, data can be saved. Therefore, the probability of stopping the operation of the first storage unit is increased, and the power consumption of the semiconductor device as a whole can be further reduced without securing an extra variable area for data saving in the second storage unit. .

According to a fourth aspect of the present invention, there is provided a semiconductor device according to the fourth aspect, wherein the first storage means includes a plurality of storage means each of which can be independently stopped. The stack evacuation control means controls the evacuation of data stored in the plurality of storage means to the stack area independently of the plurality of storage means when the power saving mode shift instruction is input. In addition, the power saving mode transition control means stops the operation of the storage means from which the data has been saved among the plurality of storage means.

According to this, the first storage means is constituted by a plurality of storage means each of which can independently stop the operation, and the processing for independently saving is performed, so that the first storage means can be stored for each of the storage means for which data has been saved. Operation can be stopped. For this reason,
The probability of stopping the operation of the first storage means can be increased, and the power consumption of the semiconductor device as a whole can be further reduced without securing an extra variable area for data saving in the second storage means.

According to another aspect of the present invention, there is provided a semiconductor device, comprising: It further comprises a stack information notification control means for performing.

According to this, the function of indicating the free space of the stack area is provided, so that after the data in the first storage means is sorted according to the free state of the stack area,
After the free space in the stack area increases, data can be saved to the stack area. Therefore, the probability of stopping the operation of the first storage unit is increased, and the power consumption of the semiconductor device as a whole can be further reduced without securing an extra variable area for data saving in the second storage unit. .

[0031]

Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, the first storage unit is a DRAM (Dynamic Random Access Memory), and the second storage unit is an SRA
Description will be given as M (static random access memory).

(First Embodiment) A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a configuration of a semiconductor device having a power saving mode according to the first embodiment of the present invention.
3 is a flowchart showing the operation of the semiconductor device of FIG.

The semiconductor device shown in FIG.
U101, variable area 102a and stack area 10
SRAM 102 serving as a second storage unit having 2b
And a DRAM 103 as a first storage unit, a power saving mode transition processing unit (corresponding to the power saving mode transition control unit) 104, and a stack saving processing unit (corresponding to the stack saving control unit) 105. It is.

The bus 100 includes a CPU 101 and an SRAM.
This is a common connection that connects the DRAM 102 and the like.

The CPU 101 has an SRAM 102 or DRA
From M103, data is input via the bus 100 to perform various data processing, and the processed data is stored again in the SRAM 102 or the DRAM 103 via the bus 100.

The SRAM 102 has a higher operating frequency and lower power consumption than the DRAM 103, but has a small storage capacity because of a high manufacturing cost per unit storage capacity. The variable area 102a of the SRAM 102 is an area for storing global variables and the like when performing various data processing during a normal operation. The stack area 102b of the SRAM 102 stores local variables and the like during normal operation. That is, during normal operation, global variables and the like generated when performing various data processing are stored in the variable area 102a.
And not stored in the stack area 102b.
The stack area 102b stores data stored in the DRAM 103 when the semiconductor device shifts to the power saving mode. When the semiconductor device returns to the normal mode, the data stored in the stack area 102b is DRA
It is written back to M103.

The DRAM 103 has a lower operating frequency and higher power consumption than the SRAM 102, but has a large storage capacity because the manufacturing cost per unit storage capacity is low.

The power saving mode shift processing unit 104
After the data stored in M103 is saved to the stack area 102b, the refresh operation of the DRAM 103 is stopped, and the semiconductor device shifts to the power saving mode.

When a command to shift to the power saving mode is input, the stack save processing unit 105 checks the vacant state of the storage capacity of the stack area 102b.
A process is performed to save the data stored in 103 to the stack area 102b. When returning from the power saving mode, a process of returning data from the stack area 102b to the DRAM 103 is performed.

That is, at the time of transition to the power saving mode, data such as global variables are not stored much in the DRAM 103, and since local programs are often executing higher-level functions, local variables are stored in the stack area 102b.
Is not stored much. Therefore, the stack area 1
02b has a lot of unused free space. The present embodiment focuses on such a point, and when shifting to the power saving mode, the data such as global variables stored in the DRAM 103 is stored in the stack area 102b which does not store the global variables during normal operation. Is to be evacuated.

Hereinafter, the operation of the semiconductor device according to the present embodiment configured as described above will be described with reference to FIG.

First, in step ST201, when an instruction to shift to the power saving mode is input to the semiconductor device, the semiconductor device starts shifting to the power saving mode. And
In step ST202, it is determined whether or not data is stored in the DRAM 103.

In step ST202, the DRAM 1
03 is stored in the stack area 102b in step ST203.
It is determined whether there is enough free space to save the data stored in the RAM 103. And the stack area 1
If it is determined that there is enough free space to save the data in the DRAM 102b, the data stored in the DRAM 103 is saved in the stack area 102b in step ST204.
Thereafter, in step ST205, the DRAM 103
Is stopped, and the process proceeds to step ST206. On the other hand, when it is determined that there is not enough free space to save in the stack area 102b, the saving is not performed, and
Proceed to step ST206.

On the other hand, in step ST202, DR
If it is determined that no data is stored in the AM 103, the refresh operation of the DRAM 103 is stopped in step ST205. After stopping the refresh operation, the process proceeds to step ST206.

In step ST206, processing for shifting to the power saving mode is performed.

During operation in the power saving mode, step ST2
At 07, when a return interrupt signal is input, processing for returning the operation mode of the semiconductor device from the power saving mode to the normal mode is started.

First, in step ST208, DR
It is determined whether the refresh operation of the AM 103 has been stopped. When the refresh operation has been stopped, in step ST209, the refresh operation of the DRAM 103 is restarted, and the process proceeds to step ST210.
On the other hand, if the refresh operation has not been stopped, the process directly proceeds to step ST210.

In step ST210, it is determined whether or not data has been saved in the stack area 102b. When data is saved in the stack area 102b, in step ST211 the stack area 10b
The data saved in 2b is returned to the DRAM 103, and the process proceeds to step ST212. On the other hand, if the data is not saved in the stack area 102b, the process proceeds to step S
Proceed to T212.

In step ST212, a process for returning from the power saving mode to the normal mode is performed.

As described above, according to this embodiment, the DR
In the semiconductor device including the AM and the SRAM, when shifting to the power saving mode, data stored in the DRAM is saved in a stack area of the SRAM, and the refresh operation of the DRAM is stopped. As a result, the DR
The power consumption of the entire semiconductor device can be reduced without securing an extra variable area for saving AM data.

(Second Embodiment) A second embodiment of the present invention will be described with reference to FIG.

FIG. 3 is a block diagram of a semiconductor device having a power saving mode according to the second embodiment of the present invention. In FIG. 3, the same components as those in FIG. 1 are denoted by the same reference numerals as those in FIG. Figure 1
3 is different from the semiconductor device shown in FIG. 3 in that a data deletion / restoration processing unit (corresponding to a data restoration control unit) 11
0 is provided.

In this embodiment, a TOC (Track Of Content) corresponding to data read from an optical disk (not shown) as data and data read from the optical disk as tag data indicating the location of the data is provided.
nts: track off (content) information is stored in the DRAM 103. Here, if the TOC information exists, even if the data stored in the DRAM 103 is erased, by reading the corresponding data from the optical disk using the TOC information corresponding to the erased data, the erased data is read. Can be restored.
The present embodiment utilizes such characteristics.

That is, when a power saving mode shift command is input, first, the data deletion / restoration processing unit 110
The TOC information stored in the AM 103 is saved in the stack area 102b of the SRAM 102. Next, if there is still free space in the stack area 102b even after all the TOC information has been saved, the stack save processing unit 105
Saves data stored in the DRAM 103 as much as possible. Data that cannot be backed up is deleted /
It is deleted by the restoration processing unit 110.

When returning from the power saving mode, the stack evacuation processing unit 105 sets the stack area 102
b is returned to the DRAM 103, and the data deletion / restoration processing unit 110
Using the TOC information saved in 02b, the corresponding data is read from the optical disk, stored in the DRAM 103, and the deleted data is restored.

As described above, according to the present embodiment, the DR
In a semiconductor device having AM and SRAM, DR
When shifting to the power saving mode with data and tag data stored in the AM, the tag data is saved to the stack area of the SRAM, and the data is deleted. Then, the deleted data can be restored by using the tag data. Therefore, even if the amount of data stored in the DRAM is larger than the free space in the stack area of the SRAM, the refresh operation of the DRAM can be stopped by saving only the tag data and deleting the data. Thereby, DR
The AM refresh operation can be stopped with a higher probability, and the power consumption of the entire semiconductor device can be further reduced without securing an extra variable area for saving DRAM data in the SRAM.

In this embodiment, TOC information corresponding to all data stored in the DRAM is stored in the DRAM.
However, even when the TOC information corresponding to a part of the data stored in the DRAM is stored in the DRAM, the present invention can be implemented similarly to the present embodiment.

In this embodiment, the data is restored using the TOC information as the tag data. However, if the corresponding data can be restored by any additional information, the additional information is used instead of the TOC information. It can also be implemented in the same manner as this embodiment by using.

(Third Embodiment) A third embodiment of the present invention will be described with reference to FIG.

FIG. 4 is a block diagram of a semiconductor device having a power saving mode according to the third embodiment of the present invention. In FIG. 4, the same reference numerals as in FIG. 1 denote the same components as in FIG. 1, and a detailed description thereof will be omitted. Figure 1
The difference is that in the semiconductor device shown in FIG.
The RAM 103 includes a plurality of DRAMs 103a to DRAM10.
3d, the refresh operation can be performed independently of each other, and the stack
The point is that the operation of retracting to the stack area 102b is performed independently for each of 105a to 105d.

In the present embodiment, when shifting to the power saving mode, the stack save processing unit 105
5a, the stored data is sequentially read out, and the SRA
The evacuation to the stack area 102b of M102 is started. Then, when there is no more free space in the stack area 102b, the evacuation operation to the stack area 102b is stopped.
For example, it is assumed that data stored in the DRAMs 103a and 103b is saved in the stack area 102b of the SRAM 102, and data stored in the DRAMs 103c and 103d is not saved in the stack area 102b. In this case, the refresh operation of the DRAMs 103a and 103b is stopped, the refresh operation of the DRAMs 103c and 103d is not stopped, and the data holding state is maintained.

As described above, according to the present embodiment, the DR
In a semiconductor device including an AM and an SRAM, when shifting to a power saving mode in a state where data is stored in a plurality of DRAMs, data is saved for each DRAM,
The refresh operation is stopped for each saved DRAM. For this reason, the flexibility of the control for saving the data stored in the DRAM is increased, and the refresh operation of the DRAM can be stopped with a higher probability. Thereby, S
The power consumption of the semiconductor device as a whole can be further reduced without securing an extra variable area for saving DRAM data in the RAM.

The present embodiment is particularly effective, for example, when the state of the semiconductor device continues for a long time after entering the power saving mode.

(Fourth Embodiment) A fourth embodiment of the present invention will be described with reference to FIG. FIG.
FIG. 14 is a block diagram of a semiconductor device having a power saving mode according to a fourth embodiment of the present invention. 5, the same components as those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and the detailed description thereof will be omitted. 5 is different from FIG.
Is provided with a stack evacuation adjustment unit 120.

In the present embodiment, the stack evacuation adjusting unit 120 determines whether the stack area 102b is empty or not.
The data stored in the DRAM 103 is rearranged, and the time is adjusted until the data can be saved in the stack area 102b. For example, if the amount of data stored in the DRAM 103 is larger than the free space in the stack area 102b, the data in the DRAM 103 is organized to reduce the data amount so that the data can be saved to the stack area 102b. The operation of saving to the stack area 102b is waited until the free space in the area 102b increases. After making such an adjustment to save to the stack area 102b, the stack save processing unit 105
The data stored in 103 is saved in the stack area 102b.

As described above, according to the present embodiment, the DR
In a semiconductor device provided with an AM and an SRAM, when shifting to the power saving mode, the data is sorted and the time is adjusted according to the free state of the stack area instead of shifting to the power saving mode immediately after the shift instruction. Thereafter, a save process to the stack area is performed. For this reason, the flexibility of control for saving data stored in the DRAM is increased,
Can be stopped with a higher probability. As a result, it is possible to further reduce the power consumption of the entire semiconductor device without securing an extra variable area for saving the DRAM data in the SRAM.

(Fifth Embodiment) A fifth embodiment of the present invention will be described with reference to FIG. FIG.
It is a block diagram of a semiconductor device provided with a power saving mode according to a fifth embodiment of the present invention. 6, the same components as those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and a detailed description thereof will be omitted. FIG. 6 differs from FIG.
Is provided with a stack information notification processing unit (corresponding to stack information notification control means) 130.

In this embodiment, when a power saving mode shift command is input, the stack information notification processing unit 130
Has a function of indicating the free space of the stack area 102b, and therefore, before the semiconductor device shifts to the power saving mode, the free space of the stack area 102b and the DRAM 103
The information indicating the amount of data existing in the stack is acquired, and is shown to the stack save processing unit 105. Then, the stack evacuation processing unit 10
5, based on this information, for example, when the amount of data stored in the DRAM 103 is larger than the free space of the stack area 102b, after the data in the DRAM 103 is organized and the amount of data is reduced, After the free space in the stack area 102b increases, the data stored in the DRAM 103 can be saved to the stack area 102b. Thereafter, the power saving mode shift processing unit 104 shifts to the power saving mode, so that processing such as erasing or restoring data in the DRAM 103 can be omitted. Further, even when there is data that the user does not want to erase in the DRAM 103, the possibility of stopping the refresh operation of the DRAM 103 can be increased.

As described above, according to the present embodiment, DR
In the semiconductor device including the AM and the SRAM, when shifting to the power saving mode, the function of indicating the free space of the stack area allows the stack evacuation processing unit to execute the free space of the stack area after the data of the DRAM is organized. After the number has increased, a save process to the stack area is performed. For this reason, the flexibility of the control for saving the data stored in the DRAM is increased, and the refresh operation of the DRAM can be stopped with a higher probability. As a result, it is possible to further reduce the power consumption of the entire semiconductor device without securing an extra variable area for saving the DRAM data in the SRAM.

In all of the above-described embodiments, a case has been described in which a DRAM and an SRAM are used as storage means. However, the present invention can be similarly implemented by using other types of memories.

In all the above-described embodiments, the DR
The configuration and operation when the data stored in the AM is saved to the stack area of the SRAM has been described.
The same applies to the case where data stored in the DRAM is saved in the variable area of the SRAM.

[0072]

As described above, according to the present invention, in a semiconductor device having a first storage means (for example, DRAM) and a second storage means (for example, SRAM) having a stack area, In order to save the data stored in the storage means in the stack area of the second storage means, an extra storage area for saving data is secured in the variable area of the second storage means to increase the circuit scale. Accordingly, power consumption of the entire semiconductor device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating an operation of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a block diagram of a semiconductor device according to a third embodiment of the present invention.

FIG. 5 is a block diagram of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 6 is a block diagram of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 7 is a block diagram of a conventional semiconductor device.

FIG. 8 is a flowchart illustrating an operation of a conventional semiconductor device.

[Explanation of symbols]

100 Bus 101 CPU 102 SRAM (second storage unit) 102a Variable area of SRAM 102b Stack area of SRAM 103 DRAM (first storage unit) 103a, 103b, 103c, 103d DRAM
(Multiple storage units) 104 Power saving mode transition processing unit (Power saving mode transition control unit) 105 Stack save processing unit (Stack save control unit) 110 Data deletion / restoration processing unit (Data restoration control unit) 120 Stack save adjustment unit 130 Stack information notification processing unit (stack information notification control means)

Claims (5)

[Claims] A first storage unit, a second storage unit having a stack area, and when a power-saving mode shift instruction is input, data stored in the first storage unit is transferred to the stack area. Stack evacuation control means for performing control for evacuation in the first storage means, and after the data stored in the first storage means has been evicted in the stack area, stop the operation of the first storage means and shift to a power saving mode And a power-saving mode shift control unit for performing control to perform the control. 2. The semiconductor device according to claim 1, wherein said first storage means is a dynamic random access memory; said second storage means is a static random access memory; Means for stopping a refresh operation of the dynamic random access memory,
A semiconductor device for stopping the operation of the dynamic random access memory. 3. The semiconductor device according to claim 1, wherein said first storage means stores data and tag data corresponding to said data, and when a power saving mode shift command is input, said first storage means stores said data. Control for saving tag data to the stack area and acquiring data corresponding to the tag data using the tag data when returning from the power saving mode, and restoring the acquired data to the first storage means A semiconductor device further comprising data restoration control means for performing the data restoration. 4. The semiconductor device according to claim 1, wherein said first storage means comprises a plurality of storage means each of which can be independently stopped in operation, and said stack evacuation control means is When a power-saving mode shift command is input, control for saving data stored in the plurality of storage units to the stack area is performed independently for each of the plurality of storage units. The semiconductor device, wherein the power-saving mode shift control means stops the operation of the storage means in which the data has been saved among the plurality of storage means. 5. The stack information notification control means according to claim 1, wherein when a power-saving mode shift command is input, information on the free space of said stack area is provided to said stack evacuation control means. A semiconductor device further comprising: