JP2002229180A - Reticle for manufacturing semiconductor device and method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the fabrication in high accuracy and to enable the fine patterning working in the manufacture of semiconductor device. SOLUTION: This reticule for the manufacture of semiconductor device is provided with a mask pattern which is for manufacturing a semiconductor device of which the picture element part in which picture elements are arranged in a two-dimensional array type is formed on a central part and the peripheral circuit and the scribing line are disposed on the periphery of the picture element part. In addition, this reticle for the manufacture of semiconductor device and method for manufacturing semiconductor device using the reticle features that the semiconductor device is divided into plural blocks of >=2, the respective divided blocks are replaced with each other and the respective blocks are arranged in such a manner that at least one side of the peripheral circuit and scribing line is arranged on the center.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a reticle for manufacturing a semiconductor device and a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art Conventionally, as a method of forming a fine pattern on a semiconductor substrate, a lithography technique using a projection exposure apparatus (stepper or scanner) has been used. In this projection exposure method, after a predetermined pattern formed on a reticle is transferred to a photoresist applied on a semiconductor substrate (wafer) through a projection lens,
The development is performed to form a fine pattern. The pattern drawn on the reticle is projected to be reduced to a smaller area than the entire surface of the wafer. Then, while moving the wafer relatively to the projection optical system, shots (exposure areas) are arranged at a constant pitch over the entire surface of the wafer.

Usually, when manufacturing a reticle which is a photolithographic mask for manufacturing the semiconductor device, a scribe area for dicing the wafer into chips is provided around a chip layout. This is a Liquid Crystal O liquid crystal display
The same applies to a large-area semiconductor chip such as n Silicon (LCOS).

FIG. 10 schematically shows a layout example of a LCOS chip on a reticle according to a conventional method. As shown in FIG. 10, in the LCOS chip 100, when the chip layout is within the exposure range of a stepper, a scanner, or the like, the pixel unit 102 is disposed at the center of the chip, and each pixel of the pixel unit 102 is surrounded by the pixel unit 102. And a peripheral circuit 106 for controlling the driving circuit 104 is arranged around the driving circuit 104. A pad 108 used for connection to an external circuit is arranged on the outermost periphery of the main body of the LCOS chip 100, and a scribe line 110 having a width δ is provided outside the main body of the LCOS chip 100, that is, on the outermost periphery of the exposure region.
Is arranged.

FIG. 11 shows the LCOS chip 10.
Pixels of the pixel portion 102 of 0 are enlarged and schematically shown. Figure 1
As shown in FIG. 1, each pixel 112 includes a pixel electrode 114,
And a switch transistor 116. The switching transistor 116 switches the application of a voltage to the pixel electrode 114.
Numeral 4 displays an image by driving a liquid crystal (not shown) when a voltage is applied (charge is applied), changes the orientation of the liquid crystal, and changes the way of reflecting light. . Thus, the switching transistor 1
Numeral 16 designates a voltage for driving the liquid crystal applied to the pixel electrode 114, which has a relatively high withstand voltage (for example, 12V to 4V).
0V).

Therefore, the layout of the pixel section 102 is less strict than a normal transistor driven at a low voltage of 3.3 V or 5 V, for example, 1.5 μm to 3 μm.
The layout can be drawn according to the 0 μm rule. Further, a driving circuit 1 for driving the pixel portion 102 in FIG.
As for the transistor 04, a transistor having a relatively high withstand voltage is used. On the other hand, the peripheral circuit 106 that controls the drive circuit 104 of the pixel portion 102 often uses a transistor with a high degree of integration and low-voltage operation for the purpose of high-speed processing of a digital signal. 35 μm
And high processing accuracy of 0.5 μm.

Conventionally, in a semiconductor manufacturing process, FIG.
A pattern is printed on a silicon substrate using a reticle 120 as shown in FIG.
That is, the pattern for one chip of the semiconductor device was exposed at a time. 12, a central portion 122 of the reticle 120 is a portion corresponding to the pixel portion 102 of the LCOS chip 100, a peripheral portion 124 is a portion corresponding to the peripheral circuit 106, and the outermost periphery 126 of the width δ is This is a part corresponding to the scribe line 110.

[0008]

However, since a stepper or scanner used for exposure when printing a pattern on a silicon substrate using a reticle uses an optical lens, an aberration or the like causes a peripheral part of the lens from the center of the lens to be exposed. The processing accuracy of the part is inferior. Therefore, in the LCOS device, when a pattern is printed using a reticle as in the conventional case, a peripheral circuit for low-voltage operation requiring higher precision is actually provided, and a peripheral portion of an optical lens having low processing precision is actually provided. Must be used and exposed.

For example, when exposure is performed using the reticle 120 shown in FIG.
Table 1 shows how the finished dimensions of the transistor in the vicinity of the exposed area indicated by reference numerals P, Q, and R in the figure.

As described above, the gate length is designed to be 0.5 μm
The finished dimension of the transistor is shortened in the periphery of the exposure area. In particular, at the corner Q of the reticle 120, the finished dimension is 0.431, and the difference between the finished dimension and the designed dimension is as large as 0.069. ing. in this way,
When exposure is performed using a conventional reticle, there is a problem that high processing accuracy cannot be obtained particularly in a peripheral circuit for controlling a pixel of a chip that requires high accuracy.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and provides a reticle for manufacturing a semiconductor device and a method of manufacturing a semiconductor device capable of processing a fine pattern with high processing accuracy. As an issue.

[0012]

In order to solve the above-mentioned problems, a first aspect of the present invention is to arrange a pixel section in which pixels operated by a first power supply voltage are two-dimensionally arranged in an array. A peripheral circuit operating at a second power supply voltage lower than the first power supply voltage, and a scribe line disposed around the pixel portion, and having a mask pattern for manufacturing a semiconductor device. A reticle for manufacturing a semiconductor device, wherein the semiconductor device is divided into two or more blocks, and each of the divided blocks is replaced so that at least one side of the peripheral circuit and the scribe line is arranged in the center. Thus, a reticle for manufacturing a semiconductor device, wherein each block is arranged, is provided.

Also, the semiconductor device is divided into four blocks by dividing the semiconductor device into two in the vertical and horizontal directions, and a mask pattern for manufacturing an upper left block among the divided blocks. Is placed in the lower right area, the mask pattern for manufacturing the lower left block is placed in the upper right area, the mask pattern for manufacturing the lower right block is placed in the upper left area, and the upper right block is placed It is preferable that the peripheral circuit and the scribe line are arranged in a cross shape at the center by arranging a mask pattern for manufacturing in a lower left region.

[0014] Similarly, in order to solve the above problems,
According to a second aspect of the present invention, in a photolithographic step of manufacturing a semiconductor device, sequential exposure is performed using the reticle for manufacturing a semiconductor device according to claim 1 or 2,
A method of manufacturing a semiconductor device, wherein a mask pattern of the reticle is repeatedly transferred onto a semiconductor substrate.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a reticle for manufacturing a semiconductor device and a method for manufacturing a semiconductor device according to the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

FIG. 1 schematically shows a method for manufacturing a reticle according to one embodiment of the present invention. FIG. 1 (a)
Indicates a semiconductor device (LCOS chip). As shown in detail in FIG.
The S chip 1 includes a pixel unit 2 and a peripheral circuit 4. LC
The size of the OS chip 1 main body is 20 in the case of the present embodiment.
mm × 16 mm. As described above, the scribe line 6 conventionally used for dicing the chip is used.
(For example, width δ = 100 μm) is provided around
A reticle (see FIG. 12) having the same image as the LCOS chip as shown in FIG. On the other hand, in the present embodiment, the reticle is manufactured by dividing the LCOS chip 1 into a plurality of blocks, rearranging the divided blocks, and arranging peripheral circuits and scribe lines in the center. is there.

That is, in the present embodiment, as shown in FIG. 1A, the LCOS chip 1 (the layout thereof) is divided into two parts in the vertical and horizontal directions, thereby dividing the whole into four parts. Then, the upper left portion A of the LCOS chip 1 is arranged at the lower right of the reticle 10 as shown in FIG. Similarly, the upper right portion B of the LCOS chip 1
Are arranged at the lower left of the reticle 10, the lower left part C of the LCOS chip 1 is arranged at the upper right of the reticle 10, and the lower right part D of the LCOS chip 1 is arranged at the upper left of the reticle 10. In this way, as shown in FIG.
A portion (pixel region) 12 corresponding to the pixel portion 2 of the S chip 1
Are arranged around the periphery, and a reticle 10 in which a part (peripheral circuit area) 14 corresponding to the peripheral circuit 4 and a part (scribe area) 16 corresponding to the scribe line 6 are arranged so as to form a cross at the center is manufactured. . Scribe area 16
Has a width δ, forms a cross at the center, divides the entire reticle 10 into four parts, and forms a peripheral circuit area 14 on both sides of the scribe area 16.

Incidentally, the four divisions are not necessarily 20 mm × 1.
The layout of LCOS chip 1 body of 6mm is 5mm ×
It is not necessary to divide into 4 mm to divide it into 4 mm, and it may be divided at an appropriate place according to the break of the peripheral circuit block or the like. The specific cutting method will be described later in detail. In addition, as will be described later, when exposing a pattern on a silicon substrate, in consideration of an alignment error between shots, each divided pattern is aligned at a boundary.
The pattern at the boundary may be partially thickened or thinned, or the patterns may be overlapped.

The manufacture of the LCOS chip is performed by a known semiconductor manufacturing process. In the photolithography process of the semiconductor manufacturing process, as shown in FIG. 2, a mask pattern is projected onto a silicon substrate 20 using the reticle 10 shown in FIG. They are arranged at a constant pitch. Also, as shown in FIG.
When the LCOS chip 1 is divided, for example, the divided block A of the pixel portion is in contact with a block B and a block C formed in different shots, respectively, and must be properly aligned at this boundary. Therefore, in consideration of the alignment error and the like, the width δ0 = 0.1 μm
An overlapping portion 8 of about m is set, and correspondingly, the width δ0 = around the reticle 10 as shown in FIG.
An overlapping portion 18 of about 0.1 μm may be provided, and overlapping exposure may be performed in this portion. In this way, the mask pattern is printed with the required alignment accuracy even in the portion where the overlapping exposure is performed.

Further, as shown in FIG.
At the end of 0, a portion that is known in advance not to be a complete chip may be partially shielded from light from the exposure area of the stepper or the scanner. After the completion of the wafer process, the dicing portion indicated by the arrow E in FIG. 2 is diced and cut into chips to complete the LCOS chip body.

As described above, the exposure in the photolithography process for manufacturing the LCOS chip is performed by using a reticle 10 as shown in FIG. Is formed. That is, as described above, the ends (boundaries) of adjacent shots
The upper left part of the reticle is in the lower right part of the chip, the lower left part is in the upper right part of the chip, the lower right part is in the upper left part of the chip, and the upper right part is An LCOS chip is manufactured by performing shots so as to be arranged on the respective portions.

At this time, the reticle 1 shown in FIG.
When exposure is performed using 0, the finished dimensions of a transistor having a gate length design dimension of 0.5 μm at the periphery of the exposure area indicated by reference symbols X, Y, and Z in the figure are as follows. Is shown in Table 2. In this way, a value very close to the design dimension was obtained especially at the Y position. In this embodiment, a mask pattern is exposed using a reticle in which a peripheral circuit and a scribe region are arranged in a central portion, and a pixel region is arranged in an outer peripheral portion.
Since the OS chip is manufactured, finer processing can be performed for peripheral circuits that require high-precision processing without being affected by aberration at the peripheral portion of the lens.

Further, as shown in FIG. 1 (b), since the pixel region is arranged outside, there is a problem in which part of the pixel is cut. Hereinafter, the method of cutting the pixel will be described. Basically, the pixels are formed by repeating the same pattern, so that it is sufficient to cut them in an area where a relatively thick pattern is included without any break. In FIG.
An example of how to cut pixels is shown. FIG. 4 is an enlarged plan view showing a pixel portion of the LCOS chip. In FIG. 4, each pixel mainly includes a transistor 30 formed in a diffusion layer formed on a semiconductor substrate (silicon substrate) and a wiring layer 3.
2. A pixel reflector metal layer (reflective pixel electrode) 36 connected to the transistor 30 via the via 34. A light-shielding layer 38 is provided between the pixel reflector metal layer 36 and the wiring layer 32 to prevent external light from affecting the transistor 30. Further, a load capacitance 42 for holding a voltage applied to the pixel reflector metal layer 36 is connected to the transistor 30 via the wiring layer 32 and the contact 40. Reference numeral 44 denotes a polycrystalline silicon layer forming a gate electrode of the transistor 30.

FIG. 5 is a sectional view taken along the line V--V in FIG. As shown in FIG. 5, the LCOS chip includes a diffusion layer (transistor) 30, a load electrode 42, and a pixel reflector metal layer 3 on a semiconductor substrate (silicon substrate) 46.
6 and the like, a transparent liquid crystal facing electrode 48 is formed on the top, and a liquid crystal 50 is arranged between the liquid crystal facing electrode 48 and the pixel reflector metal layer 36. here,
The cut line K is set so as to cut the pixel between the pixel reflector metal layers 36 which are the breaks of each pixel. In addition,
In the present embodiment, the pixel pitch is 16.0 μm × 16.0.
μm, and the cut line width is 0.2 μm. That is, it is set to be 0.1 μm each from one side. In addition, it is preferable to cut so as to avoid gaps between the patterns, particularly, contacts and vias.

That is, as shown in FIG. 6, the cut line K is set so as to cut between the pixel reflector metal layers 36 which are the breaks of each pixel. Further, as shown in FIG. 7, the light-shielding layer 38 is cut off at the center at this time.
There is no problem if the light shielding layer 38 is cut anywhere. As shown in FIG. 8, the wiring layer (metal layer) 32 is arranged along the pixel reflector metal layer 36, and the cut line K is arranged so as not to cut the wiring layer 32. . Further, as shown in FIG. 9, a cut line K is arranged between the two transistors so that the transistor 30 is not divided. In addition, the load capacitance 42 can be cut anywhere without any problem as long as the vias and contacts are avoided.

As described above, in the present embodiment, the gaps between the pixel reflector metal layer 36 and the wiring layer 32 are cut, and the diffusion layer 30 and the polycrystalline silicon layer 44 are shifted. However, even if thinning or fattening occurs, the portion that has little effect is cut. Also, at this time, as shown in FIG. 3, if the overlapping portion 18 of about 0.1 μm is provided around the reticle 10, 0.1 μm can be obtained from each adjacent shot.
A total cut line width of 0.2 μm can be obtained. As a result, even if there is some alignment error, it is possible to compensate for the consistency between adjacent pixels.

As described above, according to this embodiment, a finer pattern can be processed.
More circuit blocks can be mounted as a peripheral circuit than before, and a high-performance chip can be designed and manufactured. In addition, it is possible to set a small circuit design margin, and it is possible to design and manufacture a peripheral circuit that can operate at a higher speed, for example, by operating a 40 MHz operation instead of the conventional 35 MHz operation. Further, it is not necessary to limit the exposure area of the stepper or the scanner in order to keep the processing variation within a desired range. For example, in the past it was only possible to manufacture up to 18 mm
It is possible to manufacture up to 2 mm square, and accordingly, it is possible to design and manufacture a higher-luminance, higher-definition LCOS chip by increasing the pixel size accordingly. Furthermore, a large area chip can be manufactured by a photolithographic apparatus such as a stepper or a scanner manufactured for an old generation having a low lens accuracy.

In the above embodiment, the LCOS chip is divided into four parts, but the present invention is not limited to four parts. That is, the chip layout is divided into a plurality of parts, the divided blocks are rearranged so that the peripheral circuit and the scribe area are arranged in the center of the reticle, a reticle is manufactured, and an LCOS chip is manufactured using the reticle. Then, the peripheral circuit can be processed with high accuracy. For example, a reticle may be manufactured by dividing a chip layout into two parts on the left and right sides, exchanging the left and right sides, so that left and right peripheral circuits are arranged in the center, and one scribe line is arranged vertically in the middle. It may be. In this case, the upper and lower peripheral circuits are the same as the conventional ones, but the left and right peripheral circuits can be processed with sufficiently high definition. Similarly, the chip layout is divided into upper and lower parts, and the upper and lower parts are exchanged so that the upper and lower peripheral circuits are arranged in the center, and one scribe line is arranged in the center in the horizontal direction. May be produced.

Further, even when the chip layout is divided into four parts, the chip layout is not limited to the one divided into a cross as in the above embodiment. The dividing method other than the cross may be any method as long as the peripheral circuit is disposed at the center so as not to be affected by peripheral aberration of the lens. In the above embodiment, a reticle including a mask pattern for one chip is manufactured by rearranging the chip layout divided into four parts. However, if the chip area is too large to fit in the exposure area of the exposure apparatus, the divided chip layout can be divided and arranged on two or more reticles. For example, a horizontally long chip is divided into two vertically and four horizontally to
And a first reticle in which peripheral circuits and scribe lines are arranged in a cross at the center, and the four blocks in the center are interchanged. Thus, it is also possible to form a second reticle in which peripheral circuits and scribe lines are arranged in the center in the horizontal direction. As described above, the reticle for manufacturing a semiconductor device and the method for manufacturing a semiconductor device according to the present invention have been described in detail. However, the present invention is not limited to the above examples, and various improvements can be made without departing from the gist of the present invention. Of course, changes may be made.

[0030]

As described above, according to the present invention, a finer pattern can be processed without being affected by the aberration of the lens of the stepper, and more circuit blocks are mounted as peripheral circuits than before. It has become possible to design and manufacture high-performance chips.

[Brief description of the drawings]

FIG. 1 is an explanatory view schematically showing a method for manufacturing a reticle according to one embodiment of the present invention, and FIG.
(B) is a layout of the reticle.

FIG. 2 is an explanatory view showing a state where a shot is made on a substrate using the reticle of the present embodiment.

FIG. 3 is an explanatory diagram showing a state in which overlapping portions are provided in a reticle of the present embodiment to achieve matching between pixels;
(A) is a layout of an LCOS chip, and (b) is a layout of a reticle.

FIG. 4 is a plan view of a pixel region for showing a line for cutting a pixel in the present embodiment.

FIG. 5 is a sectional view taken along the line VV of FIG. 4;

FIG. 6 is a plan view showing a relationship between a cut line and a pixel reflector metal layer.

FIG. 7 is a plan view showing a relationship between a cut line and a light shielding layer.

FIG. 8 is a plan view showing a relationship between a cut line and a wiring layer.

FIG. 9 is a plan view showing a relationship between a cut line and a diffusion layer.

FIG. 10 is an explanatory view schematically showing a layout example of a conventional LCOS chip on a reticle.

FIG. 11 is a schematic view showing pixels of an LCOS chip.

FIG. 12 is a plan view showing a conventional reticle.

[Explanation of symbols]

 Reference Signs List 1 semiconductor device (LCOS chip) 2 pixel unit 4 peripheral circuit 6 scribe line 10 reticle 12 pixel region 14 peripheral circuit region 16 scribe region 18 overlapping unit 20 silicon substrate 22 shot 30 diffusion layer (transistor) 32 wiring layer 34 via 36 pixel Reflector metal layer 38 light shielding layer 40 contact 42 load capacitance 44 polycrystalline silicon layer 46 semiconductor substrate (silicon substrate) 48 liquid crystal counter electrode 50 liquid crystal

Claims (3)

[Claims] 1. A pixel which operates at a first power supply voltage has a pixel portion arranged in a two-dimensional array at a central portion, and operates at a second power supply voltage lower than the first power supply voltage. A reticle for manufacturing a semiconductor device, having a mask pattern for manufacturing a semiconductor device, wherein a peripheral circuit and a scribe line to be disposed are arranged around the pixel portion, wherein the semiconductor device is divided into two or more blocks. A reticle for manufacturing a semiconductor device, wherein the reticle is divided so that each of the divided blocks is replaced such that at least one side of the peripheral circuit and the scribe line is disposed at the center. 2. A mask pattern for manufacturing an upper left block among the divided blocks by dividing the semiconductor device into two in the vertical and horizontal directions, respectively. Is placed in the lower right area, the mask pattern for manufacturing the lower left block is placed in the upper right area, the mask pattern for manufacturing the lower right block is placed in the upper left area, and the upper right block is placed 2. The reticle for manufacturing a semiconductor device according to claim 1, wherein a mask pattern for manufacturing is arranged in a lower left area, so that the peripheral circuits and scribe lines are arranged in a cross shape at a central portion. 3. A semiconductor device manufacturing photolithographic process, wherein a reticle for manufacturing a semiconductor device according to claim 1 or 2 is used for sequential exposure, and a mask pattern of the reticle is repeated on a semiconductor substrate. A method for manufacturing a semiconductor device, comprising transferring.