JP2002208844A - Glitch elimination circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a glitch elimination circuit in which a circuit scale and power consumption can be reduced for eliminating glitches which mix in the input signal. SOLUTION: This glitch elimination circuit consists of a delay circuit 23 for adding a delays that is larger than the glitch width mixed in input data (Y), a comparator circuit 22 for comparing the logical value of the input data (Y) with the logical value of output data (Z) and deciding agreement/ disagreement, and a latch circuit 24 to which delay data (DY) outputted from the delay circuit 23 and the decision results (GY) of the comparator circuit 22 are inputted and which holds the delay data (DY), when the decision results (GY) of the comparator circuit 22 disagree and the output data (Z), when the decision results (GY) agree and outputs output data (Z) from an output terminal 25.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a deglitch circuit,
In particular, the present invention relates to a glitch removal circuit that removes a glitch without using a clock signal of a logic circuit.

[0002]

BACKGROUND OF THE INVENTION Glitch refers to pulsed or whiskered noise having a relatively short duration and indistinct vertices. Such a glitch causes a malfunction in a logic (digital) circuit. Therefore, it is necessary to remove the glitch and improve the reliability of the operation of the digital circuit. A glitch removing circuit is used for this purpose. That is, when a combinational logic (digital) circuit is implemented using a plurality of logic elements, a pulse that cannot theoretically exist may be generated. Such a pulse is generally generated because the operation time of each logic element varies.
Normally, a pulse (glitch) having an extremely short pulse width is obtained. This glitch must be removed because it causes a malfunction of another logic circuit connected in the subsequent stage.

The prior art of such a glitch detection circuit is disclosed in, for example, Japanese Unexamined Patent Application Publication No. 11-214965, entitled "Semiconductor Device".
And "Noise prevention circuit" in Japanese Utility Model Application Laid-Open No. 58-169732. FIG. 4 shows a configuration of the above-described prior art glitch removing circuit for removing glitches without using a clock of a logic circuit. This glitch removal circuit includes a delay circuit 110, an exclusive OR circuit (EXNOR) 111, a delay circuit 112, and a D-type flip-flop (D-FF) circuit 113.

The input terminal 100 receives an input signal (OUT) containing a glitch. This input signal (OUT) is used as a signal (E) 104 to which a delay is added using a delay circuit (A) 110, and the input signal (OUT)
Itself is input to the EXNOR 111 and the input signal (OU
A change point detection pulse signal (F) 103 of T) is generated. This signal (F) is delayed by a delay circuit (B) 112 and input to a clock terminal C of a D-FF circuit 113. Further, the input signal (OUT) itself is converted to DF
Input to the input terminal D of F113. Here, by setting the amount of additional delay in the delay circuit (B) 112 to a time sufficiently larger than the pulse width of the glitch, the D-FF 113
Is latched after the glitch, it is possible to prevent the glitch from being propagated to the output terminal 102.

FIG. 5 is a timing chart showing the operation of the conventional glitch removing circuit shown in FIG. Here, FIGS. 5A to 5F show OUT, D, E, F, C, and Q respectively entered in FIG. That is,
(A) is an input signal (OU) input to the input terminal 100.
T) and (b) show data (D) input to the input terminal D of the D-FF circuit 113, and (c) shows a delay circuit (A) 110
Signals (E) 104 and (d) delayed by
(E) Delays the output signal 103 of the EXNOR 111 by the delay circuit (B) 112, and
Signal (C) input to clock terminal C of F circuit 113
101 and (f) are output signals (Q) output from the Q output terminal of the D-FF circuit 113 to the output terminal 102 of the glitch removal circuit.

[0006]

Generally, when a logic circuit is realized using actual elements, the design is easier as the number of places where the delay adjustment is required is smaller. However, FIG.
The conventional technique described above with reference to FIG. 1 has a problem that the design is not easy because there are a plurality of delay circuits that need to be adjusted. Further, the prior art has a problem that the circuit configuration is redundant, and the circuit scale and power consumption are large because a plurality of delay circuits exist as described above.

[0007]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a glitch removing circuit which can be easily realized with an actual device and does not increase the circuit scale and power consumption.

[0008]

SUMMARY OF THE INVENTION A glitch removing circuit according to the present invention is a circuit for outputting a signal obtained by removing a glitch from input data containing a glitch as output data. A delay circuit for adding a large delay time, a comparison circuit for comparing input data and output data to determine match / mismatch, inputting the delay data output from the delay circuit and the determination result of the comparison circuit, and outputting output data And a latch circuit that performs the operation.

According to a preferred embodiment of the glitch removing circuit of the present invention, the latch circuit receives the delayed data from the delay circuit and the judgment result of the comparison circuit, respectively.
It has a pair of input terminals, and an output terminal that outputs delay data when the determination result of the comparison circuit does not match, and holds and outputs the output data when the determination result matches. An exclusive OR circuit is used as the comparison circuit. As the delay circuit, a plurality (even number) of cascade-connected inverters is used. The glitch removing circuit is connected to each of a plurality of signal lines such as a bus, and removes a glitch of data flowing through the signal lines.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The construction and operation of a preferred embodiment of a glitch removal circuit according to the present invention will be described in detail with reference to the accompanying drawings.

First, FIG. 1 shows a basic configuration of a preferred embodiment of a glitch removing circuit according to the present invention. The glitch removal circuit 20 includes a comparison circuit 22, a delay circuit 23, and a latch circuit 24. From an input terminal 21, an input signal or input data (Y) is input to one input terminal of a comparison circuit 22 and a delay circuit 23. The Q terminal of the latch circuit 24 is connected to the output terminal 25 of the glitch removal circuit 20.
And the other input terminal of the comparison circuit 22.

The input terminal 21 of the glitch removing circuit 20
Input data (Y) input through the delay circuit 23
And one input terminal of the comparison circuit 22. The delay circuit 23 outputs the input data (Y) by adding a delay amount larger than the width of the glitch to be removed. The data (DY) output from the delay circuit 23 is input to the D input of the latch circuit 24. On the other hand, Q of the latch circuit 24
The data (Z) output from the output is output as output data via the output terminal 25, and is output from the comparison circuit 22.
Is input to the other input terminal. The comparison result (GY) output from the comparison circuit 22 is input to the G input of the latch circuit 24 and used for controlling the data holding operation of the latch circuit 24.

Next, the operation of the glitch removal circuit according to the present invention shown in FIG. 1 will be described in detail. The change in the logical value of the input data (Y) input via the input terminal 21 is determined by comparing the input data (Y) with the output data (Z) currently held by the latch circuit 24 by the comparison circuit 22. Is detected by When there is a change in the input data (Y), the comparison result (GY) between the input data (Y) and the output data (Z) does not match. Therefore, the latch circuit 24
Stops the holding operation from the time when the mismatch occurs, and operates to pass the data as it is.

On the other hand, when the change of the input data (Y) is not caused by the glitch, the new logical value of the input data (Y) is transmitted through the delay circuit 23 and the latch circuit 24 and output. And when this new logical value is output,
The comparison result (GY) of the comparison circuit 22 returns from non-coincidence to coincidence, and the output logic value is held by the latch circuit 24.
When the logic value of the input data (Y) changes due to the glitch, the latch circuit 24 operates to pass the data from the point of occurrence of the glitch, but the delay amount added to the data by the delay circuit 23 is smaller than the glitch width. Before the glitch passes through the latch circuit 24, the comparison result (GY) of the comparison circuit 22 returns from non-coincidence to coincidence, and the logical value of the data input at the time before the glitch is held. The glitch does not propagate to the output terminal 25,
Thus, glitches are eliminated.

Next, FIG. 2 shows a specific circuit configuration diagram of a preferred embodiment of the glitch removal circuit of the present invention shown in FIG. 1 described above. This glitch removing circuit 20 is provided by the comparing circuit 2
2 is constituted by an exclusive OR (EXOR) circuit 221. The delay circuit 23 is composed of a plurality (even number) of cascaded inverters 231 to 23n. Input data (Y) input via the input terminal 21 is input to one of input terminals of inverters 231 to 23n forming the delay circuit 23 and an EXOR circuit 221 forming the comparison circuit 22. The delay amount of the delay circuit 23 is
Adjustment is performed with the number of connection stages of 1 to 23n so that the delay amount is larger than the glitch width. The data (DY) output from the delay circuit 23 is input to the D input of the latch circuit 24. Output data (Z) output from the Q output of the latch circuit 24 is output via the output terminal 25 and is input to the other input terminal of the EXOR 221. EX
The comparison result (GY) output from the OR circuit 221 is input to the G input of the latch circuit 24 and used for controlling the data holding operation of the latch circuit 24.

Next, the operation of the glitch removal circuit 20 of FIG. 2 will be described with reference to the timing chart of FIG. In the timing chart of FIG. 3, (a) indicates the input terminal 2
1 are input to the delay data (D) from the delay circuit 23 (or the inverter 23n).
Y) and (c) show output data (Z) output from the Q output terminal of the latch circuit 24 to the output terminal 25, and (d) shows EXO data.
Outputs (GY) and (e) from the R circuit 221 indicate the operation of the latch 24. The logical value of the input data (Y) input via the input terminal 21 is “0” during the time t1 to t3.
Alternatively, an example is shown in which a low level, “1” or a high level during times t3 to t5, and “0 (glitch)” during times t5 to t6 are input.

First, the operation in the case where the change in the logical value of the input data (Y) is not due to a glitch will be described. When the logical value of the input data 21 changes from “1” to “0” at time t1, the output (GY) of the EXOR circuit 221 becomes “1”.
(That is, the logical values of the input data (Y) and the output data (Z) do not match). When the output of the EXOR circuit 221 is “1”, the latch circuit 24 outputs the value of the D input as it is (through operation). Therefore, the logical value “0” of the input data (Y) is determined by the delay circuit 23 and the latch circuit 2.
4 and is output from the output terminal 25 of the glitch removal circuit 20 as output data (Z). When the logical value “0” propagates to the output data (Z), at time t2, the output (GY) of the EXOR circuit 221 becomes “0” (that is, the logical value between the input data (Y) and the output data (Z)). (The values match). Therefore, the latch circuit 24
Holds a logical value “0” from time t2. From time t3
The timing chart at t4 indicates that the input data (Y)
Is changed from “0” to “1”, and the operation is the same as the operation at the time t1 to t2 described above.

Next, the operation when the change in the logical value of the input data (Y) is caused by a glitch will be described. At time t5, the logical value of the input data (Y) becomes “1” due to glitch.
→ When it changes to “0”, the output of the EXOR circuit 221 becomes
"1" (that is, a state where the logical values of the input data (Y) and the output data (Z) do not match). Latch circuit 24
Is D when the output of the EXOR circuit 221 is “1”.
The input value is output as it is (through operation). However, the inverter 23n constituting the delay circuit 23
Since the delay amount of the delay output (DY) from the input data (Y) is larger than the width of the glitch, the output data (Z) has a glitch (logical value “0”) even at time t6 when the glitch disappears from the input data (Y). Does not propagate. Therefore, at time t6, the output (GY) of the EXOR circuit 221 becomes “0”, and the latch circuit 24 outputs the logical value “1” before the glitch input.
Hold.

The configuration and operation of the preferred embodiment of the glitch removal circuit according to the present invention have been described above in detail. However, it should be noted that such an embodiment is merely an example of the present invention and does not limit the present invention in any way. It will be readily apparent to those skilled in the art that various modifications can be made in accordance with the particular application without departing from the spirit of the invention.

[0020]

As described above, according to the glitch removing circuit of the present invention, the following practically remarkable effects can be obtained. First,
In addition, since the number of delay circuits that need to be adjusted is reduced from two in the prior art to one, it can be halved and implementation (or implementation) is easy. Second, the circuit scale and power consumption can be reduced by simplifying the circuit configuration. These effects are particularly remarkable when a plurality of glitch removing circuits are required (for example, when removing glitches of a large number of signals in a bus).

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a preferred embodiment of a glitch removal circuit according to the present invention.

FIG. 2 is a specific circuit configuration diagram according to a preferred embodiment of the glitch removal circuit shown in FIG. 1;

FIG. 3 is a timing chart showing an operation of the glitch removal circuit according to the present invention shown in FIG. 2;

FIG. 4 is a circuit configuration diagram of a conventional glitch removal circuit.

FIG. 5 is a timing chart showing the operation of the conventional glitch removal circuit shown in FIG.

[Explanation of symbols]

 Reference Signs List 20 glitch removing circuit 21 input terminal 22 comparison circuit 221 exclusive OR (EXOR) circuit 23 delay circuit 231 to 23n inverter 24 latch circuit 25 output terminal

Claims (5)

[Claims] 1. A glitch removing circuit for outputting a signal obtained by removing a glitch from glitch-mixed input data as output data, comprising: a delay circuit for adding a delay larger than a glitch width to the input data; A comparison circuit that compares data and the output data to determine a match / mismatch; and a latch circuit that receives the delay data output from the delay circuit and the determination result of the comparison circuit as input, and outputs the output data. A glitch elimination circuit, comprising: 2. The latch circuit outputs a pair of input terminals for receiving the delay data from the delay circuit and the determination result of the comparison circuit, respectively, and outputs the delay data when the determination result of the comparison circuit does not match. 2. The glitch removing circuit according to claim 1, further comprising: an output terminal for holding and outputting the output data when the values match. 3. The glitch removing circuit according to claim 1, wherein an exclusive OR circuit is used as said comparison circuit. 4. The glitch removing circuit according to claim 1, wherein a plurality of (even number) cascaded inverters are used as said delay circuit. 5. The glitch removing circuit according to claim 1, wherein the glitch removing circuit is connected to a bus or the like for each of a plurality of signal lines, and removes a glitch of data flowing through the signal lines.