JP2002204078A - Multilayer circuit board and semiconductor integrated circuit device - Google Patents

Abstract

(57) Abstract: A multi-layer wiring board and a semiconductor integrated circuit device are formed at a low cost without a peeling of a wiring layer or a crack in an interlayer insulating film. SOLUTION: An interlayer insulating film 4 is made of a hard-to-rough resin layer 2 such as a thermoplastic resin such as polyethersulfone resin or polyetherimide resin, or a thermosetting resin such as polyimide resin or polybenzoxazole resin. It is composed of an easily roughening resin layer 3 such as an epoxy resin which covers the surface of the hardly roughening resin layer 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer circuit board and a semiconductor integrated circuit device, and more particularly, to preventing a crack from being generated when forming a multilayer wiring structure with a fine wiring pattern, and at the same time, forming a conductive pattern. The present invention relates to a multilayer circuit board and a semiconductor integrated circuit device characterized by the structure of an interlayer insulating film for improving adhesion.

[0002]

2. Description of the Related Art Conventionally, printed circuit boards have been generally used for compactly incorporating electronic components into electronic equipment. This printed circuit board is formed by etching a copper foil bonded to a laminate according to an electronic circuit pattern. Although it is difficult to mount electronic components at a high density, it is advantageous in terms of cost.

On the other hand, for hybrid ICs, a build-up multi-layer wiring structure has been used for a long time. This is done by sequentially printing and stacking a thick film paste of a conductor and an insulator on a ceramic substrate and then firing. Although it is disadvantageous in terms of cost, it is characterized in that high-density mounting becomes possible.

In recent years, along with demands for miniaturization, high performance, and low price of electronic devices, miniaturization, multi-layering, and high-density mounting of electronic components formed on a printed circuit board have been demanded. Has rapidly advanced, and studies on whether to adopt a build-up multilayer wiring structure for printed circuit boards have been activated.

The interlayer insulating film used in such a build-up multilayer wiring structure is formed between layers of an electronic circuit pattern, and is formed on the entire surface except for a connection portion with an upper electronic circuit pattern. The connection point with the electronic circuit pattern is usually called a via hole.

Here, a process for forming a conventional build-up multilayer wiring structure will be described with reference to FIGS. See FIG. 5 (a) First, bisphenol A type epoxy resin (manufactured by Toto Kasei), novolak type phenol resin PSM-4300 (trade name, manufactured by Gunei Chemical) as an epoxy curing agent, and imidazole 2E4MZ (manufactured by Shikoku Chemicals) as a curing accelerator. A resin composition is prepared by blending ethyl cellosolve acetate as a solvent in a ratio of 20 parts by weight: 20 parts by weight: 1 part by weight: 60 parts by weight (see Table 1 described later).

Next, the prepared resin composition is applied on a printed circuit board (FR-4) 41 provided with a wiring pattern (not shown) by spin coating,
After heating and curing for minutes, an interlayer insulating film 42 made of an epoxy resin film having a thickness of, for example, 30 μm is formed.

Referring to FIG. 5B, the interlayer insulating film 42 is irradiated with a laser beam 43 to form a via hole 44 for connecting to a wiring pattern provided on the printed circuit board 41.

Next, as shown in FIG. 5 (c), the substrate was immersed in a preconditioner conditioner (trade name, manufactured by Shipley) at 60 ° C. for 10 minutes, and then dipped in a potassium permanganate drug promoter (trade name, manufactured by Shipley).
The exposed surface of the interlayer insulating film 42 is roughened by sequentially performing immersion at 10 ° C. for 10 minutes and immersion at 60 ° C. for 10 minutes in a neutralizer Nutriser (trade name, manufactured by Shipley). In this chemical etching process using an alkali or an oxidizing agent, the interlayer insulating film 42
A large number of fine holes are formed on the exposed surface of.

Next, the entire surface is formed to a thickness of, for example, 0.3 μm by an electroless plating method using a copper sulfate-based plating solution.
A plating seed layer 45 made of a Cu electroless plating film is formed. In this electroless plating step, the interlayer insulating film 4
Cu enters into a large number of fine holes formed on the surface of the surface of the plating seed layer 4 due to its anchor effect.
5 and the interlayer insulating film 42 are improved in adhesion.

Next, referring to FIG. 5D, a plating frame 46 made of a resist pattern corresponding to the wiring pattern of the first layer is used as a mask, and the thickness is selectively changed by an electrolytic plating method using a copper sulfate-based plating solution. For example, a wiring layer 4 made of a 10 μm Cu plating film
7, 48 are formed.

Next, after the plating frame 46 is removed, the exposed plating seed layer 45 is removed using an aqueous solution of copper chloride.

Referring to FIG. 6 (f), the above-prepared resin composition is applied again by the spin coating method so that the thickness of the resin composition becomes, for example, 3
A second interlayer insulating film 49 made of a 0 μm epoxy resin film is formed.

Referring to FIG. 6G, a build-up multilayer wiring circuit board is obtained by sequentially repeating the via hole forming step, the plating seed layer forming step, the wiring layer forming step, and the interlayer insulating film forming step. . Note that the drawing shows a two-layer structure.

As an interlayer insulating film constituting such a build-up multilayer wiring circuit board, in addition to the resin composition having the above-mentioned composition, a resin composition comprising an epoxy acrylate, a sensitizer, a curing agent, and the like ( If necessary, refer to
44431 and JP-B-51-40451) and a resin composition containing a reaction product obtained by reacting an unsaturated monocarboxylic acid with an epoxy resin and further adding a polybasic acid anhydride as a base polymer ( If necessary, an easily roughening resin composition which can be easily roughened, such as JP-B-56-40329 and JP-B-57-45785, can be used.

[0016]

In recent years, portable electronic devices have rapidly spread, and there is a demand for further miniaturization and multilayering of circuits on circuit boards.
Studies have been made to form four or more interlayer insulating films having a thickness of about m. In this case, the mechanical strength of the interlayer insulating film becomes a problem.

That is, when an interlayer insulating film is formed, a stress is generated due to a coefficient of thermal expansion with the substrate and the like, but the damage due to the stress is increased by the multi-layer structure, and as a result, a stress crack is easily generated. In addition, electronic components mounted on a substrate are also increased in density, which also causes stress.

The easily roughening resin such as the epoxy resin described above has relatively low mechanical strength, and it is difficult to form a tough film by itself. Therefore, it is difficult to form a multilayer circuit board using epoxy resin. Is difficult. For example, if the interlayer insulating film is
When the layers are formed, there is a problem that stress cannot be tolerated and a stress crack occurs in the interlayer insulating film.

FIG. 7 shows an interlayer insulating film made of the above-described epoxy resin film.
FIG. 4 is a schematic cross-sectional view of a conventional build-up multilayer wiring circuit board in which layers are formed, in which occurrence of stress cracks 62 due to stress is observed in an interlayer insulating film in each layer.

On the other hand, in order to prevent the occurrence of stress cracks due to multilayering, a thermosetting polyimide resin or a thermoplastic polyether sulfone resin having high mechanical strength may be used. Since it is difficult to form a plating seed layer by an electroless plating method due to the difficulty in forming a plating seed layer, this situation will be described with reference to FIG.

Referring to FIG. 8A, FIG. 8A shows polyether sulfone (Sumika Excel: trade name, manufactured by Sumitomo Chemical Co., Ltd.) and a solvent, instead of the above-described interlayer insulating film made of epoxy resin. N
1 is a schematic cross-sectional view of a principal part of a first reference example using a polyethersulfone composition formed by blending -methylpyrrolidone in a ratio of 40 parts by weight: 60 parts by weight. In this case, since it is difficult to perform electroless plating, the plating seed layers 64, 66, and 68 were formed by a sputtering method.

In this case, although the stress crack does not occur, there is a problem that the solvent crack 70 due to the solubility of the polyether sulfone in the solvent is found in the interlayer insulating film of each layer as shown in the figure.

FIG. 8 (b) FIG. 8 (b) shows a polyimide resin (Chemite: trade name of Toshiba Chemical) and N-methyl as a solvent instead of the above-mentioned conventional interlayer insulating film made of epoxy resin. It is a schematic principal part sectional drawing of the 2nd reference example using the polyimide resin composition formed by mix | blending pyrrolidone by 40 weight part: 60 weight part. Also in this case, since it is difficult to perform electroless plating, the plating seed layers 64, 6
6, 68 were formed by a sputtering method.

In this case, although stress cracks and solvent cracks 70 do not occur, it is difficult to form a plating seed layer by the electroless plating method as described above, so that a vacuum treatment such as a sputtering method is required. Therefore, there is a problem that it is unsuitable for a manufacturing process of a low-cost multilayer circuit board.

In addition, since the polyimide resin film, which is a thermosetting resin, does not undergo a chemical reaction at the time of film formation, there is a problem that the adhesion to the application surface is poor and the reliability of the multilayer wiring circuit board is reduced.

Accordingly, an object of the present invention is to form a multi-layer wiring structure free of peeling of a wiring layer and generation of cracks in an interlayer insulating film at low cost.

[0027]

FIG. 1 is an explanatory view of the principle configuration of the present invention. Referring to FIG. 1, means for solving the problems in the present invention will be described. In the drawings, a substrate 1 is a circuit board on which a wiring pattern is formed, a semiconductor substrate on which devices are formed, or the like. See FIG. 1 In order to achieve the above-mentioned object, the present invention relates to a multi-layer circuit board, wherein an interlayer insulating film 4 is made of a thermoplastic resin such as polyethersulfone resin or polyetherimide resin, a polyimide resin or a polybenzoxazole resin. Hard-to-roughen resin layer 2 such as a thermosetting resin, etc .;
And characterized in that:

As described above, by forming the interlayer insulating film 4 into the two-layer structure of the hard-roughening resin layer 2 and the hard-roughening resin layer 3, mechanical strength is secured by the hardening-roughening resin layer 2. Then, it is possible to form the plating seed layer 5 by the electroless plating method by the easily roughening resin layer 3 provided on the surface,
A low-cost multilayer wiring circuit board can be realized.

Further, an easily roughening resin layer 3 such as an epoxy resin
Exhibits the solvent resistance and adhesiveness upon curing, so that even if the hardly roughening resin layer 2 having poor film adhesion is provided, the interlayer insulating film 4
The film adhesion as a whole is sufficiently ensured, and the reliability does not decrease.

Further, the interlayer insulating film 4 having such a two-layer structure is used.
Is also effective in semiconductor integrated circuit devices,
By using an organic insulating film having a lower dielectric constant than the inorganic insulating film such as O ₂ as the interlayer insulating film 4, the parasitic capacitance can be reduced, and thereby the signal delay can be reduced.

[0031]

Referring to FIGS. 2 and 3, a description will be given of a manufacturing process of a build-up multilayer wiring structure according to a first embodiment of the present invention. See FIG. 2 (a) First, polyethersulfone (Sumika Excel: trade name, manufactured by Sumitomo Chemical) and N-methylpyrrolidone as a solvent in a ratio of 40 parts by weight: 60 parts by weight are mixed. Then, a bisphenol A type epoxy resin (manufactured by Toto Kasei), a novolak type phenol resin PSM-4300 (trade name, manufactured by Gunei Chemical) as an epoxy resin curing agent, and imidazole 2E as a curing accelerator
20 parts by weight of 20 parts by weight of 4MZ (trade name of Shikoku Chemicals) and ethyl cellosolve acetate as a solvent.
Part by weight: 60 parts by weight to prepare an epoxy resin composition.

Next, the prepared polyethersulfone composition is applied on a printed circuit board (FR-4) 11 provided with a wiring pattern (not shown) by a spin coating method, and is applied at 100 to 200 ° C., for example. Heated at 180 ° C. for 30 minutes and dried to form a hard-to-roughen resin layer 12 made of a polyethersulfone resin film having a thickness of, for example, 30 μm.
Next, the prepared epoxy resin composition is applied onto the hard-to-roughen resin layer 12 by using a spin coating method.
By heating and curing at 0 ° C., for example, 180 ° C. for 60 minutes, the easily roughening resin layer 13 made of an epoxy resin film having a thickness of, for example, 3 μm is formed to form an interlayer insulating film 14 having a two-layer structure.

Next, as shown in FIG. 2B, the interlayer insulating film 14 is irradiated with a laser beam 15 to form a via hole 16 for connecting to a wiring pattern provided on the printed circuit board 11.

Next, as shown in FIG. 2 (c), the substrate was immersed in a preconditioner conditioner (trade name, manufactured by Shipley) at 60 ° C. for 10 minutes.
By immersing in a neutralizing agent Nutriser (trade name of Shipley Co., Ltd.) for 10 minutes at 60 ° C. and etching the surface sequentially.
The exposed surface of the interlayer insulating film 14 is roughened. In the chemical etching process using the alkali or the oxidizing agent, a large number of fine holes are formed on the surface of the easily roughening resin layer 13 on the interlayer insulating film 14.

Then, the entire surface is formed to a thickness of, for example, 0.3 μm by an electroless plating method using a copper sulfate-based plating solution.
A plating seed layer 17 made of a Cu electroless plating film is formed. In this electroless plating step, the interlayer insulating film 1
Cu enters into a large number of fine holes formed on the surface of No. 4, and the adhesion between the plating seed layer 17 and the interlayer insulating film 14 is improved by the anchor effect.

Next, referring to FIG. 2 (d), the plating frame 18 made of a resist pattern corresponding to the wiring pattern of the first layer is used as a mask, and the thickness is selectively changed by an electrolytic plating method using a copper sulfate-based plating solution. For example, a wiring layer 1 made of a 10 μm Cu plating film
9 and 20 are formed.

Next, after the plating frame 18 is removed, the exposed plating seed layer 17 is removed using an aqueous solution of copper chloride.

Next, the above-prepared two resin compositions are successively applied again by spin coating and dried or cured to obtain a polyether sulfone resin film having a thickness of, for example, 30 μm. A second interlayer insulating film 23 is formed by forming an easily roughening resin layer 21 made of an epoxy resin film having a thickness of, for example, 3 μm and a hardly roughening resin layer 21 made of

Referring to FIG. 3G, the via hole forming step, the plating seed layer forming step, the wiring layer forming step, and the interlayer insulating film forming step are sequentially repeated until five interlayer insulating films are formed. As a result, a build-up multilayer wiring circuit board is obtained. Note that the drawing shows a four-layer structure.

When the build-up multilayer wiring circuit board manufactured as described above was observed with a microscope, no stress crack or solvent crack was found.
7, 24 and 30 were also well formed.

In the first embodiment of the present invention, since the interlayer insulating film is made of a polyethersulfone resin film coated with an epoxy resin, the mechanical strength is increased by the polyethersulfone resin film. As a result, stress cracks do not occur.

Since the surface of the polyethersulfone resin film is coated with an epoxy resin exhibiting solvent resistance and adhesiveness upon curing, the polyethersulfone resin is applied in the step of forming an upper interlayer insulating film. At this time, the lower polyethersulfone resin film is not dissolved, and no solvent crack occurs.

Also, when the wiring layer is formed, the surface exposed on the surface is the epoxy resin of the easily roughening resin.
The conventional roughening treatment can be performed as it is, and as a result, the plating seed layers 64, 66, and 68 can be formed by the electroless plating method, so that the cost can be reduced.

Next, a build-up multilayer wiring structure according to a second embodiment of the present invention will be described with reference to FIG. 4. A polyimide resin is used instead of the polyether sulfone resin as the hard-to-roughen resin layer. Since this embodiment is exactly the same as the above-described first embodiment except for using, the description is simplified.

First, a polyimide resin (chemitite: trade name of Toshiba Chemical Co., Ltd.) and N-methylpyrrolidone as a solvent were mixed in a ratio of 40 parts by weight: 60 parts by weight to prepare a polyimide resin composition. Polyimide resin film is hardly roughened resin layer 3
6, 37, 38 and 39 are used, and a build-up multilayer wiring circuit board schematically shown in the drawing is formed in exactly the same manner as in the first embodiment.

When the build-up multilayer wiring circuit board manufactured in this way was observed with a microscope, no stress crack or solvent crack was found.
7, 24 and 30 were also well formed.

In the second embodiment of the present invention, since each interlayer insulating film is made of a polyimide resin film coated with an epoxy resin, mechanical strength is secured by the polyimide resin film, so that stress is reduced. No cracks occur.

When the wiring layer is formed, the surface exposed at the surface is an easily roughening resin epoxy resin.
The conventional roughening treatment can be performed as it is, and as a result, the plating seed layers 64, 66, and 68 can be formed by the electroless plating method, so that the cost can be reduced.

Further, since the epoxy resin develops adhesiveness by curing, it is possible to improve the poor film adhesion when the polyimide resin is used alone.
The reliability of the multilayer wiring circuit board can be improved.

[0050]

[Table 1]

Table 1 summarizes the composition of the resin, the structure of the resin layer, and the state of the film in the first and second embodiments, the conventional example, and the first and second reference examples. As is clear from Table 1, it is understood that excellent film properties can be obtained by using an interlayer insulating film having a two-layer structure of a hard-roughening resin layer and a roughening-resistant resin layer.

Next, although not shown, a semiconductor integrated circuit device according to a third embodiment of the present invention will be briefly described. First, similarly to a conventional semiconductor integrated circuit device, devices such as MOSFETs are formed on a silicon substrate, and SiO ₂ is formed.
After providing an inorganic interlayer insulating film, a source / drain electrode and a gate lead electrode are formed.

Next, after providing an interlayer insulating film having the same two-layer structure of polyethersulfone resin and epoxy resin as in the first embodiment, a via hole is formed in the interlayer insulating film.

Next, after performing the above-described roughening treatment, a barrier layer made of a TiN film for preventing Cu migration and a plating seed layer made of a Cu film are sequentially formed by a sputtering method. After that, a wiring layer is formed by using an electrolytic plating method.

Next, after removing the exposed portions of the plating seed layer and the barrier layer, an interlayer insulating film having a two-layer structure may be formed again. Thereafter, a via hole forming step, a plating seed layer forming step, and a wiring The semiconductor integrated circuit device can be obtained by sequentially repeating the layer forming step and the interlayer insulating film forming step a required number of times.

[0056] In a third embodiment of the present invention, since an interlayer insulating film of a semiconductor integrated circuit device uses the lower organic insulating film having a dielectric constant than inorganic insulating film such as SiO _2, miniaturization , The increase in parasitic capacitance and the accompanying signal delay can be reduced.

In this case, a sputtering method, which is a vacuum processing method, is used.
By subjecting the surface to a roughening treatment as a layer structure, Ti
The adhesion between the N film and the plating seed layer is improved, and the reliability can be maintained without peeling even if the wiring layer becomes thinner and thinner with miniaturization.

Also in this case, the mechanical strength can be increased as compared with the case where the epoxy resin is used alone, while the film adhesion can be increased as compared with the case where the polyimide resin is used alone.

The embodiments of the present invention have been described above. However, the present invention is not limited to the configuration described in each embodiment, and various modifications are possible. For example, in the description of each embodiment, a spin coating method is used as a coating method of the resin composition, but the coating method is not limited to the spin coating method, and may be a screen printing method, a curtain coating method, or a roll coating method. May be used.

In the step of irradiating a laser beam for forming a via hole, a carbon dioxide gas laser, an excimer laser, a YAG laser, or the like may be used.

In the first embodiment, a polyether sulfone resin which is thermoplastic and has excellent heat resistance and excellent mechanical strength is used as the hard-to-roughen resin. The resin is not limited to the resin, and a polyetherimide resin that is the same thermoplastic resin, for example, ULTEM (trade name, manufactured by GE Plastics Japan) may be used.

In the second embodiment, a polyimide resin which is thermosetting and has excellent heat resistance and excellent mechanical strength is used as the hard-to-roughen resin, but is limited to the polyimide resin. Instead, a polybenzoxazole resin which is the same thermosetting resin may be used. In this case, the curing temperature is 200 ° C.
It is preferable that the curing temperature is 200 ° C. or lower by adding a catalyst to a commercially available product.

The heat resistance of these thermoplastic resins or thermosetting resins is resistance to the process temperature in the manufacturing process and the temperature at the time of using the circuit board. C. or higher, and the thermal decomposition onset temperature is preferably 300 C. or higher.

The mechanical strength is a film strength that can withstand the stress in the case of a multilayer structure.
It is preferable that the tensile elongation at break is 0% or more and the tensile elongation at break is 10% or more.

In each of the above embodiments, N-methylpyrrolidone is used as a solvent for preparing the resin composition. However, the solvent is not limited to N-methylpyrrolidone, and is not limited to N-methylpyrrolidone. Other organic solvents may be used.

Further, in each of the above embodiments, a bisphenol A type epoxy compound which is particularly suitable as a roughening resin is used. However, the present invention is not limited to the bisphenol A type epoxy compound, and a glycidyl ether type ( Tetraphenylolethane type, phenol novolak type, cresol novolak type), glycidyl ester type (hexahydrophthalic anhydride type, dimer acid type), mixed type (aminophenol type, oxybenzoic acid type), alicyclic type, etc. Can be used alone or as a mixture.

In each of the above embodiments, a novolak-type phenol resin is used as a curing agent for the epoxy resin. However, the present invention is not limited to the novolak-type phenol resin. A resin obtained by reacting an unsaturated carboxylic acid with a resin and further adding a polybasic acid anhydride may be used.In any case, a phenolic compound,
A cresol-based compound or a compound having a carboxyl group can be used.

An acid anhydride, an amine or the like may be used in combination with such a curing agent. For example, methylhexahydrophthalic anhydride, m-phenylenediamine,
4'-Amino diphenylene sulfone, BF ₃ monomethylamine can be used dicyandiamide.

The epoxy resin as the hard-to-roughen resin is a thermoplastic resin, ie, a solvent-soluble resin when the lower hard-to-roughy resin layer is a thermoplastic resin as in the first embodiment. It is necessary to use a non-solvent type epoxy resin or an epoxy resin containing only a specific solvent that does not dissolve the lower hard-roughening resin layer in order to not dissolve the lower hard-roughening resin layer in the resin coating process. is there.

Although not particularly mentioned in the above embodiments, various additives are added to the resin composition in order to improve the coatability of the hard-to-roughened resin layer or the easily-hardened resin layer. For example, a moisture-resistant pigment such as silica, alumina and aerosil, a coloring pigment such as phthalocyanine, an antifoaming agent composed of silicone and a fluorine-based compound, a leveling agent, and an antioxidant may be added.

In the third embodiment, the wiring layer is formed by the electrolytic plating method using the plating frame. However, the wiring layer is formed by the so-called CMP (chemical mechanical polishing) method. It is a good thing. In this case, a groove for a wiring layer is formed in an interlayer insulating film having a two-layer structure, the groove and the via hole are filled with a Cu electrolytic plating layer via a barrier layer and a plating seed layer, and unnecessary portions are removed by a CMP method. It is sufficient that a finer wiring pattern can be formed.

In each of the above embodiments, each wiring layer is formed by a Cu electrolytic plating layer.
It is not limited to the u electrolytic plating layer, but may be constituted by an Au electrolytic plating layer or a Ni electrolytic plating layer.

Here, the detailed features of the present invention will be described with reference to FIG. 1 again. See FIG. 1 (Supplementary Note 1) The interlayer insulating film 4 is made of the hard-to-rough resin layer 2 and the rough-hard resin layer 3 that covers the surface of the hard-rough resin layer 2.
And a multi-layer circuit board.
(1) (Supplementary note 2) The multilayer circuit board according to Supplementary note 1, wherein the hardly-roughening resin is a thermoplastic resin. (2) (Supplementary note 3) The multilayer circuit board according to supplementary note 2, wherein the thermoplastic resin is either polyether sulfone or polyetherimide. (Supplementary Note 4) The multilayer circuit board according to supplementary note 1, wherein the hard-to-roughening resin is a thermosetting resin. (3) (Supplementary note 5) The multilayer circuit board according to supplementary note 4, wherein the thermosetting resin is one of polyimide and polybenzoxazole. (Supplementary Note 6) The multilayer circuit board according to any one of Supplementary Notes 1 to 5, wherein the easily roughening resin is an epoxy resin. (4) (Supplementary note 7) The multilayer circuit board according to any one of Supplementary notes 1 to 6, wherein a plating seed layer 5 made of an electroless plating film is provided on the surface of the easily roughening resin. (Supplementary Note 8) The interlayer insulating film 4 is made of the hard-to-rough resin layer 2 and the rough-hard resin layer 3 that covers the surface of the hard-to-rough resin layer 2.
And a semiconductor integrated circuit device. (5)

[0074]

According to the present invention, the interlayer insulating film is formed by the two-layer structure of the hard-roughening resin layer and the rough-hardening resin layer which coats the surface of the hard-roughening resin layer. It is possible to ensure both mechanical strength and the formation of a plating seed layer by electroless plating, thereby making it possible to manufacture a multilayer wiring circuit board capable of high-density mounting at low cost. This greatly contributes to cost reduction and high performance of portable electronic devices and the like.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process of the build-up multilayer wiring structure according to the first embodiment of the present invention up to a certain point;

FIG. 3 is an explanatory diagram of a manufacturing process of the build-up multilayer wiring structure according to the first embodiment of the present invention after FIG. 2;

FIG. 4 is an explanatory diagram of a build-up multilayer wiring structure according to a second embodiment of the present invention.

FIG. 5 is an explanatory diagram of a manufacturing process of a conventional build-up multilayer wiring structure up to a certain point.

FIG. 6 is an explanatory diagram of a manufacturing process of the conventional build-up multilayer wiring structure after FIG. 5;

FIG. 7 is an explanatory diagram of a problem of a conventional build-up multilayer wiring structure.

FIG. 8 is an explanatory diagram of a problem of another build-up multilayer wiring structure.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 substrate 2 hard-to-rough resin layer 3 easy-rough resin layer 4 interlayer insulating film 5 plating seed layer 6 wiring layer 11 printed board 12 hard-to-rough resin layer 13 easy-rough resin layer 14 interlayer insulating film 15 laser Light 16 Via hole 17 Plating seed layer 18 Plating frame 19 Wiring layer 20 Wiring layer 21 Rough-hardening resin layer 22 Easy-roughening resin layer 23 Second interlayer insulating film 24 Plating seed layer 25 Second wiring layer 26 Second wiring layer 27 Rough hardening resin layer 28 Rough hardening resin layer 29 Third interlayer insulating film 30 Plating seed layer 31 Third wiring layer 32 Third wiring layer 33 Hard roughening resin layer 34 Easy roughening resin layer 35 4 interlayer insulating film 36 hard-to-rough resin layer 37 hard-to-rough resin layer 38 hard-to-rough resin layer 39 hard-to-rough resin layer 41 printed circuit board 42 interlayer insulating film 43 laser light 44 via hole 45 plating Seed layer 46 plating frame 47 wiring layer 48 wiring layer 49 second interlayer insulating film 50 plating seed layer 51 second wiring layer 52 second wiring layer 53 third interlayer insulating film 54 plating seed layer 55 third wiring layer 56 third wiring Layer 57 fourth interlayer insulating film 58 plating seed layer 59 fourth wiring layer 60 fourth wiring layer 61 fifth interlayer insulating film 62 stress crack 63 interlayer insulating film 64 plating seed layer 65 second interlayer insulating film 66 plating seed layer 67 Third interlayer insulating film 68 Plating seed layer 69 Fourth interlayer insulating film 70 Solvent crack 71 Interlayer insulating film 72 Second interlayer insulating film 73 Third interlayer insulating film 74 Fourth interlayer insulating film

 ──────────────────────────────────────────────────続 き Continued on front page F-term (reference) 5E346 AA12 CC08 CC09 CC10 CC32 CC37 DD25 EE31 GG15 HH32 5F033 HH07 HH11 HH13 HH33 JJ01 JJ07 JJ11 JJ13 JJ33 KK07 KK11 KK13 KK33 MM05 MM13 NN06 Q33 Q48 Q15 Q48 RR04 RR25 RR27 SS22 TT03 XX12 XX19 XX24 XX34

Claims (5)

[Claims] 1. A multilayer circuit board, wherein an interlayer insulating film comprises a hard-to-rough resin layer and a rough-hard resin layer covering a surface of the hard-to-rough resin layer. 2. The multilayer circuit board according to claim 1, wherein said hard-to-roughen resin is a thermoplastic resin. 3. The multilayer circuit board according to claim 1, wherein said hard-to-roughen resin is a thermosetting resin. 4. The multilayer circuit board according to claim 1, wherein the easily roughening resin is an epoxy resin. 5. A semiconductor integrated circuit device, wherein an interlayer insulating film comprises a hard-to-rough resin layer and a rough-hard resin layer covering the surface of the hard-to-rough resin layer.