JP2002299624A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

(57) [Summary] PROBLEM TO BE SOLVED: To provide a MOSF switching characteristic at turn-off.
IGBT type semiconductor device close to ET type and method of manufacturing the same
Providing the law. A collector is provided on a back surface and a peripheral side surface of a semiconductor device.
Functions as a data electrode and contacts the EQR electrode 25.
A continuous conductive film 20 is formed. In this configuration,
When a voltage is applied to the emitter electrode film 18 and the conductive film 20,
P⁺Mold layer 10, N ⁻Mold layer 11, P well layer 12, N⁺Type
The current flowing through the diffusion region 13 and the EQR electrode 25,
Channel stopper region 24, N⁻Mold layer 11, P-well layer
12, N⁺Current flowing through the diffusion region 13 is generated, and M
An IGBT type semiconductor device close to the OSFET type is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having an IGBT structure used for a power supply circuit and the like and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, IGBT type semiconductor devices have been widely used as semiconductor devices having both advantages of a bipolar power transistor and a power MOSFET. FIG. 21 is a cross-sectional view showing an IGBT type semiconductor device according to the related art. In the figure, 101 is a semiconductor device, 110 ^{P +} -type layer 111 is the N ^- -type layer, 112 P
Well layer, 113 is an N ⁺ type diffusion region, 114 is a gate insulating film, 115 is a gate electrode film, 116 is a base oxide film, 1
17 is an interlayer insulating film, 118 is an emitter electrode film, 120 is a metal film, and 130 is a silicon substrate.

[0005] A semiconductor device 101 includes a silicon substrate 130.
, A P ⁺ type layer 110, an N ⁻ type layer 111, and a P well layer 112 are formed in layers, and an N ⁺ type diffusion region 113 is formed inside the P well layer 112. On the surface of the silicon substrate 130, a gate insulating film 114 is formed so as to extend over the N ⁻ type layer 111, the P well layer 112, and the N ⁺ type diffusion region 113.
A gate electrode film 115 is formed thereon.

In addition, a base oxide film 116 is formed over a part of the N ⁺ type diffusion region 113, the side surfaces of the gate insulating film 114 and the gate electrode film 115, and the surface of the gate electrode film 115. Over the oxide film 116, an interlayer insulating film 117 is formed. Further, the interlayer insulating film 11
7, an emitter electrode film 118 is formed on the surface of the P well layer 112 and the N ⁺ type diffusion region 113 which are not covered with the interlayer insulating film 117. A metal film 120 serving as a collector electrode is formed on the back surface of the silicon substrate 130, that is, on the surface of the P ⁺ type layer 110. Therefore, this semiconductor device has a P ⁺ type layer 110 and an N ⁻ type layer 1
11, an IGBT is formed by laminating the P well layer 112 and the N ⁺ type diffusion region 113.

In the above configuration, the gate electrode film 115
When a voltage equal to or higher than a predetermined threshold value is applied between the P well layer 112 and the emitter electrode film 118, an inversion layer is formed in a boundary region between the P well layer 112 and the gate insulating film 114, thereby forming a channel. Then, a current flows from the metal film 120 to the emitter electrode film 118 through this channel.

Further, an outline of the above-described method for manufacturing a semiconductor device will be described, focusing on a semiconductor substrate dividing step.
15 to 20 are explanatory diagrams (a) schematically illustrating a method for manufacturing an IGBT type semiconductor device according to the related art, and (f) are schematic diagrams illustrating the outline of a method for manufacturing an IGBT type semiconductor device according to the related art. It is. In these figures, 101 is a semiconductor device, 120 is a metal film, 130 is a silicon substrate, 131 is a wiring pattern, 132 is a grinding wheel, 133 is a holding member,
134 is a blade, and 135 is a groove.

First, as shown in FIG. 15, a P-well layer 112 and the like are formed inside a silicon substrate 130, and a wiring pattern 131 including an emitter electrode film 118 is formed. Next, as shown in FIG. 16, the silicon substrate 130 is ground with a grinding wheel 132 from the back surface, that is, the surface on which the wiring pattern 131 is not formed, so that the silicon substrate 130 has a predetermined thickness.

Next, as shown in FIG. 17, a metal film 120 is formed on the back surface of the silicon substrate 130 by means such as vapor deposition. Further, as shown in FIG. 18, a holding member 133 is attached to the surface of the metal film 120. The holding member 1
As the 33, an adhesive tape is generally used.

Subsequently, as shown in FIG.
At 34, a groove 135 is formed in the silicon substrate 130 along the scribe line to reach the holding member 133. Finally,
As shown in FIG.
The semiconductor devices 101 are separated from each other by peeling them.

By the way, the IGBT type semiconductor device as described above, but turned off by the gate voltage to zero or a negative voltage, from the off N ^- type layer 1
It takes a considerable time before the carriers inside MOSFET 11 are eliminated, and the switching characteristics at turn-off are inferior to those of the MOSFET type.

[0011]

SUMMARY OF THE INVENTION An object of the present invention is to provide an IGBT type semiconductor device whose switching characteristics at the time of turn-off is close to a MOSFET type and a method of manufacturing the same in order to solve the above-mentioned problems. It is.

[0012]

According to another aspect of the present invention, there is provided a semiconductor device having a gate electrode and an emitter electrode formed on one surface. An EQR electrode formed on or near the edge, and a conductive film formed as a collector electrode on at least the other surface and the peripheral side surface of the semiconductor device and short-circuited with the EQR electrode. To do.

Therefore, the semiconductor device according to the present invention is:
Since the configuration is such that the EQR electrode and the conductive film serving as the collector electrode are short-circuited, a part of the current flowing from the conductive film serving as the collector electrode to the emitter electrode can be diverted to the conductive film.

The present invention also provides a semiconductor device having a gate electrode and an emitter electrode formed on one surface.
A channel stopper region exposed on a peripheral side surface of the semiconductor device; and a conductive film formed as a collector electrode on at least the other surface and the peripheral side surface of the semiconductor device and short-circuited with the channel stopper region. It is characterized by the following.

Therefore, the semiconductor device according to the present invention
Since the channel stopper region and the conductive film serving as the collector electrode are short-circuited, part of the current flowing from the conductive film serving as the collector electrode to the emitter electrode can be diverted to the conductive film.

Further, according to the present invention, in a semiconductor device having a gate electrode and an emitter electrode formed on one surface, a semiconductor device is formed by laminating a first conductive layer of a first conductivity type inside the semiconductor device. A second conductive layer formed and formed in a second conductivity type opposite to the first conductivity type;
The semiconductor device is characterized in that it has a conductive film formed on at least the other surface and the peripheral side surface of the semiconductor device as a collector electrode and short-circuited with the second conductive layer.

Therefore, the semiconductor device according to the present invention
Since the second conductive layer and the conductive film serving as the collector electrode are short-circuited, a part of the current flowing from the conductive film serving as the collector electrode to the emitter electrode can be diverted to the conductive film.

According to the present invention, in a method of manufacturing a semiconductor device, a first step of forming a wiring pattern on one surface of a semiconductor substrate, and a step of forming a predetermined depth on the semiconductor substrate along a scribe line on the one surface. A second step of forming a groove of the semiconductor substrate, a third step of attaching a holding member to the one surface of the semiconductor substrate, and grinding the other surface of the semiconductor substrate until the semiconductor substrate reaches the groove. The method includes a fourth step of dividing the substrate for each semiconductor element and a fifth step of forming a conductive film on at least the other surface and the peripheral side surface of the semiconductor element.

Therefore, in the method of manufacturing a semiconductor device according to the present invention, after the semiconductor substrate is divided for each semiconductor element,
Since the conductive film is formed on at least the other surface and the peripheral side surface of the semiconductor element, the conductive film can be simultaneously formed on at least the other surface and the peripheral side surface of the semiconductor element.

Further, the first step may include a process of forming a connection pattern for connecting the EQR electrodes formed on the one surface of the adjacent semiconductor element. According to this configuration, when a groove having a predetermined depth is formed on the semiconductor substrate along the scribe line on one surface, the connection pattern is cut when the groove is formed, and the position of the end of the EQR electrode is changed to the semiconductor element. Can be matched to the edge of Therefore, if a conductive film is subsequently formed on the peripheral side surface of the semiconductor element, the conductive film adhered to the side surface of the semiconductor device also adheres to the end of the EQR electrode, so that the EQR electrode and the conductive film can be easily connected. it can.

Further, a member made of a semiconductor can be used for the holding member. With this configuration, the shape of the member made of the semiconductor is not easily deformed. Therefore, when the semiconductor substrate is attached to the holding member, the region where the holding member is deformed and the wiring pattern of the semiconductor substrate is not formed is formed. The attachment to the holding member can be prevented. Therefore, a gap is formed between the region where the wiring pattern is not formed and the holding member, and the conductive film can be formed in the gap when forming the conductive film. Can also be easily adhered.

In addition, the third step can be performed by applying an adhesive only to a region of the semiconductor substrate on which the wiring pattern is formed. With this configuration, since the region where the wiring pattern is not formed is not bonded to the holding member, a gap is formed between the region where the wiring pattern is not formed and the holding member. Therefore, the conductive film can be formed in the gap when forming the conductive film.

Further, the fifth step may include a process of depositing a metal on at least the other surface and the peripheral side surface of the semiconductor element. Therefore,
A conductive film can be easily formed simultaneously on at least the other surface and the peripheral side surface of the semiconductor element.

Further, the fifth step may include a step of applying metal plating to at least the other surface and the peripheral side surface of the semiconductor element. Therefore, it is easy to simultaneously form the conductive film on at least the other surface and the peripheral side surface of the semiconductor element.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to a first embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a sectional view showing a semiconductor device according to the first embodiment of the present invention. In the figure, 1 is a semiconductor device, 10 is P ⁺
-Type layer 11 is the N ^- -type layer, 12 P-well layer 13 is ^{N +}
Type diffusion region, 14 is a gate insulating film, 15 is a gate electrode film, 16 is a base oxide film, 17 is an interlayer insulating film, 18 is an emitter electrode film, 19 is a connection pattern portion, 20 is a conductive film, 2
1 is a first metal film, 22 is a second metal film, 23 is a peripheral side surface portion,
24 is a channel stopper region, 25 is an EQR electrode film, 2
6 is an oxide film, 27 is an interlayer insulating film, 28 is a main wiring pattern, and 30 is a silicon substrate.

The semiconductor device 1 comprises an N ^- type silicon substrate 3
A P-well layer 12 extending from the surface of the P-well 0 to the inside is formed. In the P well layer 12, an N ⁺ type diffusion region 13 is provided.
Are formed. Further, the P well layer 12 and N ⁺
The mold diffusion region 13 forms one cell with these, and many cells are arranged on the surface of the silicon substrate 30. Further, a P ⁺ type layer 10 is formed on the back side of the N ⁻ type silicon substrate 30. The silicon substrate 30
The portion where the P ⁺ type layer 10, the P well layer 12 and the N ⁺ type diffusion region 13 are not formed becomes the N ⁻ type layer 11. The number of N ⁺ -type diffusion regions 13 formed in one P-well layer 12 is not limited to two, but may be one or three.
More than one may be formed. The P ⁺ -type layer 10 and the P-well layer 12, the N ⁺ -type diffusion region 13, and a channel stopper region 24 to be described later are made of boron (B).
And an impurity such as arsenic (As) is implanted.

Further, a conductive film 20 is formed on the back surface of the silicon substrate 30, that is, on the surface on which the P ⁺ type layer 10 is formed and the peripheral side surface portion 23 of the semiconductor device 1. Conductive film 2
Numeral 0 includes a first metal film 21 made of nickel (Ni) and a second metal film 22 made of silver (Ag). The ends of these metal films are connected to an EQR electrode film 25 described later.
And a channel stopper region 24 described later. Therefore, the conductive film 20 has a function as a collector electrode, and also has a role of short-circuiting the collector electrode, the EQR electrode film 25, and the channel stopper region 24.

The conductive film 20 may be formed so as to completely cover the peripheral side surface portion 23.
It may be formed only on a part of the peripheral side surface portion 23 of the semiconductor device 1 as long as it is electrically connected to the semiconductor device 1. Further, the conductive film 20 may be formed so as to cover part or all of the EQR electrode film 25. Further, the configuration of the conductive film 20 is 2
The number of layers is not limited to one, and may be one or three or more. In addition, the material of the conductive film 20 is not limited to those described above, and other metals such as titanium (Ti), aluminum (Al), and gold (Au) may be used. A non-metallic material may be used.
Also, by combining two or more kinds of metals, 3
It may be composed of a metal film of two or more layers, or a conductive film of two or more layers may be formed by combining a metal and a nonmetal material.

Furthermore, electrical conduction can be reliably ensured.
To connect only to the channel stopper region 24.
You may. In addition, the conductive film 20 is composed of two or more layers.
In this case, only some of the layers are electrically connected to the EQR electrode film 25.
May be connected. Thus, the conductive film 20
The structure of the semiconductor device 1 can be reduced to two layers or three or more layers.
Manufacturing process becomes complicated, but has various electrical characteristics
Semiconductor device can be manufactured. Also semi-conductive
An insulating film is formed on the peripheral side surface portion 23 of the body device 1, and P ⁺Mold layer 1
0, N⁻Conduction with the mold layer 11 and the channel stopper region 24
The electric film 20 may be insulated.

On the silicon substrate 30, a gate insulating film 14 made of a silicon oxide film is formed so as to straddle each of the N ⁻ type layer 11, the P well layer 12, and the N ⁺ type diffusion region 13. ing. A gate electrode film 15 is formed on the gate insulating film 14. Also, N ⁺
On a part of the type diffusion region 13 and the gate electrode film 15,
A base oxide film 16 made of a silicon oxide film is formed, and a PSG (Phoso
-Silicate Glass).

In addition, an emitter electrode film 18 is formed so as to straddle the P well layer 12, the N ⁺ type diffusion region 13, and the interlayer insulating film 17. Also, the emitter electrode film 1
Numeral 8 is formed integrally with a bonding pad (not shown) on the silicon substrate 30 and forms a wiring pattern 31 shown in FIG. 4 described later together with a bonding pad (not shown) connected to the gate electrode film 15.

Further, near the surface of the end of the silicon substrate 30
When the semiconductor device 1 is energized, N ⁻Diffusion in mold layer 11
That the depletion layer reaches the edge of the silicon substrate 30.
N to prevent⁺⁺Channel strike with the characteristics of
A wrapper region 24 is formed. Also, the channel stopper
On the region 24, a part of the channel stopper region 24 is covered.
An oxide film 26 made of a silicon oxide film is formed
ing. Further, a layer made of PSG is formed on the oxide film 26.
An inter-layer insulating film 27 is formed. In addition, the channel strike
So as to extend over the stopper region 24 and the interlayer insulating film 27, and
It is separated from the emitter electrode film 18 to prevent the depletion layer from spreading.
EQR (Equi-potential Rin)
g) The electrode film 25 is formed. The P well layer 12
Gas (not shown) is provided between the
The depletion layer is formed when electricity is supplied.
It has the function of expanding along the surface of the recon board 30.

As described above, the P ⁺ type layer 10 and the N ⁻ type layer 1
1, P well layer 12 and N ⁺ type diffusion region 13
An IGBT type is formed by joining PN. Also,
The conductive film 20 includes the channel stopper region 24 and the EQR
The P well layer 12, the N ⁺ -type diffusion region 13 and the channel stopper region 24
The MOSFET type is formed by forming an N junction. Therefore, the semiconductor device 1 has an IGBT type configuration and also has a MOSFET type configuration.

In the above configuration, when a voltage equal to or higher than a predetermined threshold is applied between the gate electrode film 15 and the emitter electrode film 18, the gate insulating film of the P well layer 12 is formed in the same manner as in the conventional IGBT type semiconductor device. An inversion layer is formed in a boundary region with the film 14 to form a channel. Therefore, a current flows from the conductive film 20 to the emitter electrode film 18 through the P ⁺ type layer 10, the N ⁻ type layer 11, the P well layer 12, and the N ⁺ type diffusion region 13. However, the semiconductor device 1
Also has a MOSFET-type configuration, and at the same time, passes through the channel stopper region 24 or the EQR electrode film 25 via the conductive film 20 formed on the peripheral side surface portion 23 of the semiconductor device 1. N ^- type layer 1
1. A route for shunting to the emitter electrode film 18 through the P well layer 12 and the N ⁺ type diffusion region 13 also occurs. In addition,
A small amount also flows from the conductive film 20 to the N ⁻ type layer 11.

Further, the gate electrode film 15 and the emitter electrode
When the voltage applied to the membrane 18 is set to zero or a negative voltage, N⁻Type
Carriers inside the layer 11 are eliminated toward the conductive film 20.
At the same time, it is also removed to the channel stopper region 24.
You. In particular, the voltage between the conductive film 20 and the emitter electrode film 18
When the pressure is low, for example, 0.5V or less,
Conductive film 20 and N⁻V of Schottky junction with mold layer 11_F
And the size of N⁻P of the mold layer 11 and the P well layer 12
V at N junction_FDue to the size of most current
From the conductive film 20 to the channel stopper region 24 or
Channel stopper region 24 through EQR electrode film 25,
N⁻Mold layer 11, P well layer 12 and N ⁺Diffusion area 1
3 will flow.

Accordingly, when the semiconductor device 1 is turned off, the function of the MOSFET type is exhibited well, and the fall time of the tail current, that is, the current of a lower value after the turn-off, is lower than that of the IGBT type semiconductor device according to the prior art. It has the feature that the time for which it keeps flowing like a tail can be shortened.

Next, the manufacturing process of the semiconductor device according to the first embodiment of the present invention will be described. 4 to 8
3A is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present invention, and FIG. 4E is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present invention. )
It is. In these figures, 10 is a semiconductor device, 20 is a conductive film, 23 is a peripheral side surface portion, 28 is a main wiring pattern, 30 is a silicon substrate, 31 is a wiring pattern, 32 is a grinding wheel,
33 is a holding member, 34 is a blade, and 35 is a groove.

First, as shown in FIG.
0, a P ⁺ -type layer 10, a P-well layer 12, an N ⁺ -type diffusion region 13, a channel stopper region 24, and the like, and a gate insulating film 14, a gate electrode film 15, a base oxide film 16, an interlayer insulating film 17, an emitter electrode film 18, an oxide film 26, an interlayer insulating film 27, an EQR electrode film 25 and the like are formed. At the end of these formations, the surface of the silicon substrate 30 includes a main wiring pattern 28 such as an emitter electrode film 18 and a bonding pad and an EQR electrode film 25 for each semiconductor device to be separated in a process described later. The wiring pattern 31 is formed. In a portion where the wiring pattern between the main wiring patterns 28 is not formed,
In order to protect the portion, it is preferable to form a resin film such as polyimide.

Next, as shown in FIG. 5, the silicon substrate 30 is half-cut along a scribe line with a blade 34 to form a groove 35. Subsequently, as shown in FIG. 6, a holding member 33 is attached to the surface of the silicon substrate.
At this time, the adhesive is preferably applied as follows. FIG. 9 is an explanatory diagram showing a method of applying the adhesive.
(A) is a cross-sectional view showing a first application method, (B) is a cross-sectional view showing a second application method, and (C) is a cross-sectional view showing a third application method. In the figure, 36 is an adhesive. Other symbols are the same as those in FIG.

As shown in FIG. 9A, as a method of applying the adhesive, the silicon substrate 30 is attached to the holding member 33 after the adhesive is applied to the entire surface of the holding member 33. As another method, as shown in FIG. 9B, an adhesive may be applied only to the wiring pattern 31 so that only the wiring pattern 31 and the holding member 33 are bonded. In this case, it is preferable that the outer peripheral surface of the EQR electrode film 25 is not covered with the adhesive. This is because, in a step described later, the conductive film 20 is formed and the EQR electrode film 25 and the conductive film 2 are formed.
0, when an adhesive is attached to the outer peripheral surface of the EQR electrode film 25, the adhesive is interposed between the EQR electrode film 25 and the conductive film 20 and they are not electrically connected. This is because it is assumed. If a sufficient adhesive strength can be obtained, an adhesive may be applied only to the main wiring pattern 28 excluding the EQR electrode film 25, as shown in FIG. 9C. According to the method shown in FIGS. 9B and 9C, the application process of the adhesive becomes more complicated than that shown in FIG. 9A, but the adhesive is not applied to unnecessary portions. It is possible to more reliably connect the EQR electrode film 25 and the conductive film 20 electrically.

The holding member 33 is preferably made of a hard material such as aluminum nitride (AlN), silicon (Si), or a mixture of metal and resin.
The reason for this is that, similarly to the case described above, when a highly flexible material such as a resin sheet is used, the holding member 33 adheres so as to cover the outer peripheral surface of the EQR electrode film 25. This is because the electrode film 25 and the conductive film 20 are not electrically connected.

Next, as shown in FIG.
0 is ground with a grinding wheel 32 from the back surface, that is, the surface on which the wiring pattern 31 is not formed, so that the silicon substrate 30 has a predetermined thickness. At this time, the groove 35 is exposed on the back surface side, and the silicon substrate 30 is divided for each semiconductor device.

Subsequently, as shown in FIG. 8, a conductive film 20 is formed on the back surface and the peripheral side surface 23 of the semiconductor device 1 by evaporating a metal. At this time, first, the first metal film 21 is formed by evaporating nickel, and then the second metal film 22 is formed by evaporating silver. FIG.
Although the state where the conductive film 20 is connected to the end face of the EQR electrode film 25 has been described, the conductive film 20 may cover a part or the whole of the EQR electrode film 25. Further, one or both of the first metal film 21 and the second metal film 22 may be formed by a plating method. Also, for example,
When a conductive organic material is used instead of the second metal film 22, the conductive organic material may be applied on the first metal film 21. Thereafter, the semiconductor device 1 is moved to the holding member 3.
By peeling off from the semiconductor device 3, the manufacturing process of the semiconductor device 1 is completed.

According to the above process, after the silicon substrate 30 is half-cut, the back surface is ground to divide the silicon substrate 30, and subsequently the metal is deposited to form the conductive film 20, so that the conductive film 20 is formed. 20 can be easily formed on the back surface and the peripheral side surface 23 of the semiconductor device.

Next, another manufacturing process of the semiconductor device according to the first embodiment of the present invention will be described. Figure 10
FIGS. 14A to 14C are cross-sectional views illustrating manufacturing steps of a semiconductor device according to the second embodiment of the present invention, and FIGS. (E). In these figures, 19 is a connection pattern portion,
Reference numeral 29 denotes a peripheral pattern. All other symbols are the same as those used in FIGS.

First, as shown in FIG. 10, a P well layer 12, an N ⁺ type diffusion region 13, a channel stopper region 24, and the like are formed inside a silicon substrate 30. Further, a gate insulating film 14, a gate electrode film 15, a base oxide film 16, an interlayer insulating film 17, an emitter electrode film 18, an oxide film 26, an interlayer insulating film 27, an EQR electrode film 25, and the like are sequentially formed. At this time, a connection pattern portion 19 for connecting the adjacent EQR electrode films 25 is provided, and the adjacent EQR electrode films 25 are formed.
Each of them and the connection pattern portion 19 are integrally formed as a peripheral pattern 29.

Next, as shown in FIG.
Then, the silicon substrate 30 is half-cut along scribe lines to form grooves 35. At this time, the connection pattern portion 19 of the peripheral pattern 29 is cut off, and the end of the EQR electrode film 25 appears on the side wall of the groove 35. Next, FIG.
As shown in (2), the holding member 33 is attached to the surface of the silicon substrate. The method of applying the adhesive is the same as that shown in FIG.

Next, as shown in FIG. 13, the silicon substrate 30 is ground with a grinding wheel 32 from the back surface, that is, the surface on which the wiring pattern 31 is not formed, and the silicon substrate 30 is divided for each semiconductor device. At this time, the EQR electrode film 25
Of the semiconductor device 1 coincides with the peripheral side surface of the semiconductor device 1. Further, as shown in FIG. 14, a first metal film and a second metal film 22 are formed by depositing nickel and silver to form a conductive film 20. According to the above steps, as in the case of the first embodiment, the conductive film 20 can be easily formed, and the connection between the conductive film 20 and the EQR electrode film 25 can be easily performed. .

When the EQR electrode film 25 is formed as shown in FIG. 1, when the first metal film 21 and the second metal film 22 are deposited, the metal adheres near the end face of the EQR electrode film 25. It may be difficult. However, in this manufacturing process, since the end surface of the EQR electrode film 25 coincides with the peripheral side surface of the semiconductor device 1 as in an EQR electrode film 25 shown in FIG.
Firmly adhere to the end face of Also in this manufacturing process, the conductive film 20 may be formed by a plating method. Further, the conductive film 20 may be formed so as to cover part or all of the EQR electrode film 25.

Next, a semiconductor device according to a second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 2 is a sectional view showing a semiconductor device according to a second embodiment of the present invention. All the reference numerals in the figure are the same as those used in FIG. In the semiconductor device 1 of FIG. 2, without forming the ^{P +} -type layer 10, N ^- -type layer 11, P-well layer 12
And the N ⁺ type diffusion region 13 forms an NPN junction. The conductive film 20 and the N ^- Focusing the mold layer 11 and the bonding, they constitute a Schottky diode, the conductive film 20, N ^- by type layer 11, P-well layer 12 and the ^{N +} -type diffusion region 13 , And IGBT type. In addition, the EQR electrode film 2
5 is formed by a method described later so that the position of the end face in the vertical direction coincides with the position of the end face of the silicon substrate 30. All other configurations are shown in FIG.
Is the same as that shown in FIG.

In the second embodiment of the present invention, the same operation and effect as those in the first embodiment of the present invention are obtained.
Since the conductive film 20 has both the function of the collector electrode and the function of the P ⁺ -type layer 10 in the first embodiment, it is possible to reduce the number of manufacturing steps as compared with the first embodiment of the present invention.

Further, semiconductor devices according to third and fourth embodiments of the present invention will be described in detail with reference to the drawings. FIG. 3 is a sectional view showing a semiconductor device according to the third and fourth embodiments of the present invention, and FIG. 3A is a sectional view showing a semiconductor device according to the third embodiment of the present invention. ,
(B) is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention. All the reference numerals in the figure are the same as those shown in FIG.

In the semiconductor device according to the first and second embodiments of the present invention, the conductive film 20 and the EQR electrode film 2
5, the conductive film 20 is provided on all or a part of the peripheral side surface portion 23 of the semiconductor device 1, and the EQR electrode film 25 is provided.
It is also possible to adopt a configuration that is not connected to the network. The semiconductor device according to the third embodiment of the present invention is as shown in FIG. 3A, and the parts not shown are the same as those of the semiconductor device according to the first embodiment of the present invention. Is the same. In this embodiment, the conductive film 20 is formed up to the channel stopper region 24, and is not connected to the EQR electrode film 25. Therefore, although the reliability of the connection between the conductive film 20 and the channel stopper region 24 is inferior to the semiconductor devices according to the first and second embodiments, the conductive film 20 is not connected to the EQR electrode film 25. Therefore, management of the manufacturing process is facilitated.

The semiconductor device according to the fourth embodiment of the present invention is as shown in FIG. 3B, and the parts not shown are the same as those of the first embodiment of the present invention. Is the same as the semiconductor device according to the first embodiment. In this embodiment,
The conductive film 20 is formed up to the N ⁻ type layer 11 and
The QR electrode film 25 and the channel stopper region 24 are not connected. In this embodiment, the conductive film 2
0 is formed up to the channel stopper region 24, and the EQR electrode film 25 and the channel stopper region 24 are formed.
And not connected. Therefore, the conductive film 20
There is no current flowing to the QR electrode film 25 and the channel stopper region 24, and only a small current flowing from the conductive film 20 to the N ⁻ type layer 11. Therefore, the conductive film 20 is
The first and second electric paths for forming the OSFET are as follows.
And it is inferior to the semiconductor device according to the third embodiment.
However, since the formation range of the conductive film 20 is narrow, management of the manufacturing process is easiest.

[0055]

As described above, according to the present invention, since the conductive film is formed on the back surface and the peripheral side surface of the semiconductor device and connected to the EQR electrode, the present invention has both IGBT type and MOSFET type configurations. A semiconductor device can be formed;
It is possible to provide an IGBT type semiconductor device whose switching characteristics at the time of turn-off is close to a MOSFET type and a method of manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a semiconductor device according to third and fourth embodiments of the present invention, and FIG. 3A is a cross-sectional view showing a semiconductor device according to a third embodiment of the present invention; ,
(B) is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a cross-sectional view illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention;

FIG. 6 is a cross-sectional view for explaining a manufacturing step of the semiconductor device according to the first embodiment of the present invention;

FIG. 7 is a sectional view (d) illustrating a step of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a sectional view (e) illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention;

FIG. 9 is an explanatory view showing a method of applying an adhesive, and FIG.
FIG. 3 is a cross-sectional view showing a first coating method, (B) is a cross-sectional view showing a second coating method, and (C) is a cross-sectional view showing a third coating method.

FIG. 10 is a sectional view illustrating a manufacturing process of a semiconductor device according to a second embodiment of the present invention;

FIG. 11 is a sectional view illustrating a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 12 is a sectional view (c) illustrating a step of manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 13 is a sectional view (d) illustrating a step of manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 14 is a sectional view (e) illustrating a step of manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 15 is an explanatory view (a) showing an outline of a method for manufacturing an IGBT type semiconductor device according to a conventional technique.

FIG. 16 is an explanatory view (b) showing an outline of a method for manufacturing an IGBT-type semiconductor device according to a conventional technique.

FIG. 17 is an explanatory view (c) showing an outline of a method for manufacturing an IGBT type semiconductor device according to a conventional technique.

FIG. 18 is an explanatory view (d) illustrating an outline of a method for manufacturing an IGBT-type semiconductor device according to the related art.

FIG. 19 is an explanatory view (e) schematically showing the method of manufacturing the IGBT type semiconductor device according to the conventional technique.

FIG. 20 is an explanatory view (f) schematically showing the method of manufacturing the IGBT type semiconductor device according to the conventional technique.

FIG. 21 is a cross-sectional view illustrating an IGBT type semiconductor device according to a conventional technique.

[Brief description of the code]

1 semiconductor device 10 P ⁺ -type layer 11 N ^- -type layer 12 P-well layer 13 N ⁺ -type diffusion region 14 a gate insulating film 15 gate electrode film 16 underlying oxide film 17 interlayer insulating film 18 emitter electrode film 19 connecting pattern 20 conductive Reference Signs List 21 first metal film 22 second metal film 23 peripheral side surface portion 24 channel stopper region 25 EQR electrode film 26 oxide film 27 interlayer insulating film 28 main wiring pattern 29 peripheral pattern 30 silicon substrate 31 wiring pattern 32 grinding wheel 33 holding member 34 blade 35 Groove 36 Adhesive 101 Semiconductor device 110 P ⁺ type layer 111 Gate electrode film 112 P well layer 113 N ⁺ type diffusion region 114 Gate insulating film 115 Gate electrode film 116 Base oxide film 117 Interlayer insulating film 118 Emitter electrode film 120 Metal film 130 Silicon substrate 131 arrangement Pattern 132 grinding wheel 133 holding member 134 blade 135 grooves

Claims (9)

[Claims] 1. A semiconductor device having a gate electrode and an emitter electrode formed on one surface, an EQR electrode formed on or near an edge of the one surface of the semiconductor device; A semiconductor device comprising: a collector electrode formed on the other surface and a peripheral side surface; and a conductive film short-circuited with the EQR electrode. 2. A semiconductor device having a gate electrode and an emitter electrode formed on one surface, a channel stopper region formed to be exposed on a peripheral side surface of the semiconductor device, and at least the other surface of the semiconductor device. And a conductive film formed on the peripheral side surface as a collector electrode and short-circuited with the channel stopper region. 3. A semiconductor device having a gate electrode and an emitter electrode formed on one surface, wherein the semiconductor device is formed inside the semiconductor device by being laminated on a first conductive layer of a first conductivity type. A second conductive layer formed of a second conductivity type opposite to the first conductivity type; a second conductive layer formed as a collector electrode on at least the other surface and a peripheral side surface of the semiconductor device; And a conductive film formed by short-circuiting. 4. A first step of forming a wiring pattern on one surface of a semiconductor substrate, and a second step of forming a groove of a predetermined depth in the semiconductor substrate along a scribe line on the one surface. A third step of attaching a holding member to the one surface of the semiconductor substrate; and a fourth step of grinding the other surface of the semiconductor substrate until the groove reaches the groove and dividing the semiconductor substrate for each semiconductor element. A method of manufacturing a semiconductor device, comprising: forming a conductive film on at least the other surface and the peripheral side surface of the semiconductor element. 5. The semiconductor device according to claim 4, wherein the first step includes a process of forming a connection pattern for connecting EQR electrodes formed on the one surface of the adjacent semiconductor element. A method for manufacturing a semiconductor device. 6. The method for manufacturing a semiconductor device according to claim 4, wherein a member made of a semiconductor is used for the holding member. 7. The semiconductor device according to claim 4, wherein the third step is performed by applying an adhesive only to a region of the semiconductor substrate on which the wiring pattern is formed. The manufacturing method of the semiconductor device described in the above. 8. The semiconductor device according to claim 4, wherein the fifth step includes a process of depositing a metal on at least the other surface and a peripheral side surface of the semiconductor element. The manufacturing method of the semiconductor device described in the above. 9. The semiconductor device according to claim 4, wherein the fifth step includes a step of performing metal plating on at least the other surface and the peripheral side surface of the semiconductor element. The manufacturing method of the semiconductor device described in the above.