JP2002289844A - Field effect transistor - Google Patents

Abstract

(57) Abstract: Provided is a MOS transistor having a gate stack having a high dielectric constant and good interface characteristics. SOLUTION: A conductive oxide is formed on a channel using a Si semiconductor substrate 1 as a gate electrode 4, an interface reaction layer between SiO2, silicate, metal oxide or conductive oxide and Si, an interface reaction layer with SiO2. A field effect transistor, wherein one kind selected from the group consisting of: is used for the gate insulating layer 3. Desirably, the conductive oxide contains at least one selected from alkaline earths or rare earths such as SrRuO3, and has a perovskite structure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a semiconductor device, particularly an insulated gate field effect transistor.

[0002]

2. Description of the Related Art Higher speed and higher integration of LSI have been promoted by miniaturization of MOS devices according to a scaling law. This has made it possible to simultaneously maintain the characteristics of the element at the time of miniaturization and improve the performance by simultaneously reducing the dimensions of the MOS device such as the insulating film and the gate length in the height direction and the lateral direction. . According to the scaling law, MO
S-transistors are steadily miniaturizing.
The next-generation MOS transistors from 2000 onward include SiO
A thickness of 2 nm or less is required for the two-gate insulating film. However, this film thickness region is a thickness at which the tunnel current starts to flow directly, so that the leakage current cannot be suppressed, and problems such as an increase in power consumption cannot be avoided. Therefore, it is necessary to use a material having a dielectric constant higher than that of SiO 2 and increase the physical film thickness to suppress the leak current while suppressing the equivalent silicon oxide film thickness to 2 nm or less. In addition, since the MOS transistor is a field-effect transistor (FET) while suppressing the leakage current, the Si interface characteristics are particularly important. Therefore, an insulating film gate having a high dielectric constant and capable of maintaining good interface characteristics is required.

In recent years, a so-called high-dielectric (high-dielectric) material has been used in place of a SiO2 or silicon nitride film as a gate insulating film and a metal oxide having a higher dielectric constant is used as the gate insulating film.
K) Research on gate insulating films has been actively conducted. The inventors have already deposited oxides such as ZrO2 on Si,
A new gate insulating film using an interface reaction layer generated between i and this oxide as a gate insulating film has been proposed.
In this case, when the interface reaction layer is used as a gate insulating film, it is necessary to remove an oxide layer such as ZrO2 deposited on the upper portion and then deposit a gate electrode, which is complicated in terms of the LSI process configuration. There was a problem of becoming.
Further, when depositing a gate electrode made of a metal or a semiconductor on the interface reaction layer, a low dielectric constant layer may be formed at the interface in some cases, which may cause a problem that the characteristics of the gate stack deteriorate. This problem is a concern not only for the high dielectric gate insulating film using the interface reaction layer but also for other so-called High-k gate insulating films in general.

[0004]

As described above, the LSI
In order to advance the miniaturization while maintaining and improving the performance with the aim of high integration of the semiconductor, forming an insulating film that has a high dielectric constant and good interface characteristics and a low dielectric constant layer between it and the insulating film A gate electrode is not required. Furthermore, a gate stack configuration and a process that can easily form a gate stack composed of the insulating film and the gate electrode are required. The present invention has been made in view of such a demand, and has as its object to provide a field effect transistor capable of easily achieving a gate stack having excellent characteristics.

[0005]

According to the present invention, a conductive oxide containing an alkaline earth metal or a rare earth metal such as SrRuO3 or (La, Sr) CoO3 is used as a gate electrode. Is used. Also,
As the gate insulating film, it is desirable to use a reactive layer of Si or a thin SiO2 provided on Si and the above conductive oxide. Further, the inventors deposit these oxides on Si or Si provided with a thin SiO2 film, thereby forming a highly insulating reaction layer containing alkaline earth or rare earth ions, and forming a dielectric layer of the reaction layer. Rate is SiO
It has been found that a good gate stack can be easily formed because the number is much larger than that of the gate stack No. 2.

[0006] It can be seen that the constituent elements of the conductive oxide deposited on the upper portion are taken into the interface reaction layer and become silicate, so that a high dielectric constant and good insulating properties are obtained. Therefore, when a conductive oxide composed only of an element that is difficult to form a silicate, such as RuO2, is used as the gate electrode, a good interface between the gate insulating film and the gate electrode causes a higher driving force than a normal metal gate. However, the effect of increasing the dielectric constant of the insulating film by silicate formation cannot be expected.

In general, it is considered that an electric field penetrates to the electrode side at the dielectric / electrode interface, and an effective dielectric characteristic of an ultra-thin dielectric film such as an LSI memory capacitor or a gate insulating film is not considered. (CTJ. Welser Transaction on Electron De)
vices, 44, (4) 1999). Therefore, by using a conductive oxide as an electrode of a thin-film dielectric, the penetration of an electric field into the electrode as described in the above paper can be reduced, and the effective dielectric film thickness can be reduced (M. Izuha et al.) , Jpn.J. App
l. Phys., 36 5866, 1997. M. Izuha et al,
Jpn. J. Appl. Phys. Lett., 70, 1405, 1997).

In the gate stack according to the present invention, an interface reaction layer having a high dielectric constant is formed by the reaction between the electrode material and Si or SiO2 or another dielectric film, and the effect of reducing the penetration of an electric field into this electrode is obtained. A gate stack having good characteristics can be produced by obtaining at least one of various effects such as a good interface without generation of a low dielectric constant layer at the interface between the dielectric and the electrode.

Further, in certain conductive oxides,
By changing the composition, the electronic state changes and the
A shift in the Ermi level occurs, and from this point the vacuum level
Energy, i.e. work function
You. By utilizing this property, the gate stack threshold
Control the voltage value to a value suitable for device operation.
It becomes possible. When such threshold voltage control is performed, S
rRu_(1-x)Ti _xO₃, La_(1-x)Sr_xC
oO₃Use a material such as
It is not possible to obtain the desired threshold voltage by selecting
come.

In the field effect transistor having the gate stack according to the present invention, it is possible to use only the above-mentioned conductive oxide containing rare earth or alkaline earth as the gate electrode.
It is also possible to laminate such a cap layer. By using such a cap layer, it is possible to suppress decomposition and evaporation of SrRuO3 and the like when heat treatment is performed with a forming gas containing hydrogen or the like. Further, the thickness of the conductive oxide used here can be appropriately selected from the range of about 1 nm to 100 nm, and the material used for the cap layer is not only TiN but also TiAlN and Ta.
It is also possible to use a nitride such as N, a high melting point metal such as W or Mo, or a transition metal such as Ti.

According to the present invention, a gate stack having excellent interface characteristics between Si and an insulator and between an insulator and a gate electrode can be easily obtained.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a cross-sectional structure of an n-channel MOS transistor according to a basic embodiment of the present invention. 1 is a p-type silicon substrate, 2 is an element isolation region, 3 is a gate insulating film, and 4 is a gate electrode of a conductive oxide.
The structure and manufacturing method of the gate electrode and the gate insulating film will be described later. Reference numeral 5 denotes a diffusion layer (source and drain regions) into which an n-type impurity has been introduced. Reference numeral 6 denotes an insulating film (for example, a CVD silicon nitride film) formed on the side wall of the gate electrode 4, and 7 denotes an interlayer insulating film (for example, a CVD silicon oxide film), and a contact hole provided in the interlayer insulating film 7. , An Al wiring 8 is connected to the gate electrode 4 and the source and drain regions 5.

Hereinafter, the above embodiment will be described based on an example.
This will be described in detail. (Embodiment 1) A first embodiment of a conductive oxide gate electrode and a gate insulating film of the present invention applicable to a MOS transistor having the structure shown in FIG. Will be explained.

First, plane orientation (100), specific resistance 4-6
(A groove for element isolation is formed by reactive ion etching on a p-type silicon substrate 11 of cm. Subsequently, an element isolation region 12 is formed by embedding an LP-TEOS film, for example (FIG. 2 ( a)) As an example,
A case where a gate stack is formed using ZrO2 as a gate insulating film and SrRuO3 which is a conductive oxide as a gate electrode will be described. First, the surface of the Si substrate is wet-treated with dilute hydrofluoric acid, and the surface is terminated with hydrogen. Next, this substrate is introduced into a CVD apparatus. The substrate temperature is set to 400 ° C., and the ZrO 2 film 13 is
nm. Subsequently, the substrate is introduced into a sputtering apparatus, and SrRuO3 is used as a target with SrRuO3.
The three films 14 are deposited to a thickness of 20 nm (FIG. 2B). The gate electrode formed in this manner has a very normal interface with the gate insulator, and has an effectively low equivalent film thickness due to the absence of a low dielectric constant layer at the interface, thereby obtaining a transistor having a large driving force. be able to.

As a comparative example, a transistor using TiN for the gate electrode instead of the SrRuO3 gate electrode was prepared. The converted film thickness in this case is 3 nm, and TiN and ZrO
A low dielectric constant layer was formed at the interface of No. 2.

By using the above-described manufacturing method, a gate electrode and a gate insulating film can be manufactured. The silicon oxide film equivalent effective thickness of the gate insulating film manufactured in this example was 1 nm.

In order to fabricate the MOS device as shown in FIG. 1, following the step of fabricating the gate insulating film as shown in FIG.
The rRuO3 / ZrO2 layer is removed, followed by, for example, 45
At 0 ° C. and a pressure of 10 mTorr to 1 atm, a CVD silicon nitride film 6 having a thickness of, for example, 5 to 200 nm is deposited using a mixed gas of a SiH ₄ gas and an NH ₃ gas diluted with a nitrogen gas. Subsequent steps are the same as those of a normal MOS transistor. That is, for example, the acceleration voltage 20
Arsenic ions are implanted at a keV and a dose of 1 × 10 ¹⁵ cm ⁻² to form source / drain regions 5.
Subsequently, the interlayer insulating film 37 is formed on the entire surface by a chemical vapor deposition method.
Is deposited, and a contact hole is opened in this interlayer insulating film. Subsequently, an Al film is deposited on the entire surface by a sputtering method, and the Al film is patterned by reactive ion etching, whereby a MOS transistor having a gate insulating film as shown in FIG. 1 is completed.

Since the MOS transistor thus manufactured has a low interface state and a high mobility of the inversion layer, it was confirmed that good characteristics were obtained. (Embodiment 2) A second embodiment of a gate electrode, a gate insulating film and a method of manufacturing the same according to the present invention applicable to a MOS transistor having a structure as shown in FIG.
This will be described with reference to FIG. First, plane orientation (100),
A groove for element isolation is formed by reactive ion etching on a p-type silicon substrate 21 having a specific resistance of 4 to 6 (cm). Subsequently, for example, an element isolation region 22 is formed by embedding an LP-TEOS film. (FIG. 3A).

As an example, a case where a conductive oxide gate electrode and a gate insulating film are formed by using a sputtering method will be described. First, the surface of the Si substrate 21 is wet-treated with dilute hydrofluoric acid, and the surface is terminated with hydrogen.
Next, this substrate is introduced into a sputtering apparatus. The substrate temperature is set to 500 ° C., and a SrRuO 3 film 24 is deposited to a thickness of 20 nm on the Si substrate 21 using SrRuO 3 as a target. At this time, an interface reaction layer 23 having a thickness of 3 nm is formed between SrRuO3 and Si (FIG. 3B).

This interface reaction layer shows good insulating properties,
Since the interface with Si and the upper interface with SrRuO3 are also good, a fine transistor having excellent characteristics such as a low interface level, a high mobility, and a small gate leak is manufactured by using this as a gate insulating film. can do.

By using the above-described manufacturing method, a gate electrode and a gate insulating film can be manufactured. The silicon oxide film equivalent effective thickness of the gate insulating film manufactured in this example was 1 nm.

In order to fabricate the MOS device as shown in FIG. 1, following the step of fabricating the gate insulating film as shown in FIG.
The rRuO 3 layer is removed, and subsequently, for example, at 450 ° C. and a pressure of 10 mTorr to 1 atm, a CVD silicon nitride film 6 of, for example, 5 to 200 nm is formed using a mixed gas of SiH ₄ gas and NH ₃ gas diluted with nitrogen gas. accumulate.
Subsequent steps are the same as those of a normal MOS transistor. That is, for example, arsenic ions are implanted at an acceleration voltage of 20 keV and a dose of 1 × 10 ¹⁵ cm ⁻² to form the source region / drain region 5. continue,
C to be an interlayer insulating film 37 over the entire surface by chemical vapor deposition
A VD silicon oxide film is deposited, and a contact hole is opened in this interlayer insulating film. Subsequently, an Al film is deposited on the entire surface by a sputtering method, and the Al film is patterned by reactive ion etching, whereby a MOS transistor having a gate insulating film as shown in FIG. 1 is completed.

Since the MOS transistor thus manufactured has a low interface state and a high mobility of the inversion layer, it was confirmed that good characteristics were obtained. (Embodiment 3) A third embodiment of a gate electrode, a gate insulating film and a method of manufacturing the same according to the present invention applicable to a MOS transistor having a structure as shown in FIG.
This will be described with reference to FIG. First, plane orientation (100),
A groove for element isolation is formed by reactive ion etching on a p-type silicon substrate 31 having a specific resistance of 4 to 6 (cm). Subsequently, an element isolation region 32 is formed by embedding, for example, an LP-TEOS film. (FIG. 4A).

As an example, a case where a gate insulating film including a conductive oxide gate electrode and an interface reaction layer is formed by a sputtering method will be described. First, the surface of the Si substrate 31 is wet-processed with dilute hydrofluoric acid, and the surface is terminated with hydrogen.
3 were provided. Next, this substrate is introduced into a sputtering apparatus,
At a substrate temperature of 500 ° C., an SrRuO3 film 35 is formed on the Si substrate 31 by using SrRuO3 as a target.
m. At this time, an interface reaction layer 34 is formed between SrRuO3 and SiO2, and a layer in which Sr is diffused is formed on the upper portion of SiO2 (FIG. 4B).

This interface reaction layer shows good insulating properties,
Since the interface with Si and the upper interface with SrRuO3 are also good, a fine transistor having excellent characteristics such as a small interface level, a high mobility, and a small gate leak is manufactured by using this as a gate insulating film. can do.

By using the above-described manufacturing method, a gate electrode and a gate insulating film can be manufactured. The silicon oxide film equivalent effective thickness of the gate insulating film manufactured in this example was 1.5 nm. FIGS. 5 and 6 show the dielectric characteristics and the leakage current characteristics of the capacitor similarly formed on Si.

In order to fabricate the MOS device as shown in FIG. 1, following the step of fabricating the gate insulating film as shown in FIG.
The rRuO 3 film is removed, and subsequently, for example, at 450 ° C. and a pressure of 10 mTorr to 1 atm, a CVD silicon nitride film 6 of, for example, 5 to 200 nm is formed using a mixed gas of SiH ₄ gas and NH ₃ gas diluted with nitrogen gas. accumulate.
Subsequent steps are the same as those of a normal MOS transistor. That is, for example, arsenic ions are implanted at an acceleration voltage of 20 keV and a dose of 1 × 10 ¹⁵ cm ⁻² to form the source region / drain region 5. continue,
CV which becomes interlayer insulating film 7 on the entire surface by chemical vapor deposition
A D silicon oxide film is deposited, and a contact hole is opened in this interlayer insulating film. Subsequently, A is applied to the entire surface by sputtering.
By depositing an l film and patterning the Al film by reactive ion etching, a MOS transistor having a gate insulating film as shown in FIG. 1 is completed.

The MOS transistor thus manufactured has a low interface state and a high mobility of the inversion layer, and thus it has been confirmed that good characteristics are obtained. (Embodiment 4) A fourth embodiment of a gate electrode, a gate insulating film and a method of manufacturing the same according to the present invention applicable to a MOS transistor having the structure shown in FIG.
This will be described with reference to FIG. First, plane orientation (100),
A groove for element isolation is formed by reactive ion etching on a p-type silicon substrate 41 having a specific resistance of 4 to 6 cm. Subsequently, for example, an element isolation region 42 is formed by embedding an LP-TEOS film. (FIG. 7A).

As an example, a case where a gate electrode and a gate insulating film are formed by using a sputtering method will be described. First, the surface of the Si substrate 41 is wet-treated with dilute hydrofluoric acid, and the surface is terminated with hydrogen.
An SiO2 thermal oxide film 43 having a thickness of nm was provided. Next, this substrate was introduced into a sputtering apparatus, and the substrate temperature was changed to La at 500 ° C.
Using 0.8Sr0.2CoO3 as a target, S
La0.8-Sr0.2-CoO3 film 4 on i-substrate 41
5 is deposited to a thickness of 20 nm. At this time, La0.8-Sr0.
An interface reaction layer 44 is formed between 2-CoO3 and SiO2, and a layer in which Sr is diffused is formed above the SiO2 film 43 (FIG. 7B).

This interface reaction layer shows good insulating properties,
Since the interface with Si and the upper interface with SrRuO3 are also good, a fine transistor having excellent characteristics such as a low interface level, a high mobility, and a small gate leak is manufactured by using this as a gate insulating film. can do. Similarly, La0.5Sr is used as a gate electrode.
Devices using 0.5CoO3 were prepared and their characteristics were compared.

By using the above-described manufacturing method, a gate electrode and a gate insulating film can be manufactured. The silicon oxide film equivalent effective thickness of the gate insulating film manufactured in this example was 1 nm. FIG. 8 shows the dielectric characteristics of the capacitor formed on Si in the same manner. The CV characteristics of the two have different flat bands, and the threshold voltage of the MISFET can be controlled using this characteristic.

This difference is caused by a difference in electronic state between the two kinds of conductive oxides used here. FIG. 9 shows this difference. In general, in a conductive perovskite, its conductivity is controlled by the composition of an insulating substance called a base material, and a state is formed in the band gap of the base material by injecting carriers, and this forms a band to form a ferrite. Having the surface provides metal conductivity.
The energy of the newly generated conductive band and Fermi surface measured from the valence band of the base material changes depending on the composition change, that is, the degree of carrier injection. On the other hand, these substances have a lower carrier concentration than ordinary metals,
Since the screening effect of conduction electrons is weak, the vacuum level of these substances keeps the same energy difference from the valence band of the original base material, in other words, the energy difference between the vacuum level and the Fermi surface, that is, the work function Can be controlled by changing the composition. This La-Sr
In the -Co-O system, when the amount of Sr is small, the work function is large, and the work decreases as the amount of Sr increases, and the flat band potential shown in FIG. 9 changes accordingly.

In order to fabricate the MOS device as shown in FIG. 1, following the step of fabricating the gate insulating film as shown in FIG.
removing the a0.8-Sr0.2-CoO3 layer,
For example, at 450 ° C. and a pressure of 10 mTorr to 1 atm, a CVD silicon nitride film 6 having a thickness of, for example, 5 to 200 nm is deposited using a mixed gas of SiH ₄ gas and NH ₃ gas diluted with nitrogen gas. Subsequent steps are the same as those of a normal MOS transistor. That is, for example, arsenic ions are implanted at an acceleration voltage of 20 keV and a dose of 1 × 10 ¹⁵ cm ⁻² , and the source region / drain region 5
To form Subsequently, a CVD silicon oxide film serving as an interlayer insulating film 7 is deposited on the entire surface by a chemical vapor deposition method, and a contact hole is opened in the interlayer insulating film. Subsequently, an Al film is deposited on the entire surface by a sputtering method, and the Al film is patterned by reactive ion etching, whereby a MOS transistor having a gate insulating film as shown in FIG. 1 is completed.

The MOS transistor thus manufactured has a low interface state and a high mobility of the inversion layer, and thus it has been confirmed that good characteristics have been obtained.

As described above, by using a conductive perovskite as the gate electrode, it becomes possible to control the flat band shift and the threshold voltage of the transistor as in the case of using polysilicon for the gate. Here, an example in which SiO2 or a reaction layer of SiO2 and a conductive oxide is used for the gate insulating film has been described. However, this function can be similarly used when a high dielectric thin film is used for the gate insulating film. is there. (Embodiment 5) A description will be given of a fifth embodiment of the gate electrode, the gate insulating film and the method for manufacturing the same according to the present invention which are applicable to the MOS transistor having the structure shown in FIG. First, plane orientation (100), specific resistance 4-6 (cm)
A groove for element isolation is formed on the p-type silicon substrate 11 by reactive ion etching. Subsequently, for example, an element isolation region is formed by embedding an LP-TEOS film. As an example, a case where a conductive oxide gate electrode and a gate insulating film are formed by a sputtering method will be described. First, the surface of the Si substrate was wet-treated with dilute hydrofluoric acid, and after terminating the surface with hydrogen, a 3.5-nm SiO2 thermal oxide film was provided. Next, this substrate was introduced into a sputtering apparatus, and the substrate temperature was set to 500 ° C. and Sr
Using RuO3 as a target, Sr
RuO3 is deposited to a thickness of 30 nm.

At this time, an interface reaction layer is formed between SrRuO3 and SiO2, and a layer in which Sr is diffused is formed on the upper portion of SiO2. Since this interface reaction layer has good insulating properties and also has a good interface with Si and an upper interface with SrRuO3, the interface reaction layer is used as a gate insulating film to have a small interface state and a high mobility. A fine transistor having excellent characteristics such as low leakage can be manufactured.

The SrRuO thus deposited on the insulating film
When the conductive oxide such as 3 is extremely thin, a high dielectric layer is formed by a reaction with an insulating film, and a gate electrode needs to be further provided thereon. The electrode used here may be a nitride such as TiN or TaN, a metal such as W or Mo, or an ordinary polysilicon electrode.

It is not always necessary to use a conductive oxide such as SRO to modify the upper portion of the insulating film. SrTiO 3 or the like is laminated very thinly and the reaction layer is etched by etching if necessary. It is also possible to remove the other parts and deposit the gate electrode. Also Sr
Alternatively, an element such as La or La may be added to SiO2 by a method such as ion implantation and used as a gate insulating film.

By using the above-described manufacturing method, a gate electrode and a gate insulating film can be manufactured. The silicon oxide film equivalent effective thickness of the gate insulating film manufactured in this example was 1 nm. FIGS. 5 and 6 show the dielectric characteristics and the leakage current characteristics of the capacitor similarly formed on Si. In order to fabricate the MOS device shown in FIG. 1, the SrRuO3 layer other than the gate stack portion is removed by CMP after the above-described gate insulating film fabrication process, and subsequently, for example, at 450 ° C. and a pressure of 10 mTorr. At a pressure of ６1 atm, a CVD silicon nitride film 6 having a thickness of, for example, 5 to 200 nm is deposited using a mixed gas of a SiH ₄ gas and an NH ₃ gas diluted with a nitrogen gas. Subsequent steps are performed using a normal MOS
This is the same as the transistor manufacturing process. That is, for example, an acceleration voltage of 20 keV and a dose of 1 × 10 ¹⁵ cm ⁻²
Then, ion implantation of arsenic is performed to form source / drain regions 5. Subsequently, a CVD silicon oxide film serving as an interlayer insulating film 37 is deposited on the entire surface by a chemical vapor deposition method,
A contact hole is opened in this interlayer insulating film. Subsequently, an Al film is deposited on the entire surface by a sputtering method, and the Al film is patterned by reactive ion etching, whereby an MO having a gate insulating film as shown in FIG.
The S transistor is completed.

Since the MOS transistor thus manufactured has a small interface state and a high mobility of the inversion layer, it was confirmed that good characteristics were obtained.

The following materials can be used as the conductive oxide containing an alkaline earth or a rare earth used in the present invention.

ARuO3, AirO3, ARhO3, A
CoO3, AMnO3, AVO3, ANiO3, ARu
_1-x Ti _x O 3 (A is at least one selected from rare earths or alkaline earths).

Specifically, SrRuO3, BaRuO
3, SrIrO3, SrRhO3, La0.5S
It is desirable to use r0.5CoO3 or the like.

When the work function, that is, the barrier height or the threshold value of the transistor is changed by changing the electronic state of the gate electrode material, the value of _x in SrRu _1-x Ti _x O 3 or La _1-x Sr _x CoO 3 is changed. This can be controlled and done.

Here, the amount of oxygen is a typical value of these substances, but may have oxygen deficiency.

[0047]

As described in detail above, according to the present invention, there is provided a MOS transistor having a high dielectric constant, a low leakage current, a good interface characteristic, and a gate stack capable of easily controlling the threshold voltage. Is done. By using the present invention, further miniaturization and high-speed LSI can be realized, and its industrial value is enormous.

[Brief description of the drawings]

FIG. 1 is a schematic diagram illustrating an example of a MOS transistor according to the present invention.

FIG. 2 is a process cross-sectional view for explaining the MOS transistor manufacturing method (first embodiment) of the present invention.

FIG. 3 is a process cross-sectional view for explaining the MOS transistor manufacturing method (second embodiment) of the present invention.

FIG. 4 is a process sectional view for illustrating the method for manufacturing a MOS transistor according to the present invention (third embodiment).

FIG. 5 is a diagram showing dielectric characteristics of a MIS capacitor according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a leakage characteristic of a MIS capacitor according to a third embodiment of the present invention.

FIG. 7 is a process cross-sectional view for explaining the MOS transistor manufacturing method (fourth embodiment) of the present invention.

FIG. 8 is a diagram showing dielectric characteristics of a MIS capacitor according to a fourth embodiment of the present invention.

FIG. 9 is a diagram showing a change in flat band potential according to a fourth embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Silicon semiconductor substrate 2 ... Element isolation region 3 ... Gate insulating film 4 ... Conductive oxide gate electrode 5 ... Diffusion layer (source / drain region) 6 ... CVD silicon nitride film 7 ... Interlayer insulating film 8 ... Al wiring 11 ... Silicon substrate 12 Element isolation region 13 Gate insulating film 14 Conductive oxide gate electrode

Continued on the front page (72) Inventor Go Go Yamaguchi 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside the Toshiba Yokohama Office (72) Inventor Kenya Sano 1st Kogashi-Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Co., Ltd. Inside the Toshiba R & D Center (72) Inventor Naoko Yanase 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki City, Kanagawa Prefecture Inside the Toshiba R & D Center (72) Inventor Hideki Satake 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki City, Kanagawa Prefecture Address F-term in Toshiba R & D Center (Reference) 4M104 AA01 BB36 BB37 CC05 DD37 EE03 EE16 5F058 BA20 BB04 BD01 BD04 BD05 BD10 BF12 BF23 BF30 BJ01 5F140 AA00 AA24 AA39 BA01 BD01 BD11 BD13 BE01 BG10 BE10 BE10 BK13 BK29 CA03 CC03 CC12

Claims (5)

[Claims] 1. A field effect transistor in which a source and drain regions are provided on a Si substrate, and a gate electrode is provided between the source and drain regions via a gate insulating film, wherein a conductive oxide is used for the gate electrode. A field-effect transistor, wherein the conductive oxide contains at least one selected from the group consisting of alkaline earths and rare earths. 2. The field effect transistor according to claim 1, wherein said conductive oxide has a perovskite structure. 3. The method according to claim 1, wherein the gate insulating film is formed of S
An insulating film formed by an interface reaction between i and the conductive oxide or an insulating film formed by an interface reaction between a SiO2 film provided on the Si substrate and the conductive oxide is used. Item 2. The field effect transistor according to Item 1. 4. The method according to claim 1, wherein the conductive oxide is ARuO3, AI.
rO3, ARhO3, ACoO3, AMnO3
_{AVO3, ANiO3, ARu 1-x} Ti x O3
(A is at least one selected from rare earth or alkaline earth). The field-effect transistor according to any one of claims 1 to 3, further comprising at least one selected from the group consisting of: 5. The method according to claim 1, wherein the conductive oxide is SrRuO3, B
aRuO3, SrIrO3, SrRhO3, La
The field effect transistor according to claim 4, wherein the field effect transistor contains at least one selected from 0.5Sr0.5CoO3.