JP2002289781A - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Abstract

(57) [Summary] Bi-CMO using inductor for high frequency
The present invention relates to a semiconductor integrated circuit device that realizes prevention of noise and interference from an inductor and improvement of characteristics of an inductor in an S transistor and a method of manufacturing the same. In this semiconductor integrated circuit device, a pedestal is formed by a TEOS film in order to form an interlayer insulating film according to the characteristics of the inductor below an inductor forming region. The thickness of the pedestal made of the TEOS film 61 can be increased or decreased according to the characteristics of the inductor used. As a result, the interlayer insulating film thickness can be reliably ensured according to the characteristics of the inductor, so that noise and interference in the inductor can be prevented, and the current flowing through the inductor can be prevented from flowing to the substrate 51. This can improve the characteristics of the inductor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to the design and construction of electrical inductors and, more particularly, to monolithic multilayer interconnects compatible with low cost silicon technology.
The present invention relates to a semiconductor device having an inductor structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art The miniaturization of electronic circuits is targeted in virtually every field, not only to achieve the miniaturization of mechanical packages, but also to reduce the cost of manufacturing circuits. Many digital and analog circuits, including complex microprocessors and operational amplifiers, have been successfully implemented as silicon-based integrated circuits (ICs). Such circuits typically include active devices such as bipolar transistors, field effect transistors (FETs), various types of diodes, and passive devices such as resistors and capacitors.

[0003] Further, as the channel band of information communication equipment increases, RF (Radio Frequency) or microwave (Microwave, 1 to 30 GHz) is used.
High frequency technology in the area is regarded as important, and gallium arsenide MOSFET and silicon bipolar technology are known as device technologies related thereto. Among them, silicon bipolar technology can satisfy the characteristics required by the system,
In addition, the manufacturing cost and the manufacturing process are simple, and the degree of integration and the manufacturing period can be shortened.

[0004] Passive components such as resistors, capacitors or inductors are always used in systems operating at high frequencies. Among them, the most important passive element in the silicon bipolar technology is the inductor, and the maximum effect can be obtained by optimally combining the inductor and the capacitor.

An inductor is formed by winding a metal line in a high frequency region, but it is not easy to integrate such an inductor in a semiconductor integrated circuit. that is,
For example, in silicon bipolar technology, an inductor is formed insulated on a silicon substrate, and the silicon substrate is formed as one conductor. Therefore, as an inductor including input / output terminals, a parasitic capacitance exists between the metal line and the silicon substrate. This is because it always occurs. In addition, the volume of the inductor is large in order to obtain a desired inductance value, and the parasitic capacitor is also large. This parasitic capacitance acts as a leakage path for an input signal input at a high frequency, and is a factor that degrades the performance of the system. Therefore, it is necessary to minimize the parasitic capacitor to prevent the input signal from leaking to the substrate.

A dielectric element for a semiconductor integrated circuit which has solved the above-mentioned problem is disclosed in, for example, JP-A-11-274412. FIG. 16 shows the diagram shown in this publication.

As shown in FIG. 16, a trench 2 having a predetermined depth and a predetermined width is formed on the surface of a silicon substrate 1 doped with impurities. The trench 2 is filled with an insulating material 3 having low conductivity. The material 3 for filling the trench 2 is polysilicon or ozone TEOS having an excellent trench filling ability.
(Tetraethylorthosilicate)
It is desirable to use

Then, the trench 2 is formed on the surface in this way.
A first insulating film 4 is formed on the surface of the substrate 1 in which the trench 2 is filled with the insulating material 3, and a lead 5 made of a conductor is formed on the first insulating film 4. Have been. Further, a second insulating film 6 is formed on the first insulating film 4 so as to cover a part of the lead 5, and a spiral conductor 7 constituting an inductor is formed on the second insulating film 6. Is formed. The spiral conductor 7 includes a first end 8 as an inner end of the spiral and a second end 9 as an outer end of the spiral, and the first end 8 is formed of a second insulating layer 6. Lead 5 through conductive path 10 formed to penetrate through
Is connected to The lead 5 is connected to an external input or output terminal (not shown).

Therefore, in the above-described conductive element, the trench 2 buried with the low-conductivity material has a role of reducing the surface area of the conductive substrate 1 as a result. As a result, in the conductive element, the area of one side conductor (substrate 1) of the parasitic capacitance composed of the spiral conductor 7, the first and second insulating layers 4 and 6, and the substrate 1 is reduced. Thereby, the leakage current to the substrate 1 can be reduced.

Further, as shown in FIG. 17, the thickness of the insulating film between the epitaxial layer 21 and the inductor is formed thick, so that the characteristics of a semiconductor integrated circuit device operating at a high frequency may be improved.

As shown in FIG. 17, a trench 22 having a predetermined depth and a predetermined width is formed in an epitaxial layer 21 deposited on a substrate. As described above, the trench 22 is filled with an insulating material having low conductivity. As a material for filling the trench 22, it is desirable to use polysilicon or ozone TEOS having an excellent trench filling ability.

In FIG. 17, the trench 22 is filled with polysilicon 23, and a silicon oxide film 24 is deposited on the epitaxial layer 21. On the silicon oxide film 24, a BPSG (phosphor boron silicate glass) film 25 which is an insulating film is formed. And B
A first conductive path 26 is formed on the PSG film 25 by, for example, Al, and the first conductive path 26 and the BPS
On the G film 25, a TEOS film 27 as an insulating film, SOG
(Spin On Glass) film 28 and TEOS
A film 29 has been deposited.

On the TEOS film 29, a second conductive path 30 is formed.
Is connected to the conductive path 30 through a contact hole 31. On the second conductive path 30, a TEOS film 32,
An SOG film 33 and a TEOS film 34 are deposited.
On the TEOS film 34, an inductor and a third conductive path 35 connected to the inductor are formed. The second conductive path 30 and the inductor are connected via a contact hole 36. Then, the inductor and the TEOS film 3
A PIX (polyimide) film 37 is formed on 4. By having this structure, the insulating film layer is formed thick between the inductor, which is a conductor, and the epitaxial layer 21, thereby reducing the leakage current to the substrate at high frequencies.

[0014]

As described above, in the conventional dielectric element for a semiconductor integrated circuit, in order to improve the high frequency characteristics, the insulating capacity under the inductor is taken into consideration in consideration of the usable capacity and width of the formed inductor. The thickness and the like of the film layer were determined.

For example, as shown in FIGS. 16 and 17, a trench is formed in a silicon substrate or an epitaxial layer formed on the substrate, and an insulating material is buried in the trench, thereby forming one side of the parasitic capacitance. There have been methods of reducing the area of the body (silicon substrate) and reducing leakage current to the substrate, and methods of forming a thick insulating layer film between the inductor and the substrate.

However, in order to prevent noise and interference from an inductor used for high frequency and to improve the characteristics of the inductor itself, the distance from the inductor to the silicon substrate must be increased by the insulating film layer and the insulating material. For that purpose, it is effective to increase the distance by the insulating film layer, but it is necessary to form a thicker layer for each insulating layer, and it is necessary to form a multilayer wiring structure. This caused the issues described below.

The first problem is that the thickness of the entire insulating layer is increased by forming the thickness of each insulating layer to be large. For example, as shown in FIG. 17, a contact hole 31 must be formed in the TEOS films 25 and 29 and the first conductive path 26 and the second conductive path 30 must be connected in order to form a multilayer wiring structure. No. But TEOS
Contact holes 31 are formed in the films 25 and 29 by etching.
Is formed, the thickness of the TEOS films 25 and 29 is large, and furthermore, the TEOS films 25 and 29 overlap with two layers, so that the burden on the etcher increases and productivity cannot be obtained.
The problem was that the etching technique was difficult.

The second problem is that, although the thickness of each insulating layer is appropriately suppressed, a multilayer wiring structure may be formed in order to increase the thickness between the inductor and the silicon substrate. In this case, a conductive path of Al or the like must be formed in multiple layers, and there is a problem in that the burden on cost increases.

The third problem is also included in the first and second problems, but only has a structure in which an insulating material is buried by a trench under the inductor, and is a device such as a bipolar transistor or a MOS transistor. Is not formed. However, since elements such as bipolar transistors and MOS transistors are formed on the silicon substrate other than the inductor formation region, like the inductor formation region,
There is a problem that the formation of a thick insulating film layer on the element formation region has a great effect on the quality of the element.

[0020]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems. In a semiconductor integrated circuit device according to the present invention, a silicon substrate of one conductivity type and a silicon substrate formed on the substrate are provided. An opposite conductive type epitaxial layer, a trench formed in the substrate and the epitaxial layer, a plurality of interlayer insulating films formed on the epitaxial layer in which the trench is formed, In a semiconductor integrated circuit device having a plurality of layers of conductive paths made of a metal insulated by a film and an inductor structure formed on an uppermost layer of the conductive paths, the interlayer is formed under the inductor structure. At least one layer of the insulating film is formed to be thick as a pedestal.

The semiconductor integrated circuit device of the present invention preferably has a structure in which one layer of the lower interlayer insulating film on which the inductor structure is formed is formed thick as a pedestal. Since the interlayer insulating film only under the region can be formed thick, it is possible to cope with the above-described various problems such as prevention of noise and interference of the inductor and prevention of influence on elements formed in other regions.

Further, in the semiconductor integrated circuit device of the present invention, preferably, the pedestal interlayer insulating film is formed by increasing or decreasing the interlayer insulating film thickness under the inductor formation region according to the characteristics of the inductor. It is possible to provide a semiconductor integrated circuit device corresponding to the inductor having various characteristics.

Further, in the semiconductor integrated circuit device of the present invention, preferably, at least one side surface of the interlayer insulating film for the pedestal has an inclined surface that is acutely inclined with respect to the substrate surface.
Since the conductive path formed on the pedestal is formed without disconnection, a high quality semiconductor integrated circuit device can be provided.

Further, the present invention has been made in view of the above-mentioned conventional problems. In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a step of preparing a one-conductivity-type silicon substrate is performed. Laminating a reverse conductivity type epitaxial layer on the substrate, forming a trench on the substrate and the surface of the epitaxial layer, forming a multilayer interlayer insulating film on the epitaxial layer, and forming at least one layer of the interlayer insulating film. Forming a first interlayer insulating film having a large layer thickness, forming a pedestal by removing a portion of the first interlayer insulating film by etching while leaving a part of the first interlayer insulating film; Forming a multi-layered conductive path made of a metal, and forming an inductor on the interlayer insulating film on which the pedestal is formed.

Preferably, in the method of manufacturing a semiconductor integrated circuit device according to the present invention, a silicon nitride film is formed below the pedestal interlayer insulating film, and the silicon nitride film is formed in the etching step of forming the pedestal. Can prevent etching of the interlayer insulating film below the pedestal interlayer insulating film.

[0026]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a cross-sectional view of a semiconductor integrated circuit device using a high-frequency inductor, particularly in a region where the inductor is formed, in the first embodiment. .

On a P- type single crystal silicon substrate 51,
For example, an epitaxial layer 52 having a specific resistance of 0.50 Ω · cm and a thickness of 1.40 μm is formed. The substrate 51 and the epitaxial layer 52 are separated into a plurality of island regions by a P + type separation region (not shown) completely penetrating both, and an NPN transistor, an N-channel MOS transistor, a P-channel M
An OS transistor and the like are formed. However, FIG. 1 shows only the inductor formation region, and the other formation regions are omitted.

In the substrate 51 and the epitaxial layer 52, for example, trenches 53 having a width of 1.20 μm, a depth of 5.00 μm, and a pitch of 1.20 μm are formed in a lattice shape. The trench 53 is filled with an insulating material having low conductivity. As a material for filling the trench 53, it is preferable to use polysilicon or ozone TEOS having excellent trench filling ability.

In this embodiment, the interior of the trench 53 is filled with polysilicon, and a silicon oxide film 54 is deposited on the epitaxial layer 52. Silicon oxide film 54
Is deposited on the epitaxial layer 52 to a thickness of about 0.12 μm. On the silicon oxide film 54, a BPSG (phosphor boron silicate glass) film 55 as an insulating film is formed with a thickness of about 1.00 μm. A first conductive path 56 is formed on the BPSG film 55 by, for example, Al sputtering to a thickness of about 0.5 μm, and an insulating film is formed on the first conductive path 56 and the BPSG film 55. TE
OS (Tetraethylorthosilicate)
e) Film 57, SOG (Spin On Glass) film 5
8 and TEOS film 59 are deposited.

Here, the SOG film 58 is replaced with the TEOS film 57,
By forming the TEOS film 59 between the first conductive path 56 and the first conductive path 56, the TEOS film 57 in which the concave and convex portions are formed can be flattened, and the TEOS film 59 can be formed thereon.

The inductor 4 on the TEOS film 59
Under the formation region 1 (shown in FIG. 3), a silicon nitride film 6 is formed.
0 is formed on the order of 0.20 μm, and a pedestal having a thickness of about 5.00 μm is formed on the silicon nitride film 60 by the TEOS film 61. A second conductive path 63 is formed on the pedestal made of the TEOS film 61 and on the TEOS film 59, and the first conductive path 56 and the second conductive path 63 are connected via a contact hole 62. ing. Second
On the conductive path 63, a TEOS film 64, an SOG film 65, and a TEOS film 66 are deposited. TEOS film 66
Above the third conductive path 68 and the inductor 41 are formed. The second conductive path 63 and the third conductive path 68 are connected via a contact hole 67. Then, the inductor 41, the third conductive path 68 and the TEOS
A silicon nitride film 69 is formed on the film 66 to a thickness of about 0.60 μm, and a PIX (polyimide) film 70 is formed on the silicon nitride film 69 to a thickness of about 2.00 μm. In addition, TE
The OS film 66 is formed about 0.30 in consideration of the step coverage of the silicon nitride film 69.

Here, the PIX film 70 is formed by applying a polyamic acid by a coater and causing a dehydration reaction by heat to imidize the polyamic acid. As a property, the flatness is good and the cost is low, but the quality is poor in terms of moisture resistance. However, below the PIX film 70, the silicon nitride film 69
Is formed on the entire surface, so that even if moisture permeates the PIX film 70 and enters the device, the silicon nitride film 69 can prevent the moisture.

Then, as shown in FIG.
1 is formed in a spiral shape, but its first end 42
Are connected to the third conductive path 68 and the second end 43
Is connected to another conductive path (not shown). As shown, the inductor 41 is formed of a rectangular spiral, but is not particularly limited, and may be a circular spiral or a spiral of another shape. The inductor 41 can form inductors having various characteristics by changing the width and the like of the inductor in consideration of the high-frequency characteristics of the device used.

As described above, in the semiconductor integrated circuit device of the present invention, the TEOS film 6
1, the multilayer wiring structure is suppressed, and the inductance of the inductor 4 depends on the characteristics of the inductor 41.
1 and the substrate 51 can be reliably secured. As a result, noise and interference in the inductor 41 can be prevented, and current flowing through the inductor 41 can be prevented from flowing to the substrate 51, and the inductor 41 can be prevented.
Characteristics can be improved. Further, since a multilayer wiring structure can be avoided, the cost can be reduced.

Further, in the semiconductor integrated circuit device of the present invention,
Since the inductor 41 has a pedestal formed of the TEOS film 61 below the formation region, only the interlayer insulating layer below the formation region of the inductor 41 can be formed thick according to the characteristics of the inductor 41. As a result, a thick interlayer insulating film is not formed on devices such as the NPN transistor, the N-channel MOS transistor, and the P-channel MOS transistor formed in regions other than the region where the inductor 41 is formed. The effect on the device can be significantly reduced.

Further, in the semiconductor integrated circuit device of the present invention,
The inclined surface 7 is formed on the side surface of the pedestal formed by the TEOS film 61.
2 are formed. As a result, the TEOS film 61
Since the second conductive path 63 formed thereon is formed without disconnection, a semiconductor integrated circuit device having excellent product quality can be provided.

Next, FIG. 2 shows a semiconductor integrated circuit device using an inductor for high frequency, and in particular, a second example of the semiconductor integrated circuit device in a region where the inductor is formed.
FIG. 3 is a cross-sectional view of the embodiment.

On the P ^- type single crystal silicon substrate 81,
For example, an epitaxial layer 82 having a specific resistance of 0.50 Ω · cm and a thickness of 1.40 μm is formed. The substrate 81 and the epitaxial layer 82 are separated into a plurality of island regions by a P + type separation region (not shown) completely penetrating both, and each of the island regions has an NPN transistor, an N-channel MOS transistor, and a P-channel M
An OS transistor and the like are formed. However, FIG. 2 shows only the inductor formation region, and the other formation regions are omitted.

In the substrate 81 and the epitaxial layer 82, for example, trenches 83 having a width of 1.20 μm, a depth of 5.00 μm, and a pitch of 1.20 μm are formed in a lattice shape. The trench 83 is filled with an insulating material having low conductivity. As a material for filling the trench 83, it is preferable to use polysilicon or ozone TEOS having an excellent trench filling ability.

In this embodiment, the interior of the trench 83 is filled with polysilicon, and a silicon oxide film 84 is deposited on the epitaxial layer 82. Silicon oxide film 84
Is deposited on the epitaxial layer 82 to a thickness of about 0.12 μm. On the silicon oxide film 84, a BPSG (phosphor boron silicate glass) film 85 as an insulating film is formed with a thickness of about 1.00 μm. On the BPSG film 85, a first conductive path 86 having a thickness of about 0.5 μm is formed by, for example, Al sputtering, and on the first conductive path 86 and the BPSG film 85, an insulating film is formed. TE
OS (Tetraethylorthosilicate)
e) Film 87, SOG (Spin On Glass) film 8
8 and TEOS film 89 are deposited.

Here, the SOG film 88 is replaced with a TEOS film 87,
By forming the TEOS film 89 between the first conductive path 86 and the first conductive path 86, the TEOS film 87 in which the uneven portion is formed can be flattened, and the TEOS film 89 can be formed thereon.

The inductor 4 on the TEOS film 89
1 (shown in FIG. 3), a silicon nitride film 9
0 is formed on the silicon nitride film 90 by a PIX (polyimide) film 91 to have a thickness of about 0.20 μm.
A pedestal of about 00 μm is formed. The second conductive path 9 is formed on the base made of the PIX film 91 and the TEOS film 89.
3 are formed, but the first conductive path 86 and the second conductive path 93 are connected via a contact hole 92. On the second conductive path 93, a PIX film 94 having a thickness of 2.
It is deposited to about 00 μm. The third conductive path 96 and the inductor 41 are formed on the PIX film 94. The second conductive path 93 and the third conductive path 96 are connected via a contact hole 95. A PIX film 97 having a thickness of about 2.00 μm is formed on the inductor 41, the third conductive path 96, and the PIX film 94.

Here, the PIX film is formed by applying a polyamic acid by a coater and causing a dehydration reaction by heat to imidize. As a property, the flatness is good and the cost is low, but the quality is poor in terms of moisture resistance.
In the second embodiment, unlike the first embodiment, no silicon nitride film is formed below the PIX film 97. This is because the reliability by forming the silicon nitride film on the PIX film and the moisture resistance by not forming the nitride film are considered.

Then, as shown in FIG.
1 is formed in a spiral shape, but its first end 42
Are connected to the third conductive path 96 and the second end 43
Is connected to another conductive path (not shown). As shown, the inductor 41 is formed of a rectangular spiral, but is not particularly limited, and may be a circular spiral or a spiral of another shape. The inductor 41 can form inductors having various characteristics by changing the width and the like of the inductor in consideration of the high-frequency characteristics of the device used.

As described above, the same effects as in the first embodiment shown in FIG. 1 can be obtained in the second embodiment shown in FIG. In addition to the embodiments shown in FIGS. 1 and 2, for example, a pedestal can be formed of a silicon nitride film, and various types can be used according to the characteristics of the inductor to be used without departing from the gist of the present invention. Can be changed.

Next, the manufacturing process of the first embodiment shown in FIG. 1 by the manufacturing method of the present invention will be described below with reference to FIGS. However, in FIG. 1, regions for forming NPN transistors, N-channel MOS transistors, P-channel MOS transistors and the like formed on the same substrate are omitted. Therefore, FIG. 1 shows only the inductor formation region, and the description of the manufacturing process will be made only for the inductor formation region.

First, as shown in FIG. 4, a P-type single-crystal silicon substrate 51 is prepared, and this substrate 51 is placed on a susceptor of an epitaxial growth apparatus. , 1080
By applying a high temperature of about 100 ° C. and introducing SiH ₂ Cl ₂ gas and H ₂ gas into the reaction tube, a specific resistance of 0.50 Ω ·
An epitaxial layer 52 having a thickness of 1.40 μm is grown. Then, NSG is applied to the surface of the epitaxial layer 52.
(Non-doped silicate glass) and then formed by a well-known photolithography technique.
A photoresist having an opening at a portion where 3 is to be formed is formed as a selection mask. Then, for example, by dry etching, the width is 1.20 μm, the depth is 5.00 μm,
The trenches 53 having a pitch of 1.20 μm are formed in a lattice shape.

Next, as shown in FIG. 5, after all NSG (non-doped silica glass) used as a selection mask in FIG. 4 is removed, polysilicon is buried in the trench 53, and the silicon is deposited on the epitaxial layer 52. An oxide film 54 is deposited. At this time, the epitaxial layer 5
2, a silicon oxide film 54 is formed to a thickness of about 0.12 μm. Then, on the silicon oxide film 54, a BPSG (phosphor boron silicate glass) film 55 as an insulating film is formed with a thickness of about 1.00 μm.

Next, as shown in FIG.
Above, for forming the first conductive path 56, for example,
Al is formed on the entire surface by a thickness of about 0.5 μm by sputtering. Thereafter, a photoresist (not shown) provided on the Al by using a known photolithography technique except a portion where the first conductive path 56 is formed is formed as a selection mask. After that, the first conductive path 56 is formed by removing Al by etching. And the first conductive path 5
6 and BPSG film 55, TEOS as an insulating film
(Tetraethylorthosilicate)
The film 57 is formed with a thickness of about 0.2 μm. At this time, TE
The surface of the OS film 57 is formed with irregularities by the first conductive path 56. An SOG (Spin On Glass) film 58 is formed to eliminate the irregularities and form a flat surface. Thereafter, a TEOS film 59 is deposited on the SOG film 58.

Next, as shown in FIG.
On the silicon nitride film 60, a thickness of about 0.20 μm is formed, and on the silicon nitride film 60, a TEOS film 61 is formed with a thickness of about 5.00 μm. Then, a photoresist (not shown) provided on the TEOS film 61 by using a known photolithography technique except a portion for forming a pedestal is used as a selection mask. Thereafter, the inclined surface 72 is formed on the side surface of the pedestal formed by the TEOS film 61, for example, by etching with buffered hydrofluoric acid or the like such as a tapered etchant.

Here, the silicon nitride film 60 is
When the EOS film 61 is etched, the TEOS film 59 and the like below the TEOS film 61 are formed to protect them from being etched. Thereafter, the silicon nitride film 60 other than the pedestal formation portion is removed by etching.

Next, as shown in FIG.
The second conductive path 6 is formed on the pedestal and the TEOS film 59.
Form 3 Then, similarly to the case where the first conductive path 56 is formed, for example, Al is sputtered to a thickness of 0.5
It is formed over the entire surface by about μm. Thereafter, a photoresist (not shown) provided on the Al by a known photolithography technique except a portion for forming the second conductive path 63 is used as a selection mask. After that, the second conductive path 63 is formed by removing Al by etching. At this time, the first conductive path 56 and the second conductive path 63 are connected via the contact hole 62, but the TEOS film 59
A photoresist (not shown) provided with an opening at a portion where a contact hole 62 is to be formed is formed as a selection mask on the top by a known photolithography technique, and TE
The contact holes 62 are formed by etching the OS films 57 and 59.

After that, a TEOS film 64 having a thickness of about 0.20 μm is formed on the TEOS film 61 formed as the pedestal and the second conductive path 63. At this time, the surface of the TEOS film 61 is formed with irregularities due to the second conductive path 63. In order to eliminate this unevenness and form a flat surface,
An SOG (Spin On Glass) film 65 is formed. Thereafter, a TEOS film 66 is deposited on the SOG film 65 to a thickness of about 0.30 μm.

Next, as shown in FIG.
The third conductive path 68 and the inductor 41 (shown in FIG. 3) are formed thereon. Then, similarly to the case where the third conductive path 68 is formed, for example, Al is sputtered to a thickness of 0.
It is formed on the entire surface of about 5 μm. Thereafter, a photoresist (not shown) provided on Al by leaving a portion for forming the third conductive path 68 by a known photolithography technique
Is formed as a selection mask. After that, the third conductive path 68 is formed by removing Al by etching.
At this time, the second conductive path 63 and the third conductive path 68 are connected via the contact hole 67, but the TEOS film 6
A photoresist (not shown) provided with an opening at a portion where a contact hole 67 is to be formed is formed as a selective mask on the film 6 by a known photolithography technique.
The contact holes 67 are formed by etching the EOS films 64 and 66.

Thereafter, the TEOS film 66 and the third conductive path 6
8 and the inductor 41, a silicon nitride film 69 is formed with a thickness of about 0.60 μm, and a PIX (polyimide) film 70 is formed on the silicon nitride film 69 with a thickness of about 2.00 μm. At this time, since the silicon nitride film 69 is formed on the entire surface under the PIX film 70, even if moisture permeates the PIX film 70 and enters the device, the silicon nitride film 69 can prevent the moisture. A structure that can be used.

As described above, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, the T
In the step of forming the pedestal using the EOS film 61, the thickness of the TEOS film 61 can be increased or decreased according to the characteristics of the inductor 41 used in the semiconductor integrated circuit device of the present invention. As a result, the interlayer insulating film thickness under the inductor 41 forming region can be adjusted according to various characteristics of the inductor 41, and stable characteristics of the inductor 41 can be always obtained.

Further, in the method for manufacturing a semiconductor integrated circuit device according to the present invention, a step of forming a contact hole 62 connecting the first conductive path 56 and the second conductive path 63 to form a multilayer wiring structure. In the above, a connection portion between the first conductive path 56 and the second conductive path 63 is formed in a portion other than the portion where the TEOS film 61 is formed. As a result, the load on the etcher for forming the contact hole 62 can be significantly reduced, and as a result, the etching technique can be facilitated and the productivity can be improved.

Further, in the method of manufacturing a semiconductor integrated circuit device according to the present invention, as compared with the conventional method of manufacturing a semiconductor integrated circuit device, the TEOS film 61 is used to adjust the interlayer insulating film thickness only under the inductor 41 formation region. Thus, it is possible to provide a method of manufacturing a semiconductor integrated circuit device, which can realize a flow for forming a minimum multilayer wiring structure and which can significantly reduce manufacturing costs.

Next, the manufacturing process of the second embodiment shown in FIG. 2 by the manufacturing method of the present invention will be described below with reference to FIGS. However, FIG.
Now, an NPN transistor formed on the same substrate, N
The formation regions of the channel MOS transistor, the P channel MOS transistor, and the like are omitted. Therefore, FIG.
2 shows only the inductor formation region, and the description of the manufacturing process will be made only for the inductor formation region.

First, as shown in FIG. 10, a P-type single-crystal silicon substrate 81 is prepared, and this substrate 81 is placed on a susceptor of an epitaxial growth apparatus. , 108
A high temperature of about 0 ° C. is applied and SiH ₂ Cl ₂
By introducing gas and H ₂ gas, a specific resistance of 0.50
An epitaxial layer 82 of Ω · cm and thickness of 1.40 μm is grown. Then, the surface of the epitaxial layer 82
After depositing and forming SG (non-doped silicate glass), a photoresist having an opening at a portion where a trench 83 is to be formed is formed by a known photolithography technique as a selection mask. Then, for example, the width is 1.20 μm and the depth is 5.00 μm by dry etching.
A trench 83 having a pitch of 1.20 μm is formed in a lattice shape.

Next, as shown in FIG. 11, after removing all the NSG used as the selection mask in FIG. 10, polysilicon is buried in the trench 83, and a silicon oxide film 84 is deposited on the epitaxial layer 82. I do. At this time, a silicon oxide film 84 is formed on the epitaxial layer 82.
Is formed to a thickness of about 0.12 μm. Then, on the silicon oxide film 84, a BPSG (phosphor boron silicate glass) film 85 as an insulating film is formed with a thickness of about 1.00 μm.

Next, as shown in FIG.
For example, Al is formed on the entire surface by sputtering to a thickness of about 0.5 μm to form the first conductive path 86. Thereafter, a photoresist (not shown) provided on the Al by using a known photolithography technique except a portion where the first conductive path 86 is to be formed is used as a selection mask. After that, the first conductive path 86 is formed by removing Al by etching. Then, on the first conductive path 86 and the BPSG film 85, an insulating film TE
OS (Tetraethylorthosilicate)
e) A film 87 is formed with a thickness of about 0.2 μm. At this time,
The TEOS film 87 has an uneven surface formed by the first conductive path 86. In order to eliminate this unevenness and form a flat surface, an SOG (Spin On Glass) film 8 is formed.
8 is formed. Thereafter, the TEOS film 8 is formed on the SOG film 88.
9 is deposited.

Next, as shown in FIG.
9, a silicon nitride film 90 having a thickness of about 0.20 μm is formed, and PIX (polyimide) is formed on the silicon nitride film 90.
A film 91 is formed with a thickness of about 5.00 μm. And PI
A photoresist (not shown) provided on the X film 91 by a known photolithography technique except a portion for forming a pedestal is used as a selection mask. Thereafter, for example, an inclined surface 98 is formed on the side surface of the pedestal formed by the PIX film 91 by performing etching with an etchant for polyimide, a developer, or the like.

Here, the silicon nitride film 90 is made of the P
When etching the IX film 91, the T
Since the EOS film 89 and the like are formed to protect them from being etched, the silicon nitride film 90 other than the pedestal formation portion is thereafter removed by etching.

Next, as shown in FIG.
The second conductive path 9 is formed on the pedestal and the TEOS film 89.
Form 3 Then, similarly to the case where the first conductive path 86 is formed, for example, Al is sputtered to a thickness of 0.5
It is formed over the entire surface by about μm. After that, a photoresist (not shown) provided on the Al by a known photolithography technique except a portion where the second conductive path 93 is formed is formed as a selection mask. After that, the second conductive path 93 is formed by removing Al by etching. At this time, the first conductive path 86 and the second conductive path 93 are connected via the contact hole 92, but the TEOS film 89
A photoresist (not shown) having an opening at a portion where a contact hole 92 is formed is formed as a selection mask on the upper surface by a known photolithography technique, and TE
A contact hole 92 is formed by etching the OS films 87 and 89.

Thereafter, the PIX film 9 formed as a pedestal
A PIX film 94 is formed on the first and second conductive paths 93 to a thickness of about 1.00 μm.

Next, as shown in FIG.
The third conductive path 96 and the inductor 41 (shown in FIG. 3) are formed thereon. Then, similarly to the case where the second conductive path 93 is formed, for example, Al is sputtered to have a thickness of 0.
It is formed on the entire surface of about 5 μm. Thereafter, a photoresist (not shown) provided on Al by leaving a portion for forming the third conductive path 96 by a known photolithography technique
Is formed as a selection mask. Thereafter, the third conductive path 96 is formed by removing Al by etching.
At this time, the second conductive path 93 and the third conductive path 96 are connected via the contact hole 95, but the PIX film 94
A photoresist (not shown) having an opening at a portion where a contact hole 95 is to be formed is formed as a selection mask on the upper surface by a known photolithography technique, and a PI is formed.
The contact hole 67 is etched by etching the X film 94.
To form

Thereafter, the PIX film 94 and the third conductive path 96
And a PIX film 97 having a thickness of 2.
It is formed to a thickness of about 00 μm. In the second embodiment, unlike the first embodiment, no silicon nitride film is formed below the PIX film 97. This is because the reliability by forming the silicon nitride film on the PIX film and the moisture resistance by not forming the nitride film are considered.

As described above, the manufacturing process of the second embodiment shown in FIG.
The same effect as in the manufacturing process according to the embodiment can be obtained. Further, in addition to the embodiment shown in FIGS. 1 and 2, for example, the pedestal can be formed of a silicon nitride film. In this case, the pedestal is formed by isotropic etching. That is, various changes can be made in accordance with the characteristics of the inductor used and the like without departing from the gist of the present invention.

[0071]

According to the present invention, by providing a pedestal formed of a TEOS film or a PIX film under a region where an inductor is formed, a multilayer wiring structure is suppressed, and the thickness of an interlayer insulating layer between the inductor and the substrate is reduced. It can be ensured according to the characteristics of the inductor. Thereby, noise and interference in the inductor can be prevented, and characteristics of the inductor can be improved by preventing current flowing through the inductor from flowing to the substrate. Further, since the multilayer wiring structure can be avoided, the cost can be reduced.

Further, in the semiconductor integrated circuit device of the present invention,
By having the pedestal formed by the TEOS film and the PIX film below the region where the inductor is formed, only the interlayer insulating layer below the region where the inductor is formed can be formed thick according to the characteristics of the inductor. Thus, since the thick interlayer insulating film is not formed on devices such as the NPN transistor, the N-channel MOS transistor, and the P-channel MOS transistor formed outside the inductor forming region, the weight of the thick interlayer insulating film is reduced. And the like can greatly reduce the effect on the device.

Further, in the semiconductor integrated circuit device of the present invention,
An inclined surface is formed on the side surface of the pedestal formed by the TEOS film and the PIX film. As a result, the TE
Since the conductive paths formed on the OS film and the PIX film are formed without disconnection, a semiconductor integrated circuit device having excellent product quality can be provided.

According to the present invention, in the method of manufacturing a semiconductor integrated circuit device, in the step of forming a pedestal made of a TEOS film or a PIX film below the inductor formation region, the TEOS film or the PIX The thickness of the film can be increased or decreased. Thereby, the interlayer insulating film thickness under the inductor forming region can be adjusted according to various characteristics of the inductor, and stable characteristics of the inductor can be always obtained.

Further, in the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the step of forming a contact hole connecting the first conductive path and the second conductive path to form a multilayer wiring structure, A TEOS film or a POS film formed with a connecting portion between the first conductive path and the second conductive path as a pedestal;
Except for the IX film forming part. Thereby, the load on the etcher for forming the contact hole can be greatly reduced, and as a result, the etching technique can be facilitated and the productivity can be improved.

Further, in the method of manufacturing a semiconductor integrated circuit device according to the present invention, compared with the conventional method of manufacturing a semiconductor integrated circuit device, an interlayer insulating film thickness is formed by a TEOS film or a PIX film forming a pedestal only under an inductor formation region. Can be adjusted, a flow of forming a minimum multilayer wiring structure can be realized, and a method of manufacturing a semiconductor integrated circuit device that can significantly reduce manufacturing costs can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a semiconductor integrated circuit device of the present invention.

FIG. 2 is a sectional view illustrating a semiconductor integrated circuit device of the present invention.

FIG. 3 is a plan view of an inductor used in the semiconductor integrated circuit device of the present invention.

FIG. 4 is a sectional view illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 5 is a sectional view illustrating the method for manufacturing the semiconductor integrated circuit device in the first embodiment of the present invention.

FIG. 6 is a sectional view illustrating the method for manufacturing the semiconductor integrated circuit device in the first embodiment of the present invention.

FIG. 7 is a sectional view illustrating the method for manufacturing the semiconductor integrated circuit device in the first embodiment of the present invention.

FIG. 8 is a sectional view illustrating the method for manufacturing the semiconductor integrated circuit device in the first embodiment of the present invention.

FIG. 9 is a sectional view illustrating the method for manufacturing the semiconductor integrated circuit device in the first embodiment of the present invention.

FIG. 10 is a sectional view illustrating the method for manufacturing the semiconductor integrated circuit device in the first embodiment of the present invention.

FIG. 11 is a sectional view illustrating the method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 12 is a sectional view illustrating the method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 13 is a sectional view illustrating the method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 14 is a sectional view illustrating the method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 15 is a sectional view illustrating the method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 16 is a perspective sectional view illustrating a conventional semiconductor integrated circuit device.

FIG. 17 is a sectional view illustrating a conventional semiconductor integrated circuit device.

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Claims (12)

[Claims] A silicon substrate of one conductivity type; an epitaxial layer of a reverse conductivity type formed on the substrate; a trench formed in the substrate and the epitaxial layer; A plurality of interlayer insulating films formed on the epitaxial layer, a plurality of conductive paths made of metal insulated by the interlayer insulating film, and an inductor structure formed on the uppermost layer of the conductive paths. The semiconductor integrated circuit device according to claim 1, wherein at least one layer of said interlayer insulating film is formed thick as a pedestal under said inductor structure. 2. The semiconductor integrated circuit device according to claim 1, wherein the pedestal interlayer insulating film increases or decreases the interlayer insulating film thickness under the inductor forming region according to characteristics of the inductor. 3. The semiconductor device according to claim 1, wherein a silicon nitride film is formed under the pedestal interlayer insulating film.
Or a semiconductor integrated circuit device according to claim 2. 4. The pedestal interlayer insulating film is a TEOS film (Tetraethylorthosilicate).
3. The semiconductor integrated circuit device according to claim 1, comprising: 5. The semiconductor integrated circuit device according to claim 1, wherein the pedestal interlayer insulating film is made of a polyimide film. 6. At least one of the pedestal interlayer insulating films.
The semiconductor integrated circuit device according to claim 1, wherein the side surface has an inclined surface that is acute with respect to the substrate surface. 7. A step of preparing a silicon substrate of one conductivity type, a step of laminating an epitaxial layer of the opposite conductivity type on the substrate, a step of forming a trench on the surface of the substrate and the surface of the epitaxial layer, Forming a multi-layer interlayer insulating film on the layer,
Forming at least one layer of the interlayer insulating film as a first interlayer insulating film having a large thickness; and forming a pedestal by removing a portion of the first interlayer insulating film by etching while leaving a part of the first interlayer insulating film. Forming a multilayer conductive path made of a metal insulated by the interlayer insulating film; and forming an inductor on the interlayer insulating film on which the pedestal is formed. A method for manufacturing a circuit device. 8. The pedestal having a layer thickness formed in at least one layer of the interlayer insulating film increases or decreases the interlayer insulating film thickness below the inductor formation region according to characteristics of the inductor. Item 8. The method for manufacturing a semiconductor integrated circuit device according to Item 7. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 7, wherein a silicon nitride film is formed below said pedestal interlayer insulating film. 10. The pedestal interlayer insulating film is a TEOS film (Tetraethylorthosilicate).
10. The method of manufacturing a semiconductor integrated circuit device according to claim 7, comprising a film. 11. The method for manufacturing a semiconductor integrated circuit device according to claim 7, wherein said pedestal interlayer insulating film is made of a polyimide film. 12. The semiconductor integrated circuit according to claim 7, wherein an inclined surface that is acute with respect to the substrate surface is formed on at least one side surface of the pedestal interlayer insulating film. A method for manufacturing a circuit device.