JP2002289769A - Stacked semiconductor device and method of manufacturing the same - Google Patents
Stacked semiconductor device and method of manufacturing the sameInfo
- Publication number
- JP2002289769A JP2002289769A JP2001087012A JP2001087012A JP2002289769A JP 2002289769 A JP2002289769 A JP 2002289769A JP 2001087012 A JP2001087012 A JP 2001087012A JP 2001087012 A JP2001087012 A JP 2001087012A JP 2002289769 A JP2002289769 A JP 2002289769A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- semiconductor element
- electrode
- wiring board
- wiring conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H10W72/0198—
-
- H10W72/073—
-
- H10W72/877—
-
- H10W72/884—
-
- H10W74/142—
-
- H10W74/15—
-
- H10W90/724—
-
- H10W90/732—
-
- H10W90/734—
-
- H10W90/754—
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
(57)【要約】
【課題】 積層型半導体装置では複数の半導体素子を1
枚の配線基板上に搭載する構造であり、全体として軽量
化が望まれていた。
【解決手段】 少なくとも2つ以上の半導体素子を配線
基板10上に搭載して1パッケージCSPを構成したも
のであり、封止樹脂15の上面周辺部は研削による切削
部17を有して体積が減じられている構造である。その
ため、複数の半導体素子12,14を1パッケージに構
成した積層型半導体装置の軽量化を実現できるものであ
る。さらに第1の半導体素子12と第2の半導体素子1
4との間にはフィルム配線導体13が介在しているの
で、積層型半導体装置全体としてフレキシブル性を有
し、熱膨張による応力に対応できる構造である。
(57) [Summary] [PROBLEMS] In a stacked semiconductor device, a plurality of semiconductor elements are integrated into one.
The structure is to be mounted on a single wiring board, and it has been desired to reduce the weight as a whole. SOLUTION: At least two or more semiconductor elements are mounted on a wiring board 10 to constitute a one-package CSP, and a peripheral portion of an upper surface of a sealing resin 15 has a cut portion 17 by grinding to have a volume. The structure has been reduced. Therefore, it is possible to reduce the weight of the stacked semiconductor device in which the plurality of semiconductor elements 12 and 14 are configured in one package. Further, the first semiconductor element 12 and the second semiconductor element 1
Since the film wiring conductor 13 is interposed between the semiconductor device and the semiconductor device 4, the laminated semiconductor device as a whole has flexibility and can cope with stress due to thermal expansion.
Description
【0001】[0001]
【発明の属する技術分野】本発明は複数の機能の半導体
素子を三次元方向に積層搭載した積層型半導体装置およ
びその製造方法に関するものであり、特に突起電極によ
り各半導体素子をフリップチップ接続するとともに接続
の信頼性の高い積層型半導体装置およびその製造方法に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stacked semiconductor device in which semiconductor elements having a plurality of functions are stacked in a three-dimensional direction and a method of manufacturing the same. The present invention relates to a stacked semiconductor device with high connection reliability and a method for manufacturing the same.
【0002】[0002]
【従来の技術】近年、回路構成された1つの配線基板
(キャリア基板)上に複数の機能の半導体素子を積層搭
載し、1パッケージを構成する積層型半導体装置が開発
されている。2. Description of the Related Art In recent years, a stacked semiconductor device has been developed in which semiconductor elements having a plurality of functions are stacked and mounted on one circuit board (carrier board) having a circuit structure to constitute one package.
【0003】以下、開発されている従来の積層型半導体
装置について、その代表構造として2つの半導体素子が
基板上に積層搭載されたタイプの積層型半導体装置につ
いて説明する。Hereinafter, a conventional stacked semiconductor device which has been developed will be described as a typical structure of a stacked semiconductor device in which two semiconductor elements are stacked and mounted on a substrate.
【0004】図9は従来の積層型半導体装置の構成を示
す断面図である。FIG. 9 is a sectional view showing the structure of a conventional stacked semiconductor device.
【0005】図9に示すように、従来の積層型半導体装
置は、配線電極1a,1bおよび底面に端子電極2を有
した配線基板3と、配線基板3上に樹脂4を介してその
表面側が配線基板3と対向してフリップチップ接続され
た第1の半導体素子5と、第1の半導体素子5の裏面上
に接着剤6を介してその表面側を上にして搭載された第
2の半導体素子7を有し、第1の半導体素子5はその表
面の電極パッド5aに設けた突起電極5bが配線基板3
の配線電極1aと接続し、第2の半導体素子7はその表
面の電極パッド7aが配線基板3の配線電極1bと金属
細線8で接続され、配線基板3の上面領域が絶縁性の封
止樹脂9で封止された構造である。As shown in FIG. 9, in a conventional stacked semiconductor device, a wiring board 3 having wiring electrodes 1a and 1b and a terminal electrode 2 on the bottom surface, and a surface side of the wiring board 3 with a resin 4 interposed therebetween. A first semiconductor element 5 flip-chip connected to the wiring substrate 3 and a second semiconductor mounted on the back surface of the first semiconductor element 5 via an adhesive 6 with its front side up; The first semiconductor element 5 has a protruding electrode 5b provided on an electrode pad 5a on the surface thereof.
Of the second semiconductor element 7, the electrode pad 7a on the surface thereof is connected to the wiring electrode 1b of the wiring board 3 by a thin metal wire 8, and the upper surface area of the wiring board 3 is an insulating sealing resin. 9 is a structure sealed.
【0006】また配線基板3上に搭載された半導体素子
は、メモリー素子、ロジック素子などの複数の種類の半
導体素子であり、1パッケージで多機能素子による高機
能型の半導体装置である。The semiconductor elements mounted on the wiring board 3 are a plurality of types of semiconductor elements such as a memory element and a logic element, and are high-function type semiconductor devices formed of multifunctional elements in one package.
【0007】次に従来の積層型半導体装置の製造方法に
ついて図面を参照しながら説明する。図10,図11は
従来の積層型半導体装置の製造方法を示す工程ごとの主
要な断面図である。Next, a conventional method for manufacturing a stacked semiconductor device will be described with reference to the drawings. 10 and 11 are main cross-sectional views for each process showing a conventional method for manufacturing a stacked semiconductor device.
【0008】まず図10(a)に示すように、第1の半
導体素子5の表面の複数の電極パッド5a上に突起電極
(バンプ)5bを各々形成する。この突起電極の形成は
メッキバンプ、ワイヤーボンド法によるスタッドバンプ
などの工法で形成される。First, as shown in FIG. 10A, projecting electrodes (bumps) 5b are respectively formed on a plurality of electrode pads 5a on the surface of the first semiconductor element 5. The bump electrodes are formed by a plating bump, a stud bump by a wire bonding method, or the like.
【0009】次に図10(b)に示すように、配線基板
3の上面に対してシート状の異方性導電性(ACF)の
樹脂4を供給するとともに、第1の半導体素子5をその
突起電極5bの面を配線基板3の上面に対向させる。こ
こで配線基板への樹脂4の供給は配線基板3の配線電極
1aを覆うように供給するものであり、シート状以外に
液状の樹脂をポッティングにより供給してもよい。Next, as shown in FIG. 10B, a sheet-like anisotropic conductive (ACF) resin 4 is supplied to the upper surface of the wiring board 3 and the first semiconductor element 5 is The surface of the protruding electrode 5 b faces the upper surface of the wiring board 3. Here, the resin 4 is supplied to the wiring board so as to cover the wiring electrodes 1a of the wiring board 3, and a liquid resin other than the sheet shape may be supplied by potting.
【0010】次に図10(c)に示すように、第1の半
導体素子5を配線基板3の上面に加圧して、第1の半導
体素子5の突起電極5bと配線基板3の配線電極1aと
を接続する。Next, as shown in FIG. 10C, the first semiconductor element 5 is pressed against the upper surface of the wiring substrate 3 to project the protruding electrode 5b of the first semiconductor element 5 and the wiring electrode 1a of the wiring substrate 3. And connect.
【0011】次に図10(d)に示すように、第2の半
導体素子7を配線基板3に搭載した第1の半導体素子5
の裏面(背面側)に対して接着剤6により、その裏面で
接着固定する。Next, as shown in FIG. 10D, the first semiconductor element 5 having the second semiconductor element 7 mounted on the wiring board 3 is formed.
Is bonded and fixed to the back surface (back surface side) of the device with the adhesive 6.
【0012】次に図11(a)に示すように、搭載した
第2の半導体素子7の電極パッド7aと配線基板3の上
面の配線電極1bとを金属細線8により電気的に接続す
る。Next, as shown in FIG. 11A, the electrode pads 7a of the mounted second semiconductor element 7 and the wiring electrodes 1b on the upper surface of the wiring board 3 are electrically connected by thin metal wires 8.
【0013】そして図11(b)に示すように、配線基
板3の上面領域を絶縁性の封止樹脂9で封止することに
より積層型半導体装置を形成するものである。Then, as shown in FIG. 11B, a stacked semiconductor device is formed by sealing the upper surface area of the wiring board 3 with an insulating sealing resin 9.
【0014】以上のような各工程により、従来は配線基
板上に2つの半導体素子を搭載した1パッケージタイプ
の積層型半導体装置を実現していた。Through the above steps, a one-package type stacked semiconductor device in which two semiconductor elements are mounted on a wiring board has been conventionally realized.
【0015】[0015]
【発明が解決しようとする課題】しかしながら前記従来
の積層型半導体装置では、2つの半導体素子を1枚の配
線基板上に搭載する構造であるため、配線基板の上面領
域へ付加される構成部材が多く、熱膨張によって配線基
板の反り、または熱膨張、反りによる半導体素子と配線
基板の配線電極との接続部分へのダメージが懸念されて
いた。However, the conventional stacked semiconductor device has a structure in which two semiconductor elements are mounted on a single wiring board, so that the components added to the upper surface area of the wiring board are not provided. In many cases, warpage of the wiring board due to thermal expansion or damage to a connection portion between the semiconductor element and the wiring electrode of the wiring board due to thermal expansion or warpage has been concerned.
【0016】すなわち熱膨張によって、積層型半導体装
置を構成する配線基板、半導体素子、突起電極などの各
構成部材の熱膨張係数の差から、半導体素子が膨張した
場合、パッケージ内部で微動することにより、半導体素
子と配線基板の配線電極との接続部分が破断する恐れが
あった。従来は積層型半導体装置を構成する配線基板、
半導体素子、突起電極などの各構成部材の熱膨張係数を
近似するようにしたり、または熱膨張や、それによる積
層型半導体装置自体の反りに対抗できる構造にするなど
して対策していたが、今後は2つの半導体素子の搭載に
とどまらず、3つ以上の半導体素子を1つの配線基板上
に搭載して1パッケージを構成する傾向にあるため、根
本的な積層型半導体装置の構造の開発が必要とされてい
た。That is, when the semiconductor element expands due to the difference in thermal expansion coefficient between the constituent members such as the wiring board, the semiconductor element, and the protruding electrode constituting the stacked semiconductor device due to the thermal expansion, the semiconductor element moves slightly inside the package. In addition, there is a possibility that the connection portion between the semiconductor element and the wiring electrode of the wiring board is broken. Conventionally, wiring boards that constitute a stacked semiconductor device,
Semiconductor elements, such as by approximating the thermal expansion coefficient of each component such as bump electrodes, or by making the structure capable of resisting the thermal expansion and the resulting warpage of the stacked semiconductor device itself, In the future, there will be more than three semiconductor elements mounted on a single wiring board to form one package, instead of mounting two semiconductor elements. Was needed.
【0017】さらに1パッケージで複数の半導体素子を
搭載しているため、全体として体積が増加し、その重量
も増加するため、軽量化を実現した積層型半導体装置が
要望されていた。Further, since a plurality of semiconductor elements are mounted in one package, the volume increases as a whole, and the weight also increases. Therefore, there has been a demand for a stacked semiconductor device which is lighter in weight.
【0018】本発明は前記した従来の課題を解決するも
のであり、2つ以上の半導体素子を配線基板上に3次元
で搭載して1パッケージを構成した積層型半導体装置に
おいて、各半導体素子と配線基板の配線電極との接続部
分の接続の信頼性を高め、かつ軽量化を図ることができ
る積層型半導体装置およびその製造方法を提供すること
を目的とする。The present invention solves the above-mentioned conventional problems. In a stacked semiconductor device in which two or more semiconductor elements are three-dimensionally mounted on a wiring board to constitute one package, each semiconductor element has It is an object of the present invention to provide a stacked semiconductor device capable of improving the reliability of connection of a connection portion with a wiring electrode of a wiring board and achieving weight reduction, and a method of manufacturing the same.
【0019】[0019]
【課題を解決するための手段】前記従来の課題を解決す
るために本発明の積層型半導体装置は、配線電極を有し
た配線基板と、前記配線基板上に樹脂を介してその表面
側が前記配線基板と対向してフリップチップ接続された
第1の半導体素子と、前記第1の半導体素子の裏面上に
フィルム配線導体を介してその表面側が前記第1の半導
体素子の裏面と対向してフリップチップ接続された第2
の半導体素子との少なくとも2つの半導体素子を有し、
前記第1の半導体素子はその表面に設けた突起電極が前
記配線基板の配線電極と接続し、前記第2の半導体素子
はその表面に設けた突起電極が前記フィルム配線導体の
配線導体と接続し、前記配線導体は前記配線基板の配線
電極と接続し、前記配線基板の上面領域は封止樹脂で封
止されている積層型半導体装置であって、研削によって
前記封止樹脂の上面周辺部の体積が減じられている積層
型半導体装置である。In order to solve the above-mentioned conventional problems, a stacked semiconductor device according to the present invention comprises a wiring board having wiring electrodes, and a wiring board on a surface of the wiring board via a resin. A first semiconductor element which is flip-chip connected to a substrate, and a flip chip having a front side opposed to the back side of the first semiconductor element via a film wiring conductor on a back side of the first semiconductor element; Connected second
Having at least two semiconductor elements with a semiconductor element of
In the first semiconductor element, the protruding electrode provided on the surface thereof is connected to the wiring electrode of the wiring board, and in the second semiconductor element, the protruding electrode provided on the surface thereof is connected to the wiring conductor of the film wiring conductor. The wiring conductor is connected to a wiring electrode of the wiring board, and the upper surface area of the wiring board is a stacked semiconductor device sealed with a sealing resin; The stacked semiconductor device has a reduced volume.
【0020】そして具体的には、フィルム配線導体は配
線導体を軟性樹脂で挟んだ構造である積層型半導体装置
である。More specifically, the film wiring conductor is a laminated semiconductor device having a structure in which the wiring conductor is sandwiched between soft resins.
【0021】また、配線基板は、上面に配線電極と、下
面に前記上面の配線電極と接続した端子電極とを有した
配線基板である積層型半導体装置である。The wiring substrate is a stacked semiconductor device which is a wiring substrate having a wiring electrode on an upper surface and a terminal electrode connected to the wiring electrode on the upper surface on a lower surface.
【0022】また、第1の半導体素子または第2の半導
体素子の面積と配線基板の面積とは、前記配線基板の面
積が大きい条件で略同等の大きさで構成されてチップサ
イズパッケージを構成している積層型半導体装置であ
る。Further, the area of the first semiconductor element or the second semiconductor element and the area of the wiring board are substantially the same under the condition that the area of the wiring board is large, so that a chip size package is formed. Is a stacked semiconductor device.
【0023】前記構成の通り、2つ目以上の積層された
半導体素子は、軟性樹脂で構成されたフィルム配線導体
を介して積層搭載されているため、積層型半導体装置の
熱膨張によって、半導体素子が膨張した場合、パッケー
ジ内部で微動しても、その膨張移動にともなって接続部
分も連動して移動するため、半導体素子と配線基板の配
線電極との接続部分が破断することを防止し、接続の信
頼性を高めることができる。またフィルム配線導体は配
線導体がその表裏面側が軟性樹脂で挟まれた3層構造で
あるため、内層の配線導体自体の固定は避けられ、熱膨
張の微動に対応できるものである。また半導体素子と半
導体素子との間には軟性樹脂で構成されたフィルム配線
導体が介在しているので、積層型半導体装置全体として
フレキシブル性を有し、熱膨張による応力に対応できる
構造である。As described above, since the second or more stacked semiconductor elements are stacked and mounted via a film wiring conductor made of a soft resin, the semiconductor element is thermally expanded by the stacked semiconductor device. When the semiconductor device expands, even if it moves slightly inside the package, the connection portion also moves in conjunction with the expansion movement, so that the connection portion between the semiconductor element and the wiring electrode of the wiring board is prevented from breaking, and the connection is prevented. Reliability can be improved. Further, since the film wiring conductor has a three-layer structure in which the wiring conductor is sandwiched between the front and back surfaces by the soft resin, the wiring conductor itself in the inner layer can be prevented from being fixed and can cope with slight movement due to thermal expansion. Further, since a film wiring conductor made of a soft resin is interposed between the semiconductor elements, the laminated semiconductor device has flexibility as a whole, and has a structure capable of coping with stress due to thermal expansion.
【0024】さらに封止樹脂の上面の周辺部は封止樹脂
が研削で除去されて、封止樹脂全体の体積が減じられて
いるため、複数の半導体素子を1パッケージに構成した
積層型半導体装置の軽量化を実現できるものである。Further, the peripheral portion of the upper surface of the sealing resin is removed by grinding and the volume of the entire sealing resin is reduced. Therefore, a stacked semiconductor device in which a plurality of semiconductor elements are formed in one package. Can be realized.
【0025】また本発明の積層型半導体装置の製造方法
は、上面に配線電極と、下面に前記上面の配線電極と接
続した端子電極とを有した配線基板に対して、樹脂を介
してその表面の電極パッドに突起電極が形成された第1
の半導体素子をフリップチップ接続し、前記突起電極と
前記配線基板の配線電極とを接続する第1の工程と、前
記第1の半導体素子の裏面および前記配線基板上面に一
体でフィルム配線導体を接着するとともに、前記フィル
ム配線導体の配線導体の外方端部を前記配線基板の配線
電極と接続する第2の工程と、前記第1の半導体素子の
裏面に対して、前記フィルム配線導体を介してその表面
の電極パッドに突起電極が形成された第2の半導体素子
をフリップチップ接続し、前記突起電極と前記フィルム
配線導体の配線導体の内方端部とを接続する第3の工程
と、前記配線基板の上面領域を封止樹脂で封止する第4
の工程と、前記配線基板の上面に形成した封止樹脂の上
面周辺部に対して研削処理を行い、前記封止樹脂の上面
周辺部の体積を減じる第5の工程とよりなる積層型半導
体装置の製造方法である。Further, according to the method of manufacturing a stacked semiconductor device of the present invention, there is provided a method for manufacturing a stacked semiconductor device, comprising the steps of: providing a wiring substrate having a wiring electrode on an upper surface and a terminal electrode connected to the wiring electrode on the upper surface on a lower surface; The first in which the protruding electrode is formed on the electrode pad of
A first step of flip-chip connecting the semiconductor elements to connect the protruding electrodes to the wiring electrodes of the wiring board; and bonding a film wiring conductor integrally to the back surface of the first semiconductor element and the top face of the wiring board. A second step of connecting an outer end of the wiring conductor of the film wiring conductor to a wiring electrode of the wiring board; and a step of connecting the film wiring conductor to the back surface of the first semiconductor element via the film wiring conductor. A third step of flip-chip connecting a second semiconductor element having a protruding electrode to an electrode pad on the surface thereof and connecting the protruding electrode to an inner end of a wiring conductor of the film wiring conductor; The fourth step of sealing the upper surface area of the wiring board with the sealing resin
And a fifth step of performing a grinding process on the peripheral portion of the upper surface of the sealing resin formed on the upper surface of the wiring substrate to reduce the volume of the peripheral portion of the upper surface of the sealing resin. It is a manufacturing method of.
【0026】また本発明の積層型半導体装置の製造方法
は、その上面に複数の半導体素子が個々に搭載されるも
ので、また上面に個々の半導体素子に対応した配線電極
が設けられ、下面には上面の配線電極と基板内部で接続
した端子電極が設けられ、個々の半導体素子単位ごとに
分割され得る構造の1枚の大型の配線基板に対して、樹
脂を介してその表面の電極パッドに突起電極が形成され
た第1の半導体素子をフリップチップ接続し、前記突起
電極と前記配線基板の配線電極とを接続する第1の工程
と、前記第1の半導体素子の裏面および前記配線基板上
面に一体でフィルム配線導体を接着するとともに、前記
フィルム配線導体の配線導体の外方端部を前記配線基板
の配線電極と接続する第2の工程と、前記第1の半導体
素子の裏面に対して、前記フィルム配線導体を介してそ
の表面の電極パッドに突起電極が形成された第2の半導
体素子をフリップチップ接続し、前記突起電極と前記フ
ィルム配線導体の配線導体の内方端部とを接続する第3
の工程と、前記配線基板の上面領域を封止樹脂で封止す
る第4の工程と、前記配線基板に対して、個々の積層型
半導体装置に切断分離するとともに、前記配線基板の上
面に形成した封止樹脂の上面周辺部に対して研削処理を
行い、前記封止樹脂の上面周辺部の体積を減じる第5の
工程とよりなる積層型半導体装置の製造方法である。According to the method of manufacturing a stacked semiconductor device of the present invention, a plurality of semiconductor elements are individually mounted on the upper surface, wiring electrodes corresponding to the individual semiconductor elements are provided on the upper surface, and the lower surface is provided on the lower surface. Is provided with terminal electrodes connected to the wiring electrodes on the upper surface inside the substrate. One large wiring substrate with a structure that can be divided into individual semiconductor element units is applied to the electrode pads on the surface via resin. A first step of flip-chip connecting the first semiconductor element on which the protruding electrode is formed, and connecting the protruding electrode to a wiring electrode of the wiring board; a back surface of the first semiconductor element and an upper face of the wiring board A second step of bonding a film wiring conductor integrally with the wiring conductor and connecting an outer end of the wiring conductor of the film wiring conductor to a wiring electrode of the wiring board; Flip-chip connecting a second semiconductor element having a protruding electrode to an electrode pad on the surface thereof via the film wiring conductor, and connecting the protruding electrode to an inner end of the wiring conductor of the film wiring conductor; Third
And a fourth step of sealing the upper surface area of the wiring substrate with a sealing resin. The wiring substrate is cut and separated into individual stacked semiconductor devices and formed on the upper surface of the wiring substrate. A fifth step of performing a grinding process on the peripheral portion of the upper surface of the sealing resin to reduce the volume of the peripheral portion of the upper surface of the sealing resin.
【0027】そして具体的には、第1の半導体素子の裏
面に対して、フィルム配線導体を介してその表面の電極
パッドに突起電極が形成された第2の半導体素子をフリ
ップチップ接続し、前記突起電極と前記フィルム配線導
体の配線導体の内方端部とを接続する第3の工程では、
第2の半導体素子を前記フィルム配線導体に対して加圧
し、前記突起電極で前記フィルム配線導体のフィルム材
を突き破って前記配線導体の内方端部とを接続する積層
型半導体装置の製造方法である。More specifically, the second semiconductor element having a protruding electrode formed on an electrode pad on the surface of the first semiconductor element is flip-chip connected to the back surface of the first semiconductor element via a film wiring conductor. In the third step of connecting the protruding electrode and the inner end of the wiring conductor of the film wiring conductor,
A method of manufacturing a stacked semiconductor device, in which a second semiconductor element is pressed against the film wiring conductor, the projecting electrode breaks through the film material of the film wiring conductor, and connects the inner end of the wiring conductor. is there.
【0028】また、第1の半導体素子の裏面および配線
基板上面に一体でフィルム配線導体を接着するととも
に、前記フィルム配線導体の配線導体の外方端部を前記
配線基板の配線電極と接続する第2の工程では、配線導
体を軟性樹脂で挟んだ構造のフィルム配線導体を用いる
積層型半導体装置の製造方法である。In addition, a film wiring conductor is integrally bonded to the back surface of the first semiconductor element and the upper surface of the wiring board, and an outer end of the wiring conductor of the film wiring conductor is connected to a wiring electrode of the wiring board. The second step is a method of manufacturing a stacked semiconductor device using a film wiring conductor having a structure in which a wiring conductor is sandwiched between soft resins.
【0029】前記構成の通り、2つ目以上の積層された
半導体素子は、軟性樹脂で構成されたフィルム配線導体
を介して積層搭載されているため、積層型半導体装置の
熱膨張によって、半導体素子が膨張した場合、パッケー
ジ内部で微動しても、その膨張移動にともなって接続部
分も連動して移動するため、半導体素子と配線基板の配
線電極との接続部分が破断することを防止し、接続の信
頼性を高めることができる構造を実現できる。またフィ
ルム配線導体に対して、半導体素子を突起電極を加圧し
て接続する場合においても、フィルム配線導体のフィル
ム材が外圧を吸収するため、下側の半導体素子への影響
を解消し、安定に信頼性よくフリップチップ接続できる
ものである。As described above, since the second or more stacked semiconductor elements are stacked and mounted via a film wiring conductor made of a soft resin, the semiconductor elements are thermally expanded by the stacked semiconductor device. When the semiconductor device expands, even if it moves slightly inside the package, the connection portion also moves in conjunction with the expansion movement, so that the connection portion between the semiconductor element and the wiring electrode of the wiring board is prevented from being broken, and the connection is prevented. A structure that can increase the reliability of the device can be realized. Also, when connecting the semiconductor element to the film wiring conductor by pressing the protruding electrode, the film material of the film wiring conductor absorbs the external pressure, thereby eliminating the influence on the lower semiconductor element and stably. It can be flip-chip connected with high reliability.
【0030】さらに一括成形後に個々の積層型半導体装
置に切断分離する工程で、切断とともに封止樹脂の周辺
部を研削するため、封止樹脂の上面の周辺部は封止樹脂
が除去されて、封止樹脂全体の体積を減じることがで
き、軽量化を達成できるものである。Further, in the step of cutting and separating into individual stacked semiconductor devices after the collective molding, the peripheral portion of the sealing resin is ground along with the cutting, so that the peripheral portion of the upper surface of the sealing resin is removed. The volume of the entire sealing resin can be reduced, and the weight can be reduced.
【0031】[0031]
【発明の実施の形態】以下、本発明の積層型半導体装置
およびその製造方法の一実施形態について説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a stacked semiconductor device and a method of manufacturing the same according to the present invention will be described below.
【0032】まず本実施形態の積層型半導体装置につい
て図面を参照しながら説明する。図1は本実施形態の積
層型半導体装置を示す主要な断面図である。First, the stacked semiconductor device of the present embodiment will be described with reference to the drawings. FIG. 1 is a main cross-sectional view showing the stacked semiconductor device of the present embodiment.
【0033】本実施形態の積層型半導体装置は、配線電
極を有した配線基板と、その配線基板上にその表面側が
配線基板と対向してフリップチップ接続された第1の半
導体素子と、その第1の半導体素子の裏面上にフィルム
配線導体を介してその表面側が第1の半導体素子の裏面
と対向してフリップチップ接続された第2の半導体素子
との少なくとも2つの半導体素子を有した積層型半導体
装置であって、第1の半導体素子はその表面に設けた突
起電極が配線基板の配線電極と接続し、配線基板と対向
してフリップチップ接続された第1の半導体素子以外の
半導体素子はその表面に設けた突起電極でフィルム配線
導体を介してフリップチップ接続され、そのフィルム配
線導体の配線導体は配線基板の配線電極と接続して1パ
ッケージでチップ積層構造を有するものである。The stacked semiconductor device according to the present embodiment includes a wiring board having wiring electrodes, a first semiconductor element having a front surface facing the wiring board and flip-chip connected to the wiring board, and A stacked type having at least two semiconductor elements on a back surface of the first semiconductor element and a second semiconductor element flip-chip-connected to the back side of the first semiconductor element with the front side facing the back surface of the first semiconductor element via a film wiring conductor; In the semiconductor device, the first semiconductor element has a protruding electrode provided on a surface thereof connected to a wiring electrode of a wiring board, and a semiconductor element other than the first semiconductor element flip-chip connected to the wiring board is provided. The projecting electrodes provided on the surface are flip-chip connected via the film wiring conductor, and the wiring conductor of the film wiring conductor is connected to the wiring electrode of the wiring board to form a chip in one package. And it has a layer structure.
【0034】具体的には図1に示すように、本実施形態
の積層型半導体装置は、上面(表面)に配線電極10
a,10bを有し、下面(裏面)に各配線電極10a,
10bと基板内部で電気的に接続した端子電極を有した
配線基板10と、配線基板10上に異方性導電性(AC
F)の樹脂11を介してその表面側が配線基板10と対
向してフリップチップ接続されたマイコン素子などの第
1の半導体素子12と、第1の半導体素子12の裏面上
にフィルム配線導体13を介してその表面側が第1の半
導体素子12の裏面と対向してフリップチップ接続され
たメモリー素子などの第2の半導体素子14との少なく
とも2つの半導体素子を有した積層型半導体装置であっ
て、第1の半導体素子12はその表面の電極パッド12
a上に設けた突起電極12bが配線基板10の配線電極
10aと接続し、第2の半導体素子14はその表面の電
極パッド14a上に設けた突起電極14bがフィルム配
線導体13の配線導体13aの内方端部と接続し、その
配線導体13aの外方端部は配線基板10の配線電極1
0bと接続した構造である。そして第2の半導体素子1
4の裏面が露出されて配線基板10の上面領域は封止樹
脂15で封止されているものである。Specifically, as shown in FIG. 1, the stacked semiconductor device of this embodiment has a wiring electrode 10
a, 10b, and each wiring electrode 10a,
10b having a terminal electrode electrically connected to the inside of the substrate, and anisotropic conductive (AC)
F) A first semiconductor element 12 such as a microcomputer element flip-chip connected with its front side facing the wiring board 10 via the resin 11 and a film wiring conductor 13 on the back surface of the first semiconductor element 12. A stacked semiconductor device having at least two semiconductor elements with a second semiconductor element such as a memory element flip-chip-connected with the front side facing the back side of the first semiconductor element via a second semiconductor element; The first semiconductor element 12 has an electrode pad 12 on its surface.
The protruding electrode 12b provided on the wiring substrate 10 is connected to the wiring electrode 10a of the wiring board 10, and the protruding electrode 14b provided on the electrode pad 14a on the surface of the second semiconductor element 14 is connected to the wiring conductor 13a of the film wiring conductor 13. It is connected to the inner end, and the outer end of the wiring conductor 13a is connected to the wiring electrode 1 of the wiring board 10.
0b. And the second semiconductor element 1
4 is exposed and the upper surface area of the wiring board 10 is sealed with a sealing resin 15.
【0035】また、フィルム配線導体13は、配線導体
13aをエポキシ系樹脂、エラストマー、シリコーン樹
脂などの軟性樹脂によるフィルム材13bで挟んだ構造
であり、各素子間の衝撃を吸収している構造である。The film wiring conductor 13 has a structure in which a wiring conductor 13a is sandwiched between film materials 13b made of a soft resin such as an epoxy resin, an elastomer, or a silicone resin, and has a structure that absorbs shocks between respective elements. is there.
【0036】そして本実施形態の積層型半導体装置は、
第1の半導体素子12または第2の半導体素子14の面
積と配線基板10の面積とは、配線基板10の面積が大
きい条件で略同等の大きさで構成されてCSP(チップ
サイズパッケージ)を構成しているものである。The stacked semiconductor device of this embodiment is
The area of the first semiconductor element 12 or the second semiconductor element 14 and the area of the wiring board 10 are substantially equal to each other under the condition that the area of the wiring board 10 is large, and constitute a CSP (chip size package). Is what you are doing.
【0037】以上、本実施形態の積層型半導体装置は、
少なくとも2つ以上の半導体素子を配線基板上に搭載し
て1パッケージCSPを構成したものであり、特に2つ
目以上の積層された半導体素子は、軟性樹脂で構成され
たフィルム配線導体13を介して積層搭載されているた
め、積層型半導体装置の熱膨張によって、半導体素子が
膨張した場合、パッケージ内部で微動しても、その膨張
移動にともなって接続部分も連動して移動するため、半
導体素子と配線基板10の配線電極10a,10bとの
接続部分が破断することを防止し、接続の信頼性を高め
ることができる。またフィルム配線導体13は配線導体
13aがその表裏面側が軟性樹脂によるフィルム材13
bで挟まれた3層構造であるため、内層の配線導体13
a自体の固定は避けられ、熱膨張の微動に対応できるも
のである。また半導体素子と半導体素子との間には軟性
樹脂で構成されたフィルム配線導体13が介在している
ので、積層型半導体装置全体としてフレキシブル性を有
し、熱膨張による応力に対応できる構造である。As described above, the stacked semiconductor device of this embodiment is
At least two or more semiconductor elements are mounted on a wiring board to form a one-package CSP. In particular, the second or more stacked semiconductor elements are connected via a film wiring conductor 13 made of a soft resin. When the semiconductor element expands due to the thermal expansion of the stacked semiconductor device, even if it moves slightly inside the package, the connection part also moves in conjunction with the expansion movement. The connection between the wiring electrodes 10a and 10b of the wiring substrate 10 can be prevented from being broken, and the connection reliability can be improved. The film conductor 13a is made of a film material 13 made of a soft resin on the front and back sides of the wiring conductor 13a.
b, so that the wiring conductors 13 in the inner layer
The fixing of a itself can be avoided, and it can cope with the slight movement of thermal expansion. Further, since the film wiring conductor 13 made of a soft resin is interposed between the semiconductor elements, the laminated semiconductor device has flexibility as a whole and can cope with stress due to thermal expansion. .
【0038】また第2の半導体素子14の裏面を露出さ
せて配線基板10の上面領域を封止樹脂15で封止して
いるので、第2の半導体素子14に発熱性の半導体素子
を採用したとしても、放熱効果を高めることができる。
これは半導体素子の裏面を封止樹脂外に露出させるため
にはフリップチップ構造が適しているものであり、本実
施形態のように基板上に搭載するすべての半導体素子が
フリップチップ接続構造を有しているため、放熱効果を
高めるに適したパッケージ構造である。Since the back surface of the second semiconductor element 14 is exposed and the upper surface area of the wiring board 10 is sealed with the sealing resin 15, a heat-generating semiconductor element is used as the second semiconductor element 14. Also, the heat radiation effect can be enhanced.
This is because a flip-chip structure is suitable for exposing the back surface of the semiconductor element outside the sealing resin, and all the semiconductor elements mounted on the substrate have a flip-chip connection structure as in this embodiment. Therefore, the package structure is suitable for enhancing the heat radiation effect.
【0039】次に本実施形態の積層型半導体装置の製造
方法について図面を参照しながら説明する。図2,図3
は本実施形態の積層型半導体装置の製造方法を示す工程
ごとの主要な断面図である。Next, a method for manufacturing the stacked semiconductor device of the present embodiment will be described with reference to the drawings. Figures 2 and 3
FIG. 4 is a main cross-sectional view for each step showing the method for manufacturing the stacked semiconductor device of the embodiment.
【0040】まず図2(a)に示すように、第1の半導
体素子12の表面の複数の電極パッド12a上に突起電
極(バンプ)12bを各々形成する。この突起電極の形
成はメッキバンプ、ワイヤーボンド法によるスタッドバ
ンプなどの工法で形成される。First, as shown in FIG. 2A, projecting electrodes (bumps) 12b are formed on a plurality of electrode pads 12a on the surface of the first semiconductor element 12, respectively. The bump electrodes are formed by a plating bump, a stud bump by a wire bonding method, or the like.
【0041】次に図2(b)に示すように、配線基板1
0の上面に対してシート状の異方性導電性(ACF)の
樹脂11を供給するとともに、マイコン(ロジック)素
子などの第1の半導体素子12をその突起電極12bの
面を配線基板10の上面に対向させる。ここで配線基板
10への樹脂11の供給は配線基板10の配線電極10
aを覆うように供給するものであり、シート状以外に液
状の樹脂をポッティングにより供給してもよい。またこ
の樹脂11の配線基板10と第1の半導体素子12との
間隙への充填は、前述のようにシート状の樹脂11を予
め配線基板10上に供給する以外、第1の半導体素子1
2と配線基板10の配線電極10aとを接続した後、注
入によって充填形成してもよい。この後注入による充填
では、絶縁性の樹脂でよい。Next, as shown in FIG.
In addition to supplying a sheet-like anisotropic conductive (ACF) resin 11 to the upper surface of the wiring board 10, the first semiconductor element 12 such as a microcomputer (logic) element is connected to the surface of the projecting electrode 12 b of the wiring board 10. Face the upper surface. Here, the supply of the resin 11 to the wiring board 10 is performed by using the wiring electrodes 10 of the wiring board 10.
The liquid resin is supplied so as to cover the sheet a, and a liquid resin other than the sheet shape may be supplied by potting. The filling of the resin 11 into the gap between the wiring board 10 and the first semiconductor element 12 is performed by first supplying the sheet-shaped resin 11 onto the wiring board 10 as described above.
After connecting the wiring electrode 2 and the wiring electrode 10a of the wiring board 10, the filling may be performed by injection. In the subsequent filling by injection, an insulating resin may be used.
【0042】次に図2(c)に示すように、第1の半導
体素子12を配線基板10の上面に加圧して、第1の半
導体素子12の突起電極12bと配線基板10の配線電
極10aとを接続する。なお、素子接続、固定後におい
て、第1の半導体素子12の厚みを薄厚にするため、グ
ラインダーによる研削、さらにポリッシングを行い、素
子厚を薄くする工程を付加してもよい。Next, as shown in FIG. 2C, the first semiconductor element 12 is pressed against the upper surface of the wiring board 10 to project the protruding electrode 12b of the first semiconductor element 12 and the wiring electrode 10a of the wiring board 10. And connect. After connecting and fixing the elements, a step of reducing the element thickness by performing grinding with a grinder and further polishing to reduce the thickness of the first semiconductor element 12 may be added.
【0043】次に図2(d)に示すように、第1の半導
体素子12の裏面および配線基板10上面に一体でフィ
ルム配線導体13を接着する。この場合、配線導体13
aの表裏面を軟性樹脂によるフィルム材13bで挟んだ
3層構造のフィルム配線導体を用いるものである。また
フィルム配線導体13には接着性を持たせるか、または
加熱してフィルム配線導体13を軟化させて接着する。Next, as shown in FIG. 2D, a film wiring conductor 13 is integrally bonded to the back surface of the first semiconductor element 12 and the upper surface of the wiring board 10. In this case, the wiring conductor 13
In this example, a film wiring conductor having a three-layer structure in which the front and back surfaces of a are sandwiched between film materials 13b made of a soft resin is used. Further, the film wiring conductor 13 is provided with adhesiveness, or is heated to soften and adhere the film wiring conductor 13.
【0044】さらに図3(a)に示すように、フィルム
配線導体の接着とともに、フィルム配線導体13の配線
導体13aの外方端部を配線基板10の配線電極10b
と接続する。Further, as shown in FIG. 3A, the outer ends of the wiring conductors 13a of the film wiring conductors 13 are connected to the wiring electrodes 10b of the wiring board 10 together with the adhesion of the film wiring conductors.
Connect with
【0045】次に図3(b)に示すように、第1の半導
体素子12の裏面に対して、フィルム配線導体13を介
してその表面の電極パッド14aに突起電極14bが形
成されたメモリー素子などの第2の半導体素子14をフ
リップチップ接続し、突起電極14bとフィルム配線導
体13の配線導体13aの内方端部とを接続する。この
場合、第2の半導体素子14をフィルム配線導体13に
対して加熱状態で加圧し、突起電極14bでフィルム配
線導体13のフィルム材13bを突き破って配線導体1
3aの内方端部とを接続するものである。また、ここで
フィルム配線導体13に対して、第2の半導体素子14
の突起電極14bを加圧して接続するにおいても、フィ
ルム配線導体13のフィルム材13bが外圧を吸収する
ため、下側の第1の半導体素子12への影響を解消し、
安定に信頼性よくフリップチップ接続できるものであ
る。なお、素子接続、固定後において、第2の半導体素
子14の厚みを薄厚にするため、グラインダーによる研
削、さらにポリッシングを行い、素子厚を薄くする工程
を付加してもよい。Next, as shown in FIG. 3B, a memory element in which a projecting electrode 14b is formed on an electrode pad 14a on the front surface of the first semiconductor element 12 via a film wiring conductor 13 on the back surface of the first semiconductor element 12 The second semiconductor element 14 is flip-chip connected, and the protruding electrode 14b is connected to the inner end of the wiring conductor 13a of the film wiring conductor 13. In this case, the second semiconductor element 14 is pressed against the film wiring conductor 13 in a heated state, and the projecting electrode 14b breaks through the film material 13b of the film wiring conductor 13 and pressurizes the wiring conductor 1.
3a is connected to the inner end. Here, the second semiconductor element 14 is connected to the film wiring conductor 13.
When the protruding electrodes 14b are connected by pressurizing, the film material 13b of the film wiring conductor 13 absorbs the external pressure, so that the influence on the lower first semiconductor element 12 is eliminated,
Flip-chip connection can be performed stably and reliably. After the connection and fixing of the elements, a step of reducing the element thickness by grinding with a grinder and further polishing to reduce the thickness of the second semiconductor element 14 may be added.
【0046】そして図3(c)に示すように、配線基板
10の上面領域を絶縁性のエポキシ樹脂などの封止樹脂
15で封止する。この樹脂封止においては、金型を用い
たトランスファーモールド法やポッティング工法により
封止できるものである。また樹脂封止では、第2の半導
体素子14の裏面を露出させて配線基板10の上面領域
を封止樹脂15で封止する。この封止構造により、第2
の半導体素子14に発熱性の半導体素子を採用したとし
ても、放熱効果を高めることができる。Then, as shown in FIG. 3C, the upper surface area of the wiring board 10 is sealed with a sealing resin 15 such as an insulating epoxy resin. In this resin sealing, sealing can be performed by a transfer molding method using a mold or a potting method. In the resin sealing, the back surface of the second semiconductor element 14 is exposed, and the upper surface area of the wiring substrate 10 is sealed with the sealing resin 15. With this sealing structure, the second
Even if a heat-generating semiconductor element is used as the semiconductor element 14, the heat radiation effect can be enhanced.
【0047】以上、本実施形態の積層型半導体装置の製
造方法では、2つ目以上の積層された半導体素子は、軟
性樹脂で構成されたフィルム配線導体13を介して積層
搭載されているため、積層型半導体装置の熱膨張によっ
て、半導体素子が膨張した場合、パッケージ内部で微動
しても、その膨張移動にともなって接続部分も連動して
移動するため、半導体素子と配線基板10の配線電極1
0a,10bとの接続部分が破断することを防止し、接
続の信頼性を高めることができる構造を実現できる。ま
たフィルム配線導体13に対して、半導体素子を突起電
極を加圧して接続するにおいても、フィルム配線導体1
3のフィルム材13bが外圧を吸収するため、下側の半
導体素子への影響を解消し、安定に信頼性よくフリップ
チップ接続できるものである。As described above, in the manufacturing method of the stacked semiconductor device of the present embodiment, since the second or more stacked semiconductor elements are stacked and mounted via the film wiring conductor 13 made of a soft resin, When the semiconductor element expands due to the thermal expansion of the stacked semiconductor device, even if the semiconductor element slightly moves inside the package, the connection portion also moves in conjunction with the expansion movement.
It is possible to realize a structure that can prevent the connection portion with 0a and 10b from breaking, and can improve the reliability of the connection. In connecting the semiconductor element to the film wiring conductor 13 by pressing the protruding electrode, the film wiring conductor
Since the third film material 13b absorbs external pressure, the influence on the lower semiconductor element is eliminated, and the flip-chip connection can be stably and reliably performed.
【0048】また本実施形態の積層型半導体装置の製造
方法では、基板上への各半導体素子の搭載、フィルム配
線導体の形成、封止の各工程は、その上面に複数の半導
体素子が個々に搭載されるもので、また上面に個々の半
導体素子に対応した配線電極が設けられ、下面には上面
の配線電極と基板内部で接続した端子電極が設けられ、
個々の半導体素子単位ごとに分割され得る構造の1枚の
大型の配線基板に対して各々行なうものであり、一括成
形工法と称される量産に適した製造工法である。そして
配線基板の上面に対して封止樹脂で封止した後、最終工
程として、ダイシングブレードにより個々の積層型半導
体装置に切断分離する工程を有するものである。したが
って、図1に示したような実施形態の積層型半導体装置
の外形形状として、封止樹脂15の側面が配線基板10
の側面と同一面に位置しているものであり、これは一括
切断によって分割された形状である。In the method of manufacturing a stacked semiconductor device according to the present embodiment, each of the steps of mounting each semiconductor element on the substrate, forming the film wiring conductor, and encapsulating is performed by individually mounting a plurality of semiconductor elements on the upper surface. On the upper surface, wiring electrodes corresponding to individual semiconductor elements are provided on the upper surface, and terminal electrodes connected to the wiring electrodes on the upper surface inside the substrate are provided on the lower surface,
This method is performed on one large wiring board having a structure that can be divided for each semiconductor element unit, and is a manufacturing method suitable for mass production called a collective molding method. Then, after sealing the upper surface of the wiring substrate with the sealing resin, a final step is a step of cutting and separating into individual stacked semiconductor devices using a dicing blade. Therefore, as the outer shape of the stacked semiconductor device of the embodiment as shown in FIG.
Is located on the same plane as the side surface of the, and has a shape divided by batch cutting.
【0049】また本実施形態の積層型半導体装置の製造
方法で用いたフィルム配線導体については、図4の平面
図に示すように、搭載する半導体素子の表面の電極パッ
ドの配置および配線基板の配線電極の配置に対して、各
々大きさ、ピッチなどの条件を合わせた配線導体13a
を軟性樹脂によるフィルム材13bで挟んだ3層構造で
あり、図に示した構造は半導体素子の電極パッドが素子
周辺部に配置されたペリフェラルパッド配置に対応させ
た構造を示している。勿論、配線導体13aの長さやフ
ィルム材13b自体の面積についても配線基板や下側の
半導体素子の面積、段差に応じて設定するものである。As shown in the plan view of FIG. 4, the film wiring conductors used in the method of manufacturing the stacked semiconductor device according to the present embodiment are arranged as shown in the plan view of FIG. Wiring conductors 13a whose size, pitch, etc. are adjusted for the arrangement of the electrodes.
Is sandwiched between film materials 13b of a soft resin, and the structure shown in the figure shows a structure in which electrode pads of a semiconductor element correspond to peripheral pad arrangements arranged around the element. Of course, the length of the wiring conductor 13a and the area of the film material 13b itself are also set according to the area of the wiring substrate and the lower semiconductor element and the step.
【0050】次に図5の断面図には、本実施形態で説明
した積層型半導体装置において、3つの半導体素子を1
パッケージCSPとした形態を示す。Next, in the cross-sectional view of FIG. 5, three semiconductor elements are represented by one in the stacked semiconductor device described in this embodiment.
This shows a form of a package CSP.
【0051】図5に示すように、配線基板10と対向し
てフリップチップ接続された第1の半導体素子12以外
の第2の半導体素子14、第3の半導体素子16は突起
電極14b、突起電極16bで各々フィルム配線導体1
3を介してフリップチップ接続され、そのフィルム配線
導体13の配線導体13aは配線基板10の配線電極1
0bと接続して1パッケージでチップ積層構造を有する
ものである。このように3つの半導体素子を積層搭載す
る場合であっても、2つ目以上の積層された半導体素子
は、軟性樹脂で構成されたフィルム配線導体13を介し
て積層搭載されているため、積層型半導体装置の熱膨張
によって、半導体素子が膨張した場合、パッケージ内部
で微動しても、その膨張移動にともなって接続部分も連
動して移動するため、半導体素子と配線基板10の配線
電極との接続部分が破断することを防止し、接続の信頼
性を高めることができる構造を実現できる。またフィル
ム配線導体13に対して、半導体素子を突起電極を加圧
して接続するにおいても、フィルム配線導体13のフィ
ルム材が外圧を吸収するため、下側の半導体素子への影
響を解消し、安定に信頼性よくフリップチップ接続でき
るものである。As shown in FIG. 5, the second semiconductor element 14 other than the first semiconductor element 12 and the third semiconductor element 16 which are flip-chip connected to the wiring board 10 include a bump electrode 14b and a bump electrode. 16b each film wiring conductor 1
3, and the wiring conductor 13a of the film wiring conductor 13 is connected to the wiring electrode 1 of the wiring board 10.
0b and has a chip laminated structure in one package. Even when three semiconductor elements are stacked and mounted as described above, the second and more stacked semiconductor elements are stacked and mounted via the film wiring conductor 13 made of a soft resin. When the semiconductor element expands due to the thermal expansion of the semiconductor device, even if the semiconductor element slightly moves inside the package, the connection portion also moves in conjunction with the expansion movement. A structure that can prevent the connection portion from breaking and improve the reliability of the connection can be realized. Further, even when the semiconductor element is connected to the film wiring conductor 13 by pressing the protruding electrode, the film material of the film wiring conductor 13 absorbs the external pressure. Flip-chip connection can be performed with high reliability.
【0052】次に別の実施形態の積層型半導体装置およ
びその製造方法について説明する。Next, a stacked semiconductor device of another embodiment and a method of manufacturing the same will be described.
【0053】図6は別の実施形態の積層型半導体装置を
示す主要な断面図である。FIG. 6 is a main sectional view showing a stacked semiconductor device of another embodiment.
【0054】図6に示すように、本実施形態の積層型半
導体装置は、配線基板10上面の封止樹脂15の内部の
構造は図1に示した構造と同様であるが、封止樹脂15
の上面周辺部は研削による切削部17を有して体積が減
じられている構造である。本実施形態では図1で示した
積層型半導体装置の封止樹脂の体積に対して20[%]
の体積を研削によって減じている。As shown in FIG. 6, in the stacked semiconductor device of this embodiment, the structure inside the sealing resin 15 on the upper surface of the wiring board 10 is the same as the structure shown in FIG.
The periphery of the upper surface has a cut portion 17 by grinding to reduce the volume. In this embodiment, the volume of the sealing resin of the stacked semiconductor device shown in FIG.
Is reduced by grinding.
【0055】この構造により、複数の半導体素子を1パ
ッケージに構成した積層型半導体装置の軽量化を実現で
きるものである。With this structure, it is possible to reduce the weight of a stacked semiconductor device in which a plurality of semiconductor elements are formed in one package.
【0056】次に本実施形態の積層型半導体装置の製造
方法について、図面を参照しながら説明する。Next, a method for manufacturing the stacked semiconductor device of the present embodiment will be described with reference to the drawings.
【0057】図7,図8は本実施形態の積層型半導体装
置の製造方法を示す主要な工程ごとの断面図である。FIGS. 7 and 8 are cross-sectional views showing the main steps of a method for manufacturing a stacked semiconductor device according to this embodiment.
【0058】まず図7(a)に示すように、前述の積層
型半導体装置の製造方法で説明した通り、配線基板10
に対して複数の半導体素子を搭載、電気的に接続し、配
線基板10の上面を封止樹脂15で封止する。ここでは
個々の半導体素子単位ごとに分割され得る構造の1枚の
大型の配線基板10を使用している。First, as shown in FIG. 7A, as described in the above-described method for manufacturing a stacked semiconductor device,
A plurality of semiconductor elements are mounted on and electrically connected to each other, and the upper surface of the wiring board 10 is sealed with a sealing resin 15. Here, one large wiring board 10 having a structure that can be divided for each semiconductor element unit is used.
【0059】次に図7(b)に示すように、封止樹脂1
5が形成された配線基板10の上方の各分割領域に対し
て、研削機能部18と切断機能部19とを有した回転ブ
レード20を配置させる。Next, as shown in FIG.
A rotating blade 20 having a grinding function section 18 and a cutting function section 19 is arranged in each of the divided areas above the wiring board 10 on which the wiring board 5 is formed.
【0060】次に図8(a)に示すように、回転ブレー
ド20を封止樹脂15に当接させ、回転ブレード20の
研削機能部18で封止樹脂15を研削除去するととも
に、封止樹脂15、配線基板10の分割領域を切断機能
部19で切断することにより、個々の積層型半導体装置
21を得る。Next, as shown in FIG. 8A, the rotating blade 20 is brought into contact with the sealing resin 15, and the sealing resin 15 is ground and removed by the grinding function section 18 of the rotating blade 20. 15. By cutting the divided region of the wiring board 10 by the cutting function unit 19, individual stacked semiconductor devices 21 are obtained.
【0061】これにより、図8(b)に示すように、封
止樹脂15の上面周辺部は研削による切削部17を有し
て体積が減じられている構造の積層型半導体装置21を
実現できるものである。As a result, as shown in FIG. 8B, a stacked semiconductor device 21 having a structure in which the peripheral portion of the upper surface of the sealing resin 15 has a cut portion 17 by grinding to reduce the volume can be realized. Things.
【0062】なお、使用する回転ブレード20の研削機
能部18の幅や、切断機能部19の幅、長さ、および研
削機能部18と切断機能部19との長さについては、切
断分離する封止樹脂の厚み、配線基板の厚みにより適
宜、設定するものである。また研削機能部18の粗さに
ついても同様である。The width of the grinding function portion 18 of the rotating blade 20 to be used, the width and length of the cutting function portion 19, and the length of the grinding function portion 18 and the cutting function portion 19 are determined by the sealing to be cut and separated. The thickness is appropriately set depending on the thickness of the resin and the thickness of the wiring board. The same applies to the roughness of the grinding function unit 18.
【0063】以上、本実施形態では、配線電極を有した
配線基板と、その配線基板上にその表面側が配線基板と
対向してフリップチップ接続された第1の半導体素子
と、その第1の半導体素子の裏面上にフィルム配線導体
を介してその表面側が第1の半導体素子の裏面と対向し
てフリップチップ接続された第2の半導体素子との少な
くとも2つの半導体素子を有した積層型半導体装置であ
って、第1の半導体素子はその表面に設けた突起電極が
配線基板の配線電極と接続し、配線基板と対向してフリ
ップチップ接続された第1の半導体素子以外の半導体素
子はその表面に設けた突起電極でフィルム配線導体を介
してフリップチップ接続され、そのフィルム配線導体の
配線導体は配線基板の配線電極と接続して1パッケージ
でチップ積層構造を有するものであるため、2つ目以上
の積層された半導体素子は、軟性樹脂で構成されたフィ
ルム配線導体を介して積層搭載され、積層型半導体装置
の熱膨張によって、半導体素子が膨張した場合、パッケ
ージ内部で微動しても、その膨張移動にともなって接続
部分も連動して移動するため、半導体素子と配線基板の
配線電極との接続部分が破断することを防止し、接続の
信頼性を高めることができる。またフィルム配線導体は
配線導体がその表裏面側が軟性樹脂で挟まれた3層構造
であるため、内層の配線導体自体の固定は避けられ、熱
膨張の微動に対応できるものである。また半導体素子と
半導体素子との間には軟性樹脂で構成されたフィルム配
線導体が介在しているので、積層型半導体装置全体とし
てフレキシブル性を有し、熱膨張による応力に対応でき
る構造である。As described above, in the present embodiment, the wiring substrate having the wiring electrodes, the first semiconductor element on the wiring substrate whose front side is flip-chip connected to the wiring substrate, and the first semiconductor element A stacked semiconductor device having at least two semiconductor elements on a back surface of the element and a second semiconductor element flip-chip-connected to the back surface of the first semiconductor element with the front side facing the back surface of the first semiconductor element via a film wiring conductor. In the first semiconductor element, the protruding electrodes provided on the surface thereof are connected to the wiring electrodes of the wiring board, and the semiconductor elements other than the first semiconductor element flip-chip connected to the wiring board are provided on the surface thereof. Flip-chip connection is made with the provided protruding electrode via the film wiring conductor, and the wiring conductor of the film wiring conductor is connected to the wiring electrode of the wiring board to form a chip laminated structure in one package. Since the second or more stacked semiconductor elements are stacked and mounted via a film wiring conductor made of a soft resin, and when the semiconductor element expands due to thermal expansion of the stacked semiconductor device, Even if it moves slightly inside the package, the connection part moves in conjunction with the expansion movement, so that the connection part between the semiconductor element and the wiring electrode of the wiring board is prevented from breaking, and the connection reliability is improved. be able to. Further, since the film wiring conductor has a three-layer structure in which the wiring conductor is sandwiched between the front and back surfaces by the soft resin, the wiring conductor itself in the inner layer can be prevented from being fixed and can cope with slight movement due to thermal expansion. Further, since a film wiring conductor made of a soft resin is interposed between the semiconductor elements, the laminated semiconductor device has flexibility as a whole, and has a structure capable of coping with stress due to thermal expansion.
【0064】[0064]
【発明の効果】本発明の積層型半導体装置は、2つ目以
上の積層された半導体素子は、軟性樹脂で構成されたフ
ィルム配線導体を介して積層搭載されているため、積層
型半導体装置の熱膨張によって、半導体素子が膨張した
場合、パッケージ内部で微動しても、その膨張移動にと
もなって接続部分も連動して移動し、半導体素子と配線
基板の配線電極との接続部分が破断することを防止し、
接続の信頼性を高めることができる積層型半導体装置で
ある。また半導体素子と半導体素子との間には軟性樹脂
で構成されたフィルム配線導体が介在しているので、積
層型半導体装置全体としてフレキシブル性を有し、熱膨
張による応力に対応できる構造を有した高信頼性の積層
型半導体装置を実現できるものである。According to the stacked semiconductor device of the present invention, the second or more stacked semiconductor elements are stacked and mounted via a film wiring conductor made of a soft resin. When the semiconductor element expands due to thermal expansion, even if it moves slightly inside the package, the connection part also moves in conjunction with the expansion movement, and the connection part between the semiconductor element and the wiring electrode of the wiring board is broken. To prevent
This is a stacked semiconductor device capable of improving connection reliability. Further, since a film wiring conductor made of a soft resin is interposed between the semiconductor elements, the laminated semiconductor device has flexibility as a whole and has a structure capable of coping with stress due to thermal expansion. A highly reliable stacked semiconductor device can be realized.
【0065】また本発明の積層型半導体装置の製造方法
は、2つ目以上の積層された半導体素子は、軟性樹脂で
構成されたフィルム配線導体を介して積層搭載されてい
るため、積層型半導体装置の熱膨張によって、半導体素
子が膨張した場合、パッケージ内部で微動しても、その
膨張移動にともなって接続部分も連動して移動するた
め、半導体素子と配線基板の配線電極との接続部分が破
断することを防止し、接続の信頼性を高めることができ
る構造を実現できる。またフィルム配線導体に対して、
半導体素子を突起電極を加圧して接続するにおいても、
フィルム配線導体のフィルム材が外圧を吸収するため、
下側の半導体素子への影響を解消し、安定に信頼性よく
フリップチップ接続できるものである。In the method of manufacturing a stacked semiconductor device according to the present invention, the stacked semiconductor elements are stacked and mounted via a film wiring conductor made of a soft resin. When the semiconductor element expands due to the thermal expansion of the device, even if the semiconductor element slightly moves inside the package, the connection part also moves in conjunction with the expansion movement. A structure that can prevent breakage and enhance the reliability of connection can be realized. Also, for film wiring conductors,
Even when connecting semiconductor elements by pressing the protruding electrodes,
Because the film material of the film wiring conductor absorbs external pressure,
This eliminates the influence on the lower semiconductor element and enables stable and reliable flip-chip connection.
【図1】本発明の一実施形態の積層型半導体装置を示す
断面図FIG. 1 is a sectional view showing a stacked semiconductor device according to an embodiment of the present invention;
【図2】本発明の一実施形態の積層型半導体装置の製造
方法を示す断面図FIG. 2 is a cross-sectional view illustrating a method of manufacturing a stacked semiconductor device according to one embodiment of the present invention.
【図3】本発明の一実施形態の積層型半導体装置の製造
方法を示す断面図FIG. 3 is a sectional view showing the method of manufacturing the stacked semiconductor device according to one embodiment of the present invention;
【図4】本発明の一実施形態の積層型半導体装置の製造
方法で用いるフィルム配線導体を示す平面図FIG. 4 is a plan view showing a film wiring conductor used in the method for manufacturing a stacked semiconductor device according to one embodiment of the present invention;
【図5】本発明の一実施形態の積層型半導体装置を示す
断面図FIG. 5 is a sectional view showing a stacked semiconductor device according to one embodiment of the present invention;
【図6】本発明の一実施形態の積層型半導体装置を示す
断面図FIG. 6 is a sectional view showing a stacked semiconductor device according to one embodiment of the present invention;
【図7】本発明の一実施形態の積層型半導体装置の製造
方法を示す断面図FIG. 7 is a sectional view showing the method of manufacturing the stacked semiconductor device according to one embodiment of the present invention;
【図8】本発明の一実施形態の積層型半導体装置の製造
方法を示す断面図FIG. 8 is a sectional view showing the method of manufacturing the stacked semiconductor device according to one embodiment of the present invention;
【図9】従来の積層型半導体装置を示す断面図FIG. 9 is a cross-sectional view showing a conventional stacked semiconductor device.
【図10】従来の積層型半導体装置の製造方法を示す断
面図FIG. 10 is a cross-sectional view illustrating a method for manufacturing a conventional stacked semiconductor device.
【図11】従来の積層型半導体装置の製造方法を示す断
面図FIG. 11 is a sectional view showing a conventional method of manufacturing a stacked semiconductor device.
1a,1b 配線電極 2 端子電極 3 配線基板 4 樹脂 5 第1の半導体素子 5a 電極パッド 5b 突起電極 6 接着剤 7 第2の半導体素子 7a 電極パッド 8 金属細線 9 封止樹脂 10 配線基板 10a,10b 配線電極 11 樹脂 12 第1の半導体素子 12a 電極パッド 12b 突起電極 13 フイルム配線導体 13a 配線導体 13b フィルム材 14 第2の半導体素子 14a 電極パッド 14b 突起電極 15 封止樹脂 16 第3の半導体素子 16b 突起電極 17 切削部 18 研削機能部 19 切断機能部 20 回転ブレード 21 積層型半導体装置 1a, 1b Wiring electrode 2 Terminal electrode 3 Wiring board 4 Resin 5 First semiconductor element 5a Electrode pad 5b Protruding electrode 6 Adhesive 7 Second semiconductor element 7a Electrode pad 8 Fine metal wire 9 Sealing resin 10 Wiring board 10a, 10b Wiring electrode 11 Resin 12 First semiconductor element 12a Electrode pad 12b Protruding electrode 13 Film wiring conductor 13a Wiring conductor 13b Film material 14 Second semiconductor element 14a Electrode pad 14b Protruding electrode 15 Sealing resin 16 Third semiconductor element 16b Projection Electrode 17 Cutting part 18 Grinding function part 19 Cutting function part 20 Rotating blade 21 Stacked semiconductor device
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 21/60 H01L 25/08 Z 23/12 501 23/28 Fターム(参考) 4M109 AA01 BA03 CA04 CA21 DA03 DA07 EA02 5F044 KK07 KK08 KK16 LL09 MM06 NN07 NN13 QQ01 RR16 RR18 5F061 AA01 BA03 CA04 CA21 GA05──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 21/60 H01L 25/08 Z 23/12 501 23/28 F-term (Reference) 4M109 AA01 BA03 CA03 CA04 CA21 DA03 DA07 EA02 5F044 KK07 KK08 KK16 LL09 MM06 NN07 NN13 QQ01 RR16 RR18 5F061 AA01 BA03 CA04 CA21 GA05
Claims (8)
板と対向してフリップチップ接続された第1の半導体素
子と、 前記第1の半導体素子の裏面上にフィルム配線導体を介
してその表面側が前記第1の半導体素子の裏面と対向し
てフリップチップ接続された第2の半導体素子との少な
くとも2つの半導体素子を有し、 前記第1の半導体素子はその表面に設けた突起電極が前
記配線基板の配線電極と接続し、 前記第2の半導体素子はその表面に設けた突起電極が前
記フィルム配線導体の配線導体と接続し、前記配線導体
は前記配線基板の配線電極と接続し、 前記配線基板の上面領域は封止樹脂で封止されている積
層型半導体装置であって、 研削によって前記封止樹脂の上面周辺部の体積が減じら
れていることを特徴とする積層型半導体装置。A wiring board having wiring electrodes; a first semiconductor element flip-chip-connected to the wiring board with a front surface facing the wiring board via a resin on the wiring board; and the first semiconductor. The semiconductor device further includes at least two semiconductor elements on a back surface of the element and a second semiconductor element flip-chip-connected to the back side of the first semiconductor element with the front side facing the back surface of the first semiconductor element via a film wiring conductor; In the semiconductor element, the protruding electrode provided on the surface thereof is connected to the wiring electrode of the wiring board, and in the second semiconductor element, the protruding electrode provided on the surface thereof is connected to the wiring conductor of the film wiring conductor, The conductor is connected to a wiring electrode of the wiring board, and the upper surface area of the wiring board is a stacked semiconductor device sealed with a sealing resin, and the volume of the peripheral portion of the upper surface of the sealing resin is reduced by grinding. A stacked semiconductor device, comprising:
で挟んだ構造であることを特徴とする請求項1に記載の
積層型半導体装置。2. The stacked semiconductor device according to claim 1, wherein the film wiring conductor has a structure in which the wiring conductor is sandwiched between soft resins.
前記上面の配線電極と接続した端子電極とを有した配線
基板であることを特徴とする請求項1に記載の積層型半
導体装置。3. The stacked semiconductor device according to claim 1, wherein the wiring board is a wiring board having a wiring electrode on an upper surface and a terminal electrode connected to the wiring electrode on the upper surface on a lower surface. .
子の面積と配線基板の面積とは、前記配線基板の面積が
大きい条件で略同等の大きさで構成されてチップサイズ
パッケージを構成していることを特徴とする請求項1に
記載の積層型半導体装置。4. The area of the first semiconductor element or the second semiconductor element and the area of the wiring board are substantially equal to each other under the condition that the area of the wiring board is large. The stacked semiconductor device according to claim 1, wherein:
線電極と接続した端子電極とを有した配線基板に対し
て、樹脂を介してその表面の電極パッドに突起電極が形
成された第1の半導体素子をフリップチップ接続し、前
記突起電極と前記配線基板の配線電極とを接続する第1
の工程と、 前記第1の半導体素子の裏面および前記配線基板上面に
一体でフィルム配線導体を接着するとともに、前記フィ
ルム配線導体の配線導体の外方端部を前記配線基板の配
線電極と接続する第2の工程と、 前記第1の半導体素子の裏面に対して、前記フィルム配
線導体を介してその表面の電極パッドに突起電極が形成
された第2の半導体素子をフリップチップ接続し、前記
突起電極と前記フィルム配線導体の配線導体の内方端部
とを接続する第3の工程と、 前記配線基板の上面領域を封止樹脂で封止する第4の工
程と、 前記配線基板の上面に形成した封止樹脂の上面周辺部に
対して研削処理を行い、前記封止樹脂の上面周辺部の体
積を減じる第5の工程とよりなることを特徴とする積層
型半導体装置の製造方法。5. A wiring board having a wiring electrode on an upper surface and a terminal electrode connected to the wiring electrode on the upper surface on a lower surface, wherein a protruding electrode is formed on an electrode pad on the surface via a resin. A first semiconductor element that is flip-chip connected to connect the protruding electrode to a wiring electrode of the wiring board;
And bonding a film wiring conductor integrally to the back surface of the first semiconductor element and the upper surface of the wiring board, and connecting an outer end of the wiring conductor of the film wiring conductor to a wiring electrode of the wiring board. A second step of: flip-chip-connecting a second semiconductor element having a projecting electrode to an electrode pad on the front surface of the first semiconductor element via the film wiring conductor to a back surface of the first semiconductor element; A third step of connecting an electrode and an inner end of the wiring conductor of the film wiring conductor, a fourth step of sealing an upper surface area of the wiring board with a sealing resin, A fifth step of performing a grinding process on a peripheral portion of the upper surface of the formed sealing resin to reduce a volume of the peripheral portion of the upper surface of the sealing resin.
載されるもので、また上面に個々の半導体素子に対応し
た配線電極が設けられ、下面には上面の配線電極と基板
内部で接続した端子電極が設けられ、個々の半導体素子
単位ごとに分割され得る構造の1枚の大型の配線基板に
対して、樹脂を介してその表面の電極パッドに突起電極
が形成された第1の半導体素子をフリップチップ接続
し、前記突起電極と前記配線基板の配線電極とを接続す
る第1の工程と、 前記第1の半導体素子の裏面および前記配線基板上面に
一体でフィルム配線導体を接着するとともに、前記フィ
ルム配線導体の配線導体の外方端部を前記配線基板の配
線電極と接続する第2の工程と、 前記第1の半導体素子の裏面に対して、前記フィルム配
線導体を介してその表面の電極パッドに突起電極が形成
された第2の半導体素子をフリップチップ接続し、前記
突起電極と前記フィルム配線導体の配線導体の内方端部
とを接続する第3の工程と、 前記配線基板の上面領域を封止樹脂で封止する第4の工
程と、 前記配線基板に対して、個々の積層型半導体装置に切断
分離するとともに、前記配線基板の上面に形成した封止
樹脂の上面周辺部に対して研削処理を行い、前記封止樹
脂の上面周辺部の体積を減じる第5の工程とよりなるこ
とを特徴とする積層型半導体装置の製造方法。6. A plurality of semiconductor elements are individually mounted on the upper surface, and wiring electrodes corresponding to the individual semiconductor elements are provided on the upper surface, and the lower surface is connected to the wiring electrodes on the upper surface inside the substrate. A first semiconductor element in which a protruding electrode is formed on an electrode pad on the surface of a large wiring board having a structure in which terminal electrodes are provided and which can be divided into individual semiconductor element units via resin. A first step of connecting the protruding electrodes and the wiring electrodes of the wiring board by flip-chip bonding, and bonding a film wiring conductor integrally to the back surface of the first semiconductor element and the top surface of the wiring board; A second step of connecting an outer end of the wiring conductor of the film wiring conductor to a wiring electrode of the wiring board; and a front surface of the first semiconductor element via the film wiring conductor with respect to a back surface of the first semiconductor element. A third step of flip-chip connecting a second semiconductor element having a protruding electrode formed on an electrode pad, and connecting the protruding electrode to an inner end of a wiring conductor of the film wiring conductor; A fourth step of sealing the upper surface region with a sealing resin, and cutting and separating the wiring substrate into individual stacked semiconductor devices, and a peripheral portion of an upper surface of the sealing resin formed on the upper surface of the wiring substrate And a grinding process for reducing the volume of the peripheral portion of the upper surface of the sealing resin.
ルム配線導体を介してその表面の電極パッドに突起電極
が形成された第2の半導体素子をフリップチップ接続
し、前記突起電極と前記フィルム配線導体の配線導体の
内方端部とを接続する第3の工程では、第2の半導体素
子を前記フィルム配線導体に対して加圧し、前記突起電
極で前記フィルム配線導体のフィルム材を突き破って前
記配線導体の内方端部とを接続することを特徴とする請
求項5または請求項6に記載の積層型半導体装置の製造
方法。7. A second semiconductor element having a protruding electrode formed on an electrode pad on the surface of the first semiconductor element via a film wiring conductor is flip-chip connected to the back surface of the first semiconductor element, and the protruding electrode is connected to the second electrode. In the third step of connecting the film wiring conductor to the inner end of the wiring conductor, the second semiconductor element is pressed against the film wiring conductor, and the projecting electrode breaks through the film material of the film wiring conductor. 7. The method for manufacturing a stacked semiconductor device according to claim 5, wherein the wiring conductor is connected to an inner end of the wiring conductor.
上面に一体でフィルム配線導体を接着するとともに、前
記フィルム配線導体の配線導体の外方端部を前記配線基
板の配線電極と接続する第2の工程では、配線導体を軟
性樹脂で挟んだ構造のフィルム配線導体を用いることを
特徴とする請求項5または請求項6に記載の積層型半導
体装置の製造方法。8. A method of bonding a film wiring conductor integrally to a back surface of the first semiconductor element and an upper surface of the wiring board, and connecting an outer end of the wiring conductor of the film wiring conductor to a wiring electrode of the wiring board. 7. The method according to claim 5, wherein in the step (2), a film wiring conductor having a structure in which the wiring conductor is sandwiched between soft resins is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001087012A JP2002289769A (en) | 2001-03-26 | 2001-03-26 | Stacked semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001087012A JP2002289769A (en) | 2001-03-26 | 2001-03-26 | Stacked semiconductor device and method of manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002289769A true JP2002289769A (en) | 2002-10-04 |
Family
ID=18942308
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001087012A Withdrawn JP2002289769A (en) | 2001-03-26 | 2001-03-26 | Stacked semiconductor device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002289769A (en) |
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| US9093435B2 (en) | 2011-05-03 | 2015-07-28 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
| US10593643B2 (en) | 2011-05-03 | 2020-03-17 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
| US10062661B2 (en) | 2011-05-03 | 2018-08-28 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
| US12494453B2 (en) | 2011-05-03 | 2025-12-09 | Adeia Semiconductor Solutions Llc | Package-on-package assembly with wire bonds to encapsulation surface |
| US11424211B2 (en) | 2011-05-03 | 2022-08-23 | Tessera Llc | Package-on-package assembly with wire bonds to encapsulation surface |
| US9041227B2 (en) | 2011-10-17 | 2015-05-26 | Invensas Corporation | Package-on-package assembly with wire bond vias |
| US8836136B2 (en) | 2011-10-17 | 2014-09-16 | Invensas Corporation | Package-on-package assembly with wire bond vias |
| US11735563B2 (en) | 2011-10-17 | 2023-08-22 | Invensas Llc | Package-on-package assembly with wire bond vias |
| US9252122B2 (en) | 2011-10-17 | 2016-02-02 | Invensas Corporation | Package-on-package assembly with wire bond vias |
| US9761558B2 (en) | 2011-10-17 | 2017-09-12 | Invensas Corporation | Package-on-package assembly with wire bond vias |
| US10756049B2 (en) | 2011-10-17 | 2020-08-25 | Invensas Corporation | Package-on-package assembly with wire bond vias |
| US11189595B2 (en) | 2011-10-17 | 2021-11-30 | Invensas Corporation | Package-on-package assembly with wire bond vias |
| US9842745B2 (en) | 2012-02-17 | 2017-12-12 | Invensas Corporation | Heat spreading substrate with embedded interconnects |
| US9349706B2 (en) | 2012-02-24 | 2016-05-24 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
| US9691679B2 (en) | 2012-02-24 | 2017-06-27 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
| US10510659B2 (en) | 2012-05-22 | 2019-12-17 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
| US9953914B2 (en) | 2012-05-22 | 2018-04-24 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
| US8835228B2 (en) | 2012-05-22 | 2014-09-16 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
| US10170412B2 (en) | 2012-05-22 | 2019-01-01 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
| US9917073B2 (en) | 2012-07-31 | 2018-03-13 | Invensas Corporation | Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package |
| US9391008B2 (en) | 2012-07-31 | 2016-07-12 | Invensas Corporation | Reconstituted wafer-level package DRAM |
| US10297582B2 (en) | 2012-08-03 | 2019-05-21 | Invensas Corporation | BVA interposer |
| US9502390B2 (en) | 2012-08-03 | 2016-11-22 | Invensas Corporation | BVA interposer |
| US8975738B2 (en) | 2012-11-12 | 2015-03-10 | Invensas Corporation | Structure for microelectronic packaging with terminals on dielectric mass |
| US8878353B2 (en) | 2012-12-20 | 2014-11-04 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
| US9615456B2 (en) | 2012-12-20 | 2017-04-04 | Invensas Corporation | Microelectronic assembly for microelectronic packaging with bond elements to encapsulation surface |
| US9095074B2 (en) | 2012-12-20 | 2015-07-28 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
| US9601454B2 (en) | 2013-02-01 | 2017-03-21 | Invensas Corporation | Method of forming a component having wire bonds and a stiffening layer |
| US8883563B1 (en) | 2013-07-15 | 2014-11-11 | Invensas Corporation | Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation |
| US9633979B2 (en) | 2013-07-15 | 2017-04-25 | Invensas Corporation | Microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation |
| US9023691B2 (en) | 2013-07-15 | 2015-05-05 | Invensas Corporation | Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation |
| US9034696B2 (en) | 2013-07-15 | 2015-05-19 | Invensas Corporation | Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation |
| US10460958B2 (en) | 2013-08-07 | 2019-10-29 | Invensas Corporation | Method of manufacturing embedded packaging with preformed vias |
| US9685365B2 (en) | 2013-08-08 | 2017-06-20 | Invensas Corporation | Method of forming a wire bond having a free end |
| US10008477B2 (en) | 2013-09-16 | 2018-06-26 | Invensas Corporation | Microelectronic element with bond elements to encapsulation surface |
| US9082753B2 (en) | 2013-11-12 | 2015-07-14 | Invensas Corporation | Severing bond wire by kinking and twisting |
| US9893033B2 (en) | 2013-11-12 | 2018-02-13 | Invensas Corporation | Off substrate kinking of bond wire |
| US9087815B2 (en) | 2013-11-12 | 2015-07-21 | Invensas Corporation | Off substrate kinking of bond wire |
| US9728527B2 (en) | 2013-11-22 | 2017-08-08 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
| US9852969B2 (en) | 2013-11-22 | 2017-12-26 | Invensas Corporation | Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects |
| USRE49987E1 (en) | 2013-11-22 | 2024-05-28 | Invensas Llc | Multiple plated via arrays of different wire heights on a same substrate |
| US10629567B2 (en) | 2013-11-22 | 2020-04-21 | Invensas Corporation | Multiple plated via arrays of different wire heights on same substrate |
| US10290613B2 (en) | 2013-11-22 | 2019-05-14 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
| US10026717B2 (en) | 2013-11-22 | 2018-07-17 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
| US9583411B2 (en) | 2014-01-17 | 2017-02-28 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
| US11404338B2 (en) | 2014-01-17 | 2022-08-02 | Invensas Corporation | Fine pitch bva using reconstituted wafer with area array accessible for testing |
| US11990382B2 (en) | 2014-01-17 | 2024-05-21 | Adeia Semiconductor Technologies Llc | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
| US9837330B2 (en) | 2014-01-17 | 2017-12-05 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
| US10529636B2 (en) | 2014-01-17 | 2020-01-07 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
| US9214454B2 (en) | 2014-03-31 | 2015-12-15 | Invensas Corporation | Batch process fabrication of package-on-package microelectronic assemblies |
| US9356006B2 (en) | 2014-03-31 | 2016-05-31 | Invensas Corporation | Batch process fabrication of package-on-package microelectronic assemblies |
| US9812433B2 (en) | 2014-03-31 | 2017-11-07 | Invensas Corporation | Batch process fabrication of package-on-package microelectronic assemblies |
| US10381326B2 (en) | 2014-05-28 | 2019-08-13 | Invensas Corporation | Structure and method for integrated circuits packaging with increased density |
| US9646917B2 (en) | 2014-05-29 | 2017-05-09 | Invensas Corporation | Low CTE component with wire bond interconnects |
| US10032647B2 (en) | 2014-05-29 | 2018-07-24 | Invensas Corporation | Low CTE component with wire bond interconnects |
| US10475726B2 (en) | 2014-05-29 | 2019-11-12 | Invensas Corporation | Low CTE component with wire bond interconnects |
| US9947641B2 (en) | 2014-05-30 | 2018-04-17 | Invensas Corporation | Wire bond support structure and microelectronic package including wire bonds therefrom |
| US9412714B2 (en) | 2014-05-30 | 2016-08-09 | Invensas Corporation | Wire bond support structure and microelectronic package including wire bonds therefrom |
| KR102181013B1 (en) * | 2014-09-05 | 2020-11-19 | 삼성전자주식회사 | Semiconductor Package |
| KR20160029422A (en) * | 2014-09-05 | 2016-03-15 | 삼성전자주식회사 | Semiconductor Package |
| US9735084B2 (en) | 2014-12-11 | 2017-08-15 | Invensas Corporation | Bond via array for thermal conductivity |
| US9888579B2 (en) | 2015-03-05 | 2018-02-06 | Invensas Corporation | Pressing of wire bond wire tips to provide bent-over tips |
| US10806036B2 (en) | 2015-03-05 | 2020-10-13 | Invensas Corporation | Pressing of wire bond wire tips to provide bent-over tips |
| US10008469B2 (en) | 2015-04-30 | 2018-06-26 | Invensas Corporation | Wafer-level packaging using wire bond wires in place of a redistribution layer |
| US9761554B2 (en) | 2015-05-07 | 2017-09-12 | Invensas Corporation | Ball bonding metal wire bond wires to metal pads |
| US9812402B2 (en) | 2015-10-12 | 2017-11-07 | Invensas Corporation | Wire bond wires for interference shielding |
| US10559537B2 (en) | 2015-10-12 | 2020-02-11 | Invensas Corporation | Wire bond wires for interference shielding |
| US10115678B2 (en) | 2015-10-12 | 2018-10-30 | Invensas Corporation | Wire bond wires for interference shielding |
| US10490528B2 (en) | 2015-10-12 | 2019-11-26 | Invensas Corporation | Embedded wire bond wires |
| US11462483B2 (en) | 2015-10-12 | 2022-10-04 | Invensas Llc | Wire bond wires for interference shielding |
| US10332854B2 (en) | 2015-10-23 | 2019-06-25 | Invensas Corporation | Anchoring structure of fine pitch bva |
| US10181457B2 (en) | 2015-10-26 | 2019-01-15 | Invensas Corporation | Microelectronic package for wafer-level chip scale packaging with fan-out |
| US10043779B2 (en) | 2015-11-17 | 2018-08-07 | Invensas Corporation | Packaged microelectronic device for a package-on-package device |
| US9911718B2 (en) | 2015-11-17 | 2018-03-06 | Invensas Corporation | ‘RDL-First’ packaged microelectronic device for a package-on-package device |
| US9659848B1 (en) | 2015-11-18 | 2017-05-23 | Invensas Corporation | Stiffened wires for offset BVA |
| US9984992B2 (en) | 2015-12-30 | 2018-05-29 | Invensas Corporation | Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces |
| US10325877B2 (en) | 2015-12-30 | 2019-06-18 | Invensas Corporation | Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces |
| US9935075B2 (en) | 2016-07-29 | 2018-04-03 | Invensas Corporation | Wire bonding method and apparatus for electromagnetic interference shielding |
| US10658302B2 (en) | 2016-07-29 | 2020-05-19 | Invensas Corporation | Wire bonding method and apparatus for electromagnetic interference shielding |
| US10299368B2 (en) | 2016-12-21 | 2019-05-21 | Invensas Corporation | Surface integrated waveguides and circuit structures therefor |
| CN113540068A (en) * | 2021-07-20 | 2021-10-22 | 甬矽电子(宁波)股份有限公司 | Device stack packaging structure and device stack packaging method |
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