JP2002288150A - Semiconductor integrated circuit device - Google Patents

Abstract

[PROBLEMS] To provide a semiconductor integrated circuit device capable of realizing both high performance, low power consumption, and low leakage current. A semiconductor integrated circuit has a high performance CPUA.
101, a low-power-consumption CPUB 102, a processing-content determining unit 103 that determines which CPU is best to use in accordance with the processing content, and a power supply for a CPU that executes processing based on the determination result and is not involved in the processing. A power supply voltage controller 104 for controlling voltage and clock supply and a clock supply controller 105 are provided. CPU that does not perform processing
By shutting off the power supply, the leakage current can be reduced,
Power consumption can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art In recent years, the miniaturization of semiconductor manufacturing technology has advanced,
Power supply voltages applied to semiconductor integrated circuits tend to decrease. Accordingly, the threshold voltage tends to decrease as miniaturization advances in order to realize operation as a transistor. As the threshold voltage decreases, the leak current between the source and the drain increases. In order to realize a transistor with higher performance, it is necessary to further lower the threshold voltage, and the leakage current increases more and more. In the miniaturization process, this leakage current is LS
I is becoming a major cause of the increase in power consumption. Therefore, in order to realize low power consumption of the LSI in the miniaturization process, it is necessary to not only reduce the power during operation but also
Another important issue is to reduce the leak current.

As a method of reducing the leak current, a method of reducing the leak current by increasing the threshold voltage of the transistor, a method of controlling the back gate bias such as a VTCMOS to make the threshold voltage controllable, and A method for reducing the leak current and increasing the speed during operation, and further, as described in Japanese Patent Application Laid-Open No. 05-29551, are designed so that the power supply can be turned on / off for each functional block constituting the LSI, and individual functions are designed. When the block does not need to operate, there is a method of turning off the power supply to reduce the leak current.

When the miniaturization is further advanced, not only the conventional leakage current between the drain and the source but also the leakage current from the gate becomes remarkable. This is largely attributable to the thinning of the gate oxide film thickness and the like accompanying the miniaturization. The best way to reduce the gate leakage is to turn off the power as described in the above-mentioned Japanese Patent Application Laid-Open No. 05-29551. Method.

[0005]

However, when the threshold voltage of the transistor is increased to reduce the leak current, there is an advantage in terms of power reduction, but it becomes difficult to realize high performance.

Further, with respect to a method of controlling a back gate bias and changing a threshold voltage depending on an operation mode like a VTCMOS, when scaling for improving the operation speed of a circuit is performed after a 0.10 μm generation process, the back gate bias is reduced. The dependence of the threshold voltage on the gate bias voltage tends to decrease.Thus, even if the back gate bias voltage control technology is used, the threshold voltage cannot be changed sufficiently, and it is necessary to reduce the leakage current or improve the performance. It becomes difficult to plan.

[0007] Today, with the advance of miniaturization of the semiconductor manufacturing process, it has become possible to realize a system LSI capable of realizing a complex system on one chip.
Millions and tens of millions of transistors will be mounted on one chip, and when considering leakage current on one chip,
The absolute value of the leakage current will increase significantly. Therefore, how to reduce this leakage current is a major issue in the design of a system LSI. On the other hand, high performance is also required in order to realize the operation of the system LSI, and it is a big issue to achieve both low leakage current and high performance in realizing the system LSI.

It is therefore an object of the present invention to provide a semiconductor integrated circuit device capable of realizing both high performance, low power consumption and low leakage current.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device including two CPUs and a plurality of functional blocks, wherein one of the CPUs achieves high performance. The other one is a CPU that realizes low power consumption, a processing content determining unit that determines which of the two CPUs performs the processing executed in the semiconductor integrated circuit device, and a semiconductor integrated circuit device. A power supply voltage control management unit that manages power supply to a plurality of functional blocks based on the processing content of a processing content determination unit; and two CPUs mounted in a semiconductor integrated circuit. And a clock supply control unit that controls clock supply to a plurality of functional blocks in accordance with the processing content of the processing content determination unit, and two clocks based on the processing content of the processing content determination unit. CPU when at least one of the power supply voltage U is cut off, the required information is the power supply voltage is cut off
A backup memory is provided which enables more necessary information to be transferred to the CPU which raises the power supply voltage when the power supply voltage of at least one of the two CPUs is raised.

As described above, in order to solve the above-mentioned problems, according to the present invention, for example, a high-performance CPU (CPUA) and a low-performance but low-leakage-current, low-power-consumption CPU (CPUB) are used as CPUs constituting a system LSI. Two types of CP
U, and the contents processed by the system LSI are divided into those that require high performance and those that do not require performance but require constant operation, and each process requires high performance. The processing is performed by a high-performance CPU, and the processing that requires constant operation is executed by a low-power-consumption CPU. When the processing is not executed, the CPU is turned off to reduce the leak current.

In order to realize the above processing, the system LSI of the present invention comprises a high performance CPU and a low power consumption C
PU, a processing content determining unit that determines which CPU should perform the processing to be performed, a power supply voltage control unit that controls power on / off based on the determination information, and turns off each CPU. A memory for backing up information when necessary to back up register information and memory information.

According to the semiconductor integrated circuit device of the first aspect, it is possible to optimally select a CPU to be used according to the processing content actually executed in the semiconductor integrated circuit. Using a CPU for performance,
For other processing, use the low power consumption CPU,
At that time, measures such as leakage current can be taken by cutting off the voltage applied to the CPU for high performance, and even in today's system LSI where the process is miniaturized, it is possible to automate both high performance and low power consumption. It becomes possible.

According to a second aspect of the present invention, there is provided the semiconductor integrated circuit device according to the first aspect, wherein the processing content determining unit is configured to input a processing content to be executed by two CPUs provided in the semiconductor integrated circuit device. A processing content storage unit that stores the correspondence between the processing content input via the processing content input unit and the CPU that executes the processing, and a processing content information input from the processing content input unit and stored in the processing content storage unit . A processing content comparison unit that performs comparison processing with information and determines a CPU to execute the processing content, and a CP that executes a CPU startup process for the processing execution CPU determined by the processing content comparison unit
It includes a U start unit and a data load processing unit that performs a load process of information loaded in the backup memory to the processing execution CPU determined by the processing content comparison unit.

According to the semiconductor integrated circuit device of the second aspect, the same effect as that of the first aspect is obtained.

According to a third aspect of the present invention, there is provided a semiconductor integrated circuit device comprising:
A semiconductor integrated circuit device including one CPU and a plurality of functional blocks, wherein one of the CPUs is a first CPU realizing high performance, and the other is a second CPU realizing low power consumption. The other one is a third CPU for controlling processing executed in the semiconductor integrated circuit device, and a third CPU for controlling processing in the semiconductor integrated circuit device.
A processing content control unit that executes a processing procedure determined by software executed by the CPU, three CPUs mounted in the semiconductor integrated circuit device, and power supply to a plurality of functional blocks. A power supply voltage control management unit that manages each CPU and each functional block based on the processing content of the above, three CPUs mounted on the semiconductor integrated circuit device, and clock supply to a plurality of functional blocks; A clock supply control unit that controls each CPU and function block based on the processing content of the unit, and a power supply voltage of at least one of the three CPUs based on the processing content of the processing content control unit. The necessary information is stored by the CPU whose power supply voltage is cut off, and the power supply is used when at least one of the three CPUs is powered up. Those having a backup memory that allows the transfer of necessary information to launch the pressure CPU.

According to the semiconductor integrated circuit device of the third aspect, the execution of the processing can be performed in more detail by executing the determination of the processing content by the third CPU. By making the software soft, the software is changed according to the user, so that the optimal low power consumption for each user is realized, and the generalization of the power reduction can be realized.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIGS. 1 to 3 show a first embodiment of the present invention.
This will be described below. FIG. 1 shows a first embodiment of the semiconductor integrated circuit device of the present invention.

In this semiconductor integrated circuit device, the CPUA
Reference numeral 101 denotes a high-performance CPU, which consumes a large amount of power, has a large area, and has a large number of transistors. On the other hand, the CPUB 102 is a CPU that realizes low power consumption, and has a considerably smaller performance than the CPUA 101 in terms of performance in order to realize low power consumption, but has a smaller area and a smaller number of transistors.

Peripheral circuits A1 111 and A2 1
Reference numeral 12 denotes a peripheral circuit used only by the CPUA 101; peripheral circuits B1 107 and B2 108 are peripheral circuits used only by the CPU B102; peripheral circuits 1 109 and 2110;
1. Peripheral circuits commonly used by the CPUB102.

The processing content determining unit 103 determines which CPU should execute the processing to be executed.

The backup memory 106 is provided by the power supply voltage control unit 104 when the CPU becomes unnecessary.
Power is cut off, but when there is information before the power is turned off when the CPU is restarted the next time the CPU is in the operating state, it is for backing up its contents, Normally, information on the state of the register of each CPU and the contents of the memory 106 are backed up. Further, a clock is supplied to the memory 106 only when an access to the memory 106 occurs, and the power supply voltage is fully applied. When there is no backup data, the clock and voltage are not supplied. When the data is not retained, the clock supply is stopped and the power supply voltage is given only the minimum necessary for data retention. It has become. This is all realized by the power supply voltage control unit 104 and the clock supply control unit 105. As a result, power reduction of the entire system is realized.

The power supply voltage control section 104 is a processing content determination section 1
Control such as turning on / off the power supply voltage and changing the voltage is performed based on the result of step S03. For example, when the power supply of the CPUA 101 is cut off, the power supply related to the CPU A 101 is cut off after the backup of the information necessary for the CPU A 101 in the backup memory 106 is completed.

The clock supply control unit 105 controls a path for supplying a clock, a path for stopping the clock, a path for changing the frequency, and the like in accordance with the determination result of the processing content determination unit 103.

The processing contents of the present invention in a semiconductor integrated circuit composed of these blocks will be described in detail.

In this semiconductor integrated circuit device, the CP
It is assumed that the UB 102 operates constantly, and the CPU A 101 is used or not depending on the processing content.

When only the CPU B 102 is operating, the CPU A 101, the peripheral circuit A 1111, and the peripheral circuit A
The power supply 2 112 is turned off by the power supply voltage control unit 104 so that no leak current is consumed. In addition, as described above, the backup memory is also subjected to the optimal processing to reduce power consumption. Here, when a process requiring high performance is interrupted, the process content determination unit 103 recognizes the interruption and executes a process for starting use of the CPUA 101. First, the power supply voltage control unit 104
And its peripheral circuits A1 111 and A2 112
Then, the clock control unit 105 starts supplying a clock to the CPU A 101 and its peripheral circuits A 111 and A 2112. After these operations are stabilized, the clock control unit 105 and the power supply voltage control unit 104 supply the power supply voltage and the clock to the backup memory 106, and the contents of the backup memory 106 related to the CPUA101 are transmitted from the CPUA101. And the loading operation is actually started. After the loading is completed, the power supply and the clock supply to the backup memory 106 change to the optimum ones depending on the presence or absence of the backup data.

Next, the CPUA 101 and the peripheral circuit 11
The processing which actually requires high performance is performed and completed using the steps 1 and 112. After this processing is completed, the CPU A1
When the processing content determination unit 103 confirms that there is only processing that does not need to be performed in
The procedure for turning off the power is started. Here, first, information that needs to be backed up is managed in the backup memory 106. At this time, the supply of the power supply voltage and the supply of the clock to the backup memory 106 are controlled and executed as in the case of loading the data. After the backup is completed, the supply of the power supply voltage supplied to the system of the CPUA 101 is cut off by the power supply voltage control unit 104. As described above, in a normal operation, a state in which power is supplied only to low power consumption functions on the system LSI is created, and power is also supplied to the high performance circuit unit only when high performance processing is required. Thus, the leakage current can be greatly reduced. Such a system LSI can exert its capabilities to the maximum by being mounted on a product that combines mobile communication and image data processing, which is called mobile multimedia in the future. When applied to this patent, CPUA10
Reference numeral 1 denotes a processor for performing image processing and other applications, and the CPUB 102 is a processor that performs basic processing of mobile communication, thereby achieving system optimization.

Further, the leakage current can be further reduced by increasing the threshold voltage of the transistor constituting the CPUB 102 up to the limit satisfying the performance required of the CPUB102.

FIG. 2 shows a processing content judging section 1 shown in FIG.
03 shows an example of the configuration diagram. FIG. 3 shows an example of a list of the processing contents and which CPU executes the processing, which is managed by the processing content storage unit 201 in the processing content determination unit 103.

In FIG. 2, CPUA101, CPUB
102, the content of the process to be actually run is input to the process content input unit 200, and this information is compared with the information stored in the process content storage unit 202 by the process content comparison unit 201. It is determined whether the process should be started. If the result of the determination is that the process should use the CPUA 101, the CPUA starting unit 203 is first executed. At this time, first, the power control unit 10
4. Send information to the clock control unit 105 to activate the CPU A101. As a result, after the CPU A 101 has started up, the data load processing unit 205 loads data from the backup memory 106 to the CPU A 101. As a result, processing in the CPU A101 becomes possible.

Next, when a process not using the CPUA 101 comes, the CPUA stopping unit 204 is executed. At this time, the backup processing unit 206
1 transfers necessary information to the backup memory 106 for storage. Next, information to stop the CPU 101 is sent to the power supply voltage control unit 104 and the clock control unit 105.

Thus, the power supply voltage of the CPU A101 can be cut off in a state where the storage of the backup information is completed and the CPU A101 can be started next.

FIG. 4 shows a second embodiment of the present invention.
FIG. 4 shows a second embodiment of the semiconductor integrated circuit device of the present invention.

In this semiconductor integrated circuit device, CPUA
Reference numeral 101 denotes a CPU that realizes high performance, which consumes a large amount of power and has a large area and a large number of transistors due to the realization of the configuration. On the other hand, the CPUB 102 is a CPU that realizes low power consumption, and has a considerably smaller performance than the CPUA 101 in terms of performance in order to realize low power consumption, but has a smaller area and a smaller number of transistors. Further, the CPU C 401 is composed of the CPU A 101 and the CPU B
The process 102 is used to determine which of the processes is to be used, and has low performance and low power consumption.

The difference between the first embodiment shown in FIG. 1 and FIG. 4 is that the processing content determination unit 103 becomes a processing content control unit 400, and a CPU C401 and a ROM 402 for storing a control program to be executed by the CPU C401 are added. The power supply voltage control unit 104 and the clock supply control unit 105
Is that all functional blocks can be individually controlled. The backup memory also shuts off the CPU C401 and performs backup at startup.

Referring to FIG. 4, the CPU C 401 determines the processing content, determines in detail which CPU and which peripheral circuit to use, and uses the information to cause the processing content control section 400 to control the power supply voltage control section 104 and the clock. Supply control unit 105
Power on / off, voltage value,
By controlling the clock frequency and the like, further lower power consumption can be realized.

Also in the semiconductor integrated circuit device shown in FIG. 4, the CPUB 102 is assumed to always operate, and the CPUA 101 is used or not depending on the processing contents.

When only the CPUB102 is operating, the CPUA101, the peripheral circuit A1111 and the peripheral circuit A
The power supply 2 112 is individually turned off by the power supply voltage control unit 104 so that no leak current is consumed. At this time, the peripheral B1 107 and the peripheral B2 1
08, peripheral 1109, etc., can be turned off depending on the situation. Optimal processing is applied to the backup memory as described with reference to FIG. 1, thereby reducing power consumption. Here, when a process requiring high performance is interrupted, the CPUC 401 evaluates the content of the process and determines which CPU and which peripheral circuit to use. Here, CPU
Assume that it is determined that A101 and peripheral A2 112 are to be used. Based on this information, the processing content control unit 400
A process for starting use of the PUA 101 and the peripheral A2 112 is executed. First, the power supply voltage controller 104
The power supply to the PUA 101 and the peripheral circuit A2 112 is started.
1 and the supply of the clock to the peripheral circuit A2 112 are started. After these operations are stabilized, the clock control unit 1
05, the backup memory 1 from the power supply voltage control unit 104
The power supply voltage and the clock are supplied to the CPU 06, and the contents of the backup memory 106 related to the CPU A101 can be loaded from the CPU A101, and the loading operation is actually started. After the loading is completed, the power supply and the clock supply to the backup memory 106 change to the optimum ones depending on the presence or absence of the backup data.

Next, the CPU A101 and the peripheral A21
12, the processing that actually requires high performance is performed and completed. After the completion of this processing, the CPU C 401 confirms that there is only processing that does not need to be subsequently performed by the CPU A 101.
When the confirmation is made, the processing content control unit 400 enters a procedure for powering off the CPU A 101 and the peripheral A 2 112 based on this information. Here, first, information that needs to be backed up is managed in the backup memory 106. At this time, the supply of the power supply voltage and the supply of the clock to the backup memory 106 are controlled and executed as in the case of loading the data. After backup is completed, CPU
The supply of the power supply voltage to the system of A101 is cut off by the power supply voltage control unit 104.

As described above, the execution of the processing by the CPU C 401 is determined, so that the execution of the processing can be shared in more detail. In addition, by making this determination software, it is possible to respond to the user. By changing the software, power consumption optimal for each user is realized, and generalization of power reduction can be realized.

As described above, according to the present invention, the system L
At the initial stage of SI design, the correspondence between the processing content and the CPU that executes it is clarified and stored in the circuit,
Even in today's system LSI in which process miniaturization is progressing, it is possible to automate both high performance and low power consumption. Also, by using software to select a circuit to be used in accordance with the processing content, a system LSI can be provided for each user.
Optimum use of low power consumption becomes possible.

[0043]

According to the semiconductor integrated circuit device of the first aspect, it is possible to optimally select a CPU to be used according to the processing content actually executed in the semiconductor integrated circuit. A high-performance CPU is used, and a low-power CPU is used for other processing. At that time, the voltage applied to the high-performance CPU is cut off, thereby making it possible to take measures such as a leak current. In today's system LSIs, which have become finer, it is possible to automate both high performance and low power consumption.

According to the semiconductor integrated circuit device of the second aspect, the same effect as that of the first aspect is obtained.

According to the semiconductor integrated circuit device of the third aspect, the execution of the processing can be performed in more detail by executing the determination of the processing content by the third CPU. By making the software soft, the software is changed according to the user, so that the optimal low power consumption for each user is realized, and the generalization of the power reduction can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a processing content determination unit according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram illustrating a processing content table stored in a processing content storage unit according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a semiconductor integrated circuit device according to a second embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 semiconductor integrated circuit device 101 high-performance CPUA 102 high-performance CPUB 103 processing content determination unit 104 power supply voltage control unit 105 clock control unit 106 backup memory 107 peripheral circuit B1 108 peripheral circuit B2 109 peripheral circuit 1 110 peripheral circuit 2 111 peripheral circuit A1 112 Peripheral circuit A2

Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) G06F 12/16 G06F 15/16 620A 5B098 15/16 620 1/00 332B F term (reference) 5B011 EA09 FF01 JA06 LL13 5B018 GA04 KA03 NA10 QA05 5B045 CC04 GG02 GG06 KK02 KK08 5B062 AA03 AA05 CC04 DD10 HH01 HH04 5B079 AA06 BA12 BC01 DD13 DD20 5B098 AA10 BB11 BB20 DD01 DD08 GD02

Claims (3)

[Claims] 1. A semiconductor integrated circuit device having two CPUs and a plurality of functional blocks, wherein one of the CPUs is a CPU that realizes high performance, and the other one is that that realizes low power consumption. A processing content determining unit that determines which of the two CPUs should execute processing executed in the semiconductor integrated circuit device; and the two Cs mounted on the semiconductor integrated circuit device.
A power supply voltage control management unit that manages power supply to the PU and the plurality of functional blocks based on the processing content of the processing content determination unit; and the two CPs mounted on the semiconductor integrated circuit.
U, and clock supply to the plurality of functional blocks,
A clock supply control unit that performs control based on the processing content of the processing content determination unit; and the two Cs based on the processing content of the processing content determination unit.
When at least one power supply voltage of the PU is cut off, necessary information is stored by the CPU whose power supply voltage is cut off, and the power supply voltage is raised when the power supply voltage of at least one of the two CPUs is raised. Semiconductor integrated circuit device having a backup memory capable of transferring necessary information to the CPU A processing content input unit that inputs processing content to be executed by two CPUs provided in the semiconductor integrated circuit device; and a processing content input via the processing content input unit. A processing content storage unit that stores a correspondence relationship between the CPUs that execute the processing, a comparison process between processing content information input from the processing content input unit and information stored in the processing content storage unit, and Processing comparison unit for determining a CPU to execute the processing, and a processing execution CP determined by the processing content comparison unit
A CPU activating unit for performing a CPU activating process on U; a process execution CP determined by the process content comparing unit
2. The semiconductor integrated circuit device according to claim 1, further comprising: a data load processing unit that performs a load process on information mounted on a backup memory for U. 3. A semiconductor integrated circuit device having three CPUs and a plurality of functional blocks, wherein one of the CPUs is a first CPU realizing high performance, and the other one is low power consumption. And a third CPU that controls processing executed in the semiconductor integrated circuit device, and a second CPU that controls the processing executed in the semiconductor integrated circuit device. A processing content control unit that executes a processing procedure determined by software executed by the CPU of the third integrated circuit; and the three Cs mounted on the semiconductor integrated circuit device.
A power supply voltage control management unit that manages a power supply to the PU and the plurality of functional blocks for each CPU and each functional block based on the processing content of the processing content control unit; and a power supply voltage control management unit mounted on the semiconductor integrated circuit device. Said three C
The clock supply to the PU and the plurality of functional blocks is controlled based on the processing content of the processing content control unit.
A clock supply control unit that controls each PU and each functional block; and based on the processing content of the processing content control unit, when the power supply voltage of at least one of the three CPUs is cut off, the power supply voltage A semiconductor device comprising a backup memory that stores data from the CPU whose power is to be shut off, and that can transfer necessary information to the CPU that raises the power supply voltage when raising the power supply voltage of at least one of the three CPUs. Integrated circuit device.