JP2002287712A - Liquid crystal panel and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a TFT liquid crystal panel in which the uniformity of the gray scale due to the viewing angle characteristics of the gray scale or the wavelength dispersion of light can be avoided. SOLUTION: An offset voltage is applied on a pixel electrode 14 by the capacitance coupling through a storage capacitance 15 by changing the voltage on the gate signal line 11 among at least four potentials including the on and off potentials, and the size of the storage capacitance 15 is made to mutually differ for every specified number of rows or columns.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a liquid crystal panel which operates a liquid crystal by using a thin film transistor (TFT) as a driving element, and more particularly, to the uniformity of gradation of a liquid crystal panel using a TFT as a driving element. It relates to the improvement of.

[0002]

2. Description of the Related Art In recent years, a rapid market demand has arisen for a stationary monitor using a flat panel, a wall-mounted TV, and the like.
It is as large as a DP. However, in such applications, a large size and a high performance / high image quality comparable to a CRT are required at the same time, and the development of a large liquid crystal panel has the following image quality problems.

[0003] First, as the size of the liquid crystal panel increases, the prospective angle of viewing the entire screen from one viewpoint increases, and there is a problem that a difference in brightness occurs between the upper and lower parts of the screen due to the viewing angle characteristics of the liquid crystal panel. Especially TN (Twisted Nemati)
In the case of the c) mode TFT liquid crystal panel, since the viewing angle dependence of the gradation characteristics between the upper and lower parts of the screen is large, the expected angle is about 5 ° to 3 °.
Even at 0 °, a luminance difference occurs in the vertical direction of the screen.

On the other hand, in order to greatly improve visual characteristics, T
Change the operation mode of FT liquid crystal panel from TN mode to IPS
(In Plane Switching) mode has been proposed and has already been put to practical use. In this mode, the liquid crystal is driven in the horizontal direction of the substrate by generating a horizontal electric field on the TFT substrate. The viewing angle characteristics are greatly improved as compared with the TN mode in which the liquid crystal is driven in the vertical direction of the substrate. Therefore, if the IPS mode is used, the problem of the luminance difference between the top and bottom of the screen due to the enlargement of the liquid crystal panel can be solved.

However, in the IPS mode liquid crystal panel, there is a problem that the wavelength characteristic of the gradation characteristic is large due to the normally black panel configuration. Gradation characteristics,
That is, the relationship between the liquid crystal panel transmittance and the applied voltage depends on the retardation (birefringence) value of the liquid crystal layer, but the retardation of the liquid crystal layer changes depending on the wavelength of light. For this reason, the gradation characteristic greatly changes between the red, green, and blue pixels,
In particular, there is a problem in that the gradation is inverted depending on the color in the gradation part with high transmittance (bright luminance).

In both the TN mode and the IPS mode, the wiring resistance and capacitance of the gate signal lines and the source signal lines increase as the screen size increases. Therefore, the input drive signal waveform is distorted between the input side and the terminal side (the waveform shapes do not match). As a result, TF
The ON voltage waveform for driving T also becomes dull, and crosstalk occurs due to insufficient ON voltage, insufficient capacity, and insufficient time. Furthermore, in-plane non-uniformity of the shape and size of the TFT occurs due to the increase in size (process and equipment factors). as a result,
The parasitic capacitance becomes non-uniform in the screen, and flicker occurs.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and has a TFT which can eliminate non-uniformity in gradation due to viewing angle characteristics and light wavelength dispersion. It is intended to provide a liquid crystal panel. It is another object of the present invention to provide a TFT liquid crystal panel capable of suppressing the occurrence of flicker and crosstalk due to an increase in screen size.

[0008]

In order to achieve the above object, a liquid crystal panel according to the present invention comprises the following steps: (1) changing the potential of a gate signal line or a common electrode line to a pixel electrode via a storage capacitor; Capacitive coupling drive for applying an offset voltage is performed. (2) By changing the storage capacity conventionally formed uniformly for each pixel depending on the screen position, display color, etc. of the pixel, the screen position of the liquid crystal panel is improved. This is for correcting unevenness of gradation for each display color.

First, the capacitive coupling drive, which is the first feature of the liquid crystal panel according to the present invention, will be described with reference to the structure of a general liquid crystal panel. FIG. 8 shows T in the TN mode.
It is a top view which shows the structure of the pixel part of the general TFT substrate used for FT liquid crystal panels. Pixel electrodes 84 are arranged in a matrix, a gate signal line 81 is formed in each row, and a source signal line 82 is formed in each column. A thin film transistor is formed at the intersection of the gate signal line 81 and the source signal line 82, and is connected to the pixel electrode 84 via the drain electrode 83. A storage capacitor 85 is formed by connecting to each pixel electrode 84, and each storage capacitor is connected to the gate signal line 81 in the preceding stage.

FIG. 12 shows an equivalent circuit for one pixel of the TFT substrate shown in FIG. In FIG. 12, 121 is n
-1st gate signal line, 122 is an nth gate signal line, 123 is a source signal line, 124 is a thin film transistor, 125 is a pixel electrode, 126 is a storage capacitor Cst, 12
Reference numeral 7 denotes a capacitance of the liquid crystal in the pixel portion, and reference numeral 128 denotes a parasitic capacitance Cgd formed between the drain electrode of the thin film transistor and the gate signal line. As shown in FIG.
25 and gate lines 121 and 122 are coupled by capacitors 126 and 128. Further, the thin film transistor 124 is in an off state except for a writing time to the pixel electrode. Therefore, when the potential of the gate lines 121 and 122 fluctuates, the gate lines 121 and 12
An offset voltage that compensates for the potential fluctuation of No. 2 is applied.

[0011] Capacitive coupling drive means that the potential of the gate signal line 121 of the (n-1) th stage is varied between four potentials including the ON potential and the OFF potential of the thin film transistor, thereby forming n
By positively applying an offset voltage due to capacitive coupling to the pixel electrode 125 of the stage through the storage capacitor 126, the liquid crystal 12
7 to increase the effective voltage. FIG. 13 shows an example of the voltage waveform of the gate signal line and the pixel electrode in the case of performing the capacitive coupling drive. In FIG. 13, 131 and 132 represent the potentials of the gate signal lines of the (n-1) th and nth stages, and 133 represents the potential of the pixel electrode. The gate signal line has a positive bias potential V in addition to the ON potential and the OFF potential.
_{ge (+)} and the negative bias potential _{Vge ( −)} total 4
Take one potential. The potentials 131 and 132 of the gate lines are
For example, if the timing is changed as shown in FIG.
The amplitude Vp of the potential 133 of the pixel electrode is approximately expressed by the following equation.

(Equation 1) In Equation (1), the first term on the right side (= Vs) represents the voltage written from the source signal line, and the second term on the right side represents the offset voltage applied via the storage capacitor.
As can be seen from equation (1), by performing the capacitive coupling drive, the effective voltage applied to the liquid crystal can be increased by the offset voltage.

When the storage capacitor 95 is formed between the common electrode line 96 instead of the gate line 91 as shown in FIG. 9, the potential of the common electrode line 96 is changed instead of the gate signal line 91. This also enables capacitive coupling drive. In this case, the potential of the common electrode line 96 is changed to the positive bias potential _{Vge (+)} and the negative bias potential _Vge.
The potential is changed between a total of two potentials ₍₋₎ . For example, the potential of the common electrode line 96 is set to _{Vge (+)} for each field.
And _{Vge (−)} , so that the potential of the common electrode line of the nth stage is inverted after the gate signal line of the nth stage is turned off. As a result, the same offset voltage as in equation (1) can be applied.

Further, as shown in FIG. 10 and FIG.
The following method is also used for the PS mode liquid crystal panel.
Thus, capacitive coupling driving can be performed. TN mode liquid crystal
In the panel, the counter electrode and the pixel electrode provided on the filter substrate
A voltage is applied between the poles in the vertical direction of the substrate,
The S-mode liquid crystal panel has a common power supply provided on the TFT substrate.
The point that voltage is applied in the horizontal direction of the substrate between the pole and the pixel electrode is
different. However, the capacity of the IPS mode liquid crystal panel is
The coupling drive method is exactly the same as the TN mode liquid crystal panel.
It is like. For example, an IPS mode liquid crystal panel shown in FIG.
The storage capacitor 105 is connected to the gate signal line 101
However, in this case, the potential of the gate signal line 101 is set to a thin film transistor.
Positive vias in addition to transistor on and off potentials
Potential V _{ge (+)}And the negative bias potential V_{ge (-)}
Capacitive coupling by changing between a total of four potentials
Driving can be performed. The IPS module shown in FIG.
In the liquid crystal panel, the storage capacitor 115 is connected to the common electrode line 116.
Are formed between the common electrode lines 116 in this case.
To the positive bias potential V_{ge (+)}And negative vias
Potential V_{ge (-)}Between two potentials
Thus, capacitive coupling driving can be performed.

It is necessary to set two positive and negative bias potentials for performing the capacitive coupling drive. However, two or more bias potentials may be provided.

Next, a description will be given of a second feature of the liquid crystal panel according to the present invention, namely, the point that the storage capacity is made different depending on the screen position and display color of the pixel. As shown in the above formula (1), the magnitude of the offset voltage in the capacitive coupling driving is proportional to the magnitude C _{s t} of the storage capacitor. Therefore, by varying the magnitude of the storage capacitance depending on the screen position, display color, and the like of the pixel, the magnitude of the offset voltage applied to each pixel can be individually controlled to correct non-uniform gradation between pixels. it can.

For example, when a luminance difference between the top and bottom of the screen based on the viewing angle characteristic occurs due to the expected angle of the liquid crystal panel, the magnitude of the storage capacity is gradually changed from top to bottom for each row. By doing so, the luminance difference can be corrected. In a normally white panel, when the upper part of the screen is dark and the lower part of the screen is bright, the size of the storage capacity formed in each row is gradually increased from the top to the bottom of the screen. If the upper part of the screen is bright and the lower part of the screen is dark, on the other hand, it gradually decreases from the top to the bottom of the screen.

In the case where nonuniform gradation occurs for each display color due to the wavelength dispersion of the retardation of the liquid crystal layer,
By changing the size of the storage capacitance of each pixel according to the display color of that pixel, the gradation difference between the display colors can be corrected. For example, when each pixel displays one of the three primary colors of red, green, and blue, and the applied voltage is apparently higher in the order of red>green> blue due to the wavelength dispersion of the retardation, blue>green> Increase the storage capacity in the order of red.

Further, in the liquid crystal panel according to the present invention, crosstalk and flicker of the liquid crystal panel are corrected by changing the design dimensions of the TFT which is conventionally formed uniformly for each pixel depending on the screen position of the pixel. Is preferred. That is, when the input drive waveform changes between the input side and the end side in the screen and crosstalk occurs, the TFT shape is optimized and designed so that the change can be corrected. In a portion where the ON capability is insufficient, the W / L is increased so that the insufficient capability can be corrected. Further, when the parasitic capacitance (C _gd area) in the screen changes due to process or equipment factors and flickers occur, the Cgd area of the TFT is optimized and designed in advance according to the distribution of the area change. Form. In a portion where the Cgd is formed large in the screen, the Cgd area is corrected so as to form a Cgd area corrected for the change. The reverse is also true.

Incidentally, the size of the storage capacitor for each pixel can be individually controlled by the shape of a photomask for forming the storage capacitor. For example, in the case where a storage capacitor is formed between a capacitance forming electrode connected to a pixel electrode and a gate signal line, the area where the capacitance forming electrode overlaps the gate signal line is changed on a photomask, so that the storage capacitance is changed. Can be changed. Similarly, the TFT W
The magnitudes of / L and Cgd can also be individually controlled by the shape of the photomask.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. Embodiment 1 FIG. FIG. 1 is a top view showing a pixel portion of a TFT substrate in the liquid crystal panel according to Embodiment 1 of the present invention. In the present embodiment, a configuration for correcting a luminance difference between a top and a bottom of a screen caused by an expected angle of the liquid crystal panel in a TN mode liquid crystal panel having a storage capacitor formed on a gate signal line is described. Here, a case where the upper part of the screen is dark and the lower part of the screen is bright in a TN mode liquid crystal panel of normally white display will be described as an example.

In a pixel portion of the TFT substrate, screen electrodes 14 are formed in a matrix, and a gate signal line 1 is provided for each row.
1, a source signal line 12 is formed for each column.
The gate signal line 11 is connected to the gate electrode and the source signal line 12 at a portion where the gate signal line 11 and the source signal line 12 intersect.
Is formed as a source electrode, and is electrically connected to the pixel electrode 14 via the drain electrode 13.

An electrode 15 for forming a storage capacitor is connected to the pixel electrode 14. The storage capacitor is formed by overlapping the electrode 15 with the previous gate line 11 via an insulating film. The storage capacitor forming electrode 15 is formed such that the overlapping area with the gate electrode 11 gradually increases for each row. This allows the storage capacity of each pixel to be:
It gradually increases from the top to the bottom of the screen.

The liquid crystal panel according to the present embodiment is capacitively coupled so that an offset voltage proportional to the storage capacitance is applied to each pixel electrode 14, and the gate signal line 11 is turned on, off, and positively biased. FIG. 10 shows the relationship between a total of four potentials of _{Vge (+)} and the negative bias potential _{Vge (−)} .
The waveform changes as shown in FIG. Therefore, the pixel electrode 1 of each row
The offset voltage applied to 4 gradually increases from the top to the bottom of the screen, and the luminance difference between the top and bottom of the screen is corrected.
Note that the inclination of the offset voltage amount in the vertical direction of the screen is determined by the heights _{Vge (+)} and _Vge of the bias potential of the gate signal line 11.
_{Ge (-)} . Therefore, by adjusting the setting of the bias potential of the gate signal line 11, the correction amount of the gradation in the vertical direction of the screen can be optimized.

According to the present embodiment, the offset application voltage amount for each gate signal line is optimized, and the difference in the gradation characteristics (luminance difference) due to the expected angle between the upper and lower sides of the screen (for each gate signal line) is reduced. As a result, one of the performance and quality issues in the large TFT-LCD can be improved.

Embodiment 2 FIG. 2 is a top view showing a pixel portion of a TFT substrate in a liquid crystal panel according to Embodiment 2 of the present invention. This embodiment shows a configuration for correcting a luminance difference between the upper and lower portions of a screen caused by an expected angle of a liquid crystal panel in a TN mode liquid crystal panel having a storage capacitor formed on a common electrode line. Incidentally, as in the first embodiment,
An example in which the upper part of the screen is dark and the lower part of the screen is bright in a TN mode liquid crystal panel of normally white display will be described.

In the pixel portion of the TFT substrate, a screen electrode 24, a gate signal line 21, a source signal line 22, and a drain electrode 23 are formed as in the first embodiment. And independent common electrode line 2
6 is formed below the pixel electrode 24. Pixel electrode 2
An insulating layer is formed between the pixel electrode 4 and the common electrode line 26 formed thereunder, and a region 25 where the pixel electrode 24 and the common electrode line 26 overlap serves as a storage capacitor.

The common electrode line 26 is formed such that the area of the region 25 overlapping the pixel electrode 24 gradually increases from the top of the screen to the bottom for each row. Thereby, the storage capacity of each pixel gradually increases from the top of the screen to the bottom for each row of pixels.

The liquid crystal panel according to the present embodiment is driven by capacitive coupling so that an offset voltage proportional to the storage capacitance is applied to each pixel electrode 24, and the common electrode line 26 has a positive bias potential _{Vge (+)} and Negative bias potential V
_It changes between the potentials of _{ge (-)} . Therefore, the offset voltage applied to the pixel electrodes 24 in each row increases sequentially from the top to the bottom of the screen, and the luminance difference between the top and bottom of the screen is corrected. Since the inclination of the amount of offset voltage in the vertical direction of the screen changes depending on the height of the bias potential of the common electrode line 26, the amount of gradation correction in the vertical direction of the screen is optimized by adjusting the bias potential of the common electrode line 26. Can be

Embodiment 3 FIG. 3 is a top view showing a pixel portion of a TFT substrate in a liquid crystal panel according to Embodiment 3 of the present invention. In the present embodiment, in an IPS mode liquid crystal panel in which a storage capacitor is formed on a gate signal line,
4 shows a configuration for correcting a gradation difference between pixels of different display colors caused by the wavelength dependence of the retardation of the liquid crystal layer. Here, an example in which the gray level becomes brighter in the order of red>green> blue in the normally black display IPS mode liquid crystal panel will be described.

In the pixel portion of the TFT substrate, screen electrodes 34 are formed in a matrix, and the gate signal lines 3 are provided for each row.
1 and the common electrode line 36 are connected to the source signal line 32 for each column.
Are formed. Gate signal line 11 and source signal line 1
The gate signal line 11 is connected to the gate electrode at the intersection of
A thin film transistor is formed using the source signal line 12 as a source electrode and a part of the pixel electrode 34 as a drain electrode. The pixel electrode 34 is formed so as to overlap the preceding gate signal line 31 via an insulating layer, and the regions 35A to 35C where the pixel electrode 34 and the gate signal line 31 overlap each other serve as storage capacitors. In the IPS mode panel, the pixel electrode 3
The liquid crystal is driven in the horizontal direction of the substrate by a voltage applied between the common electrode 4 and the common electrode 36.

In the TFT substrate shown in FIG. 3, each of the pixel electrodes 34A to 34C displays three colors of red, green, and blue in a set of three columns. For this purpose, a video signal corresponding to the display color is supplied from the source signal line 32 for each column,
As shown in FIG. 7, the color filter substrate bonded to the T substrate has three color layers, red 72A and green 72, respectively.
B and blue 72C are formed in a vertical stripe shape.

The pixel electrodes 34A to 34C and the gate signal line 3
The regions 35A to 35C overlapping 1 are formed so as to have different areas corresponding to the display colors. That is, for each source signal line corresponding to each of the three colors of red, green, and blue of the opposing substrates, the shape of the storage capacitor of the corresponding pixel is changed to 35A, 35B, 35
Change to C. For example, when the pixel electrodes 34A, 34B, and 34C display red, green, and blue, respectively,
The area of the overlapping region is in the order of 35C>35B> 35C.

The liquid crystal panel according to the present embodiment is
As with the TN mode liquid crystal panel of mode 1, each pixel electrode 3
4 so that an offset voltage proportional to the storage capacity is applied
Driven by capacitive coupling, the gate signal line 31
Potential, positive bias potential V _{ge (+)}And negative vias
Potential V_{ge (-)}Between the four potentials shown in FIG.
The waveform changes as shown in FIG. Therefore, the pixel electrode 3 of each column
4 is applied according to the display color.
Increases in the order of blue> green> red, and corrects the gradation difference between display colors
Is done. Incidentally, as can be seen from the equation (1), the voltage is applied to the pixel.
The ratio between the display colors of the applied voltage Vp is
Height V of ias potential_{ge (+)}And V_{g e (-)}By
Change. Therefore, the bias of the gate signal line 11
By adjusting the potential setting, the gradation between display colors can be compensated.
Positive quantities can be optimized.

According to the present embodiment, the offset application voltage amount can be optimized for each source signal line of each color of red, green, and blue, and the gradation of each color can be adjusted and optimized. As a result, the gradation characteristics of each color are improved, and one of the performance and quality issues in designing a large-sized TFT-LCD can be improved.

In the present embodiment, the correction by the storage capacity is performed for each of the three display colors, but the storage capacity may be made different only for one of the three colors having a large gradation shift. .

Embodiment 4 FIG. In this embodiment mode, the TFT
-LCD panel configuration is IPS (In Plane Switching)
An example in which the present invention is applied to a liquid crystal panel in which a storage capacitor is formed on a common (opposite) electrode line in a mode liquid crystal will be described.
FIG. 4 is a top view showing a pixel portion of a TFT substrate in a liquid crystal panel according to Embodiment 4 of the present invention. As in the third embodiment, a configuration for correcting a gradation difference between pixels having different display colors will be described. An example will be described in which the gray level becomes brighter in the order of red>green> blue in the normally black display IPS mode liquid crystal panel.

First, the operation of the IPS mode liquid crystal panel will be described. When forming a plurality of TFT pixels,
In the XY matrix, the same TFT portion and the same storage capacitor portion (additional capacitor portion) as the XY direction signal line and the X direction common (opposite) electrode line are all formed. A gate signal electrode line 41 is formed as an X direction signal line, a source signal electrode line 42 is formed as a Y direction signal line, and a common (opposite) electrode line 46 is formed in the X direction, and are electrically connected to these XY signal lines 41 and 42. The electrode is the TFT part. The TFT portion includes a part of both 41 and 42 and a drain electrode 44 connected to these parts via a capacitor. Storage capacity section 45A
45C are electrically connected to the common (opposite) electrode line 46 via a capacitor, and are electrically connected to the drain electrode 44 (or to a part of 44). In addition, IP
In the case of the S mode, the pixel electrode portion (black matrix opening) is common (opposed) to the drain electrode 44 and the electrode line 46.
It is one part of. A typical panel configuration in the case of the IPS mode is normally black (in which no voltage is applied to the liquid crystal and no light passes through the liquid crystal panel). In the case of the IPS mode, the counter electrode is formed on the array substrate side as described above (refers to a common (counter) electrode),
The voltage applied to the liquid crystal is applied horizontally (between the drain electrode and the common (opposed) electrode).

In summary, pixel electrodes 44 are formed in a matrix on the pixel portion of the TFT substrate as in the third embodiment, and a gate signal line 41 and a common electrode line 46 are provided for each row, and for each column. A source signal line 42 is formed. Part of the pixel electrode 44 is a drain electrode of the thin film transistor. In the present embodiment, the pixel electrode 4
Numeral 4 is formed so as to overlap with the common electrode line 46 via the insulating layer, and serves as an overlapping area 45A to 45C storage capacitance.

In the TFT shown in FIG.
4A to 44C have three rows as a set, and each row has three colors of red, green, and blue.
Show colors. For this purpose, a video signal corresponding to a display color is supplied from each source column from the source signal line 42 for each column, and a color filter substrate which is bonded to face the TFT substrate has three color layers as shown in FIG. Some 72A-72C are formed.

The areas 45A to 45C are formed to have different areas corresponding to the display colors. That is, for each source signal line corresponding to each of the three colors of red, green, and blue of the opposing substrates, the shape of the storage capacitor of the corresponding pixel is set to 45A, 45B, and 45.
Change to C. For example, the pixel electrodes 45A, 45B, 4
When 5C is displaying red, green, and blue, respectively, the area of the overlapping region is in the order of 45A>45B> 45C.

In the liquid crystal panel according to the present embodiment, although a constant voltage is applied to the common electrode line 46, each pixel electrode 44
Are driven so as to apply an offset voltage proportional to the storage capacity. Therefore, the offset voltage applied to the pixel electrodes 44 in each column increases in the order of blue>green> red according to the display color, and the gradation difference between the display colors is corrected.

That is, by optimally designing the areas of 45A, 45B, and 45C, the gradation of each color can be adjusted and optimized. As a result, the gradation characteristics of each color are improved, and a large T
One of the performance and quality issues in FT-LCD design can be improved.

In this embodiment, the correction is performed using the storage capacity for each of the three display colors. However, the storage capacity may be changed only for one of the three colors having a large gradation shift. .

Embodiment 5 FIG. Next, a fifth embodiment of the present invention will be described with reference to FIG. FIG. 5 is an enlarged plan view of an array substrate in which a plurality of TFT elements and pixels are formed in a matrix, and shows an example in which a TFT-LCD panel configuration is in a TN mode and a storage capacitor is formed on a gate signal line. ing. For each gate signal line 56 in the XY matrix, the shape and position of the storage capacitor portion
5A, 55B, and 55C, and at the same time, the position and shape of the drain electrode portion are also changed to 53A, 53B, and 53C. Thus, the amount of offset application voltage to the corresponding pixel can be changed for each gate signal line, and at the same time, the parasitic capacitance (Cg) generated between the drain electrode portion and the gate signal line.
d) can also be changed (conversely, the parasitic capacitance Cgd is changed by the change in the storage capacitance Cst). The offset application voltage allows the gradation characteristics to be changed and optimized based on the viewing angle dependency, while maintaining the uniformity of the pixel capacitance (the sum of the liquid crystal capacitance, the storage capacitance, and the parasitic capacitance). In addition, it is possible to reduce the distortion of the signal waveform for each gate signal line.

Therefore, according to the fifth embodiment,
By optimizing the amount of applied offset voltage for each gate signal line and reducing the distortion of the gate signal waveform as described above, the difference in the gradation characteristics (luminance difference) due to the expected angle between the top and bottom of the screen (for each gate signal line) is reduced. And flicker, crosstalk, and the like can be reduced. Therefore, it is possible to simultaneously improve the performance and quality issues of the large-sized TFT-LCD by the above two or more.

Embodiment 6 FIG. Next, a sixth embodiment of the present invention will be described with reference to FIG. That is,
FIG. 6 is an enlarged plan view of an array substrate on which a plurality of TFT elements and pixels are formed in a matrix. TFT-L
An example is shown in which a CD has a panel configuration in an IPS mode and storage capacitance is formed on a gate signal line. For each source signal line corresponding to each of the three colors of red, green, and blue of the opposing substrates, the shape and position of the storage capacitor portion of the corresponding pixel are set to 65A, 65A.
B and 65C, and at the same time, the position and shape of the drain electrode portion are also changed to 63A, 63B and 63C. Thus, for each source signal line corresponding to each of the three colors,
The amount of the offset voltage applied to the corresponding pixel can be changed, and at the same time, the parasitic capacitance generated between the drain electrode portion and the gate signal line can be changed (conversely, the amount of change in the storage capacitance changes the parasitic capacitance). The offset application voltage allows the change and optimization of the gradation characteristics of each of the red, green, and blue colors, while maintaining the uniformity of the pixel capacitance (similar to the fifth embodiment). This makes it possible to reduce the distortion of the signal waveform for each gate signal line.

Therefore, according to the sixth embodiment,
By optimizing the amount of offset voltage applied to each source signal line for each of the red, green, and blue colors and reducing the distortion of the gate signal waveform, the gradation characteristics of each color are improved, and flicker and crosstalk are reduced. it can. Therefore, large TFT
-Simultaneous improvement of the above two or more of performance / quality issues in LCD can be achieved.

In the first, second, and fifth embodiments, the TN mode is described as an example, but the same configuration can be applied to the IPS mode. In the third, fourth, and sixth embodiments, the IPS mode has been described as an example, but the present invention can also be applied to the TN mode. Although the storage capacitor is formed on the gate signal line in the example of the fifth embodiment, a common electrode line may be provided and the storage capacitor may be formed on this common electrode line. Although the storage capacitor is formed on the gate signal line in the example of the sixth embodiment, it may be formed on the common electrode line.

In the above embodiment, the size of the storage capacity is changed for each row or each column. However, the size of the storage capacity may be changed for every several rows or every several columns. .

[0050]

According to the present invention, capacitive coupling drive is performed,
It is possible to provide a TFT liquid crystal panel with excellent image uniformity by correcting the non-uniformity of gradation for each screen position and display color of the liquid crystal panel by making the storage capacitance different depending on the pixel screen position and display color. it can.

[Brief description of the drawings]

FIG. 1 is an enlarged plan view showing a TFT substrate of a liquid crystal panel according to Embodiment 1 of the present invention.

FIG. 2 is an enlarged plan view showing a TFT substrate of a liquid crystal panel according to Embodiment 2 of the present invention.

FIG. 3 is an enlarged plan view showing a TFT substrate of a liquid crystal panel according to Embodiment 3 of the present invention.

FIG. 4 is an enlarged plan view showing a TFT substrate of a liquid crystal panel according to Embodiment 4 of the present invention.

FIG. 5 is an enlarged plan view showing a TFT substrate of a liquid crystal panel according to Embodiment 5 of the present invention.

FIG. 6 is an enlarged plan view showing a TFT substrate of a liquid crystal panel according to Embodiment 6 of the present invention.

FIG. 7 is an enlarged plan view illustrating an example of a color filter.

FIG. 8 shows a TF of a conventional TN mode liquid crystal panel.
It is an enlarged plan view showing an example of a T substrate.

FIG. 9 shows a TF of a conventional TN mode liquid crystal panel.
It is an enlarged plan view which shows another example of a T substrate.

FIG. 10 is an enlarged plan view showing an example of a TFT substrate of a conventional IPS mode liquid crystal panel.

FIG. 11 is an enlarged plan view showing another example of a TFT substrate of a conventional IPS mode liquid crystal panel.

FIG. 12 is a circuit diagram showing an equivalent circuit of a TFT liquid crystal panel.

FIG. 13 is a timing chart illustrating an example of a drive waveform of the capacitive coupling drive.

[Explanation of symbols]

11, 21, 31, 41, 51, 61 gate signal line, 12, 22, 32, 42, 52, 62 source signal line, 13, 23, 33, 43, 53A-C, 63A-C drain electrode, 14, 24, 34, 44, 54, 64 pixel electrodes, 15, 25, 35A-C, 45A-C, 55A-C, 6
5A-C storage capacity

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 621 G09G 3/20 621M 622 622C 624 624B 624D 641 641P F-term (Reference) 2H092 GA14 JA24 JA29 JA37 JA37 JA41 JB67 NA01 QA07 2H093 NA16 NA31 NA51 NC34 ND06 ND10 ND15 NF05 5C006 AA16 AA22 AC11 AC22 AC25 AF42 AF46 BB16 BF37 BF43 FA18 FA22 FA23 FA37 FA55 FA56 5C080 AA10 BB05 CC03 DD04 DD06 DD28 EE29 EJ30 EJ30 JJ30 EJ30 EJ30

Claims (8)

[Claims] 1. A pixel electrode disposed in a matrix on one of a pair of substrates opposed to each other with a liquid crystal interposed therebetween, a gate signal line disposed for each row of the pixel electrode, and a column for each pixel electrode. A liquid crystal panel, comprising: a source signal line disposed at a cross section; a thin film transistor disposed at an intersection of the gate signal line and the source signal line; and a storage capacitor connected to the pixel electrode; and a storage capacitor connected to the pixel electrode. Is connected to the gate signal line, and by changing the gate signal line between at least four potentials including an ON potential and an OFF potential, an offset voltage due to capacitive coupling is applied to the pixel electrode via the storage capacitor. A liquid crystal panel, wherein the size of the storage capacitor is different for each of a predetermined number of rows or columns. 2. A pixel electrode disposed in a matrix on one of a pair of substrates opposed to each other with a liquid crystal interposed therebetween, a gate signal line and a common signal line disposed for each row of the pixel electrode, and the pixel electrode A liquid crystal panel having a source signal line arranged for each column, a thin film transistor arranged at an intersection of the gate signal line and the source signal line, connected to the pixel electrode, and a storage capacitor connected to the pixel electrode. Connecting the storage capacitor to the common signal line, changing the common signal line between at least two potentials, applying an offset voltage due to capacitive coupling to the pixel electrode via the storage capacitor, A liquid crystal panel wherein the size of the capacity is made different for each of a predetermined number of rows or columns. 3. The liquid crystal panel according to claim 1, wherein the size of the storage capacitor is gradually increased or decreased from the top to the bottom of the screen for every predetermined number of rows. 4. The liquid crystal panel according to claim 1, wherein the size of the storage capacitor is changed according to the display color of the pixel electrode. 5. The thin film transistor connected to a pixel disposed on the signal terminal side of the gate signal line.
3. The liquid crystal panel according to claim 1, wherein / L is increased as compared with other thin film transistors. 6. The size of a parasitic capacitance formed between a drain electrode of the thin film transistor and the gate wiring for supplying a gate signal to the thin film transistor,
3. The liquid crystal panel according to claim 1, wherein the liquid crystal panel is different in a screen. 7. The method according to claim 1, wherein the size of the storage capacitor is controlled by a shape of a photomask for forming the storage capacitor. 8. An image display device comprising the liquid crystal panel according to claim 1.