JP2002281571A - Remote control signal receiving circuit - Google Patents

Abstract

[PROBLEMS] To provide a remote control receiving circuit capable of performing a stable demodulation operation with respect to disturbance noise even at a low operation power supply voltage. In a remote control signal receiving circuit, an integration circuit provided between a detection circuit and a comparison circuit is made up of a first integration circuit and a second integration circuit connected to inputs of the comparison circuit. The first integrating circuit 11
Is set smaller than the integration time constant of the second integration circuit 12, and the two integration circuits are separated by the PN junction of the transistor Tr_B. This makes it possible to improve the noise removal capability of the demodulation circuit against disturbance noise such as an inverter fluorescent lamp and to stabilize demodulated pulses. As a result, when receiving a remote control signal in a noise environment, it is possible to realize an excellent remote control receiving device capable of preventing a malfunction and extending a maximum receiving distance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing for improving a decrease in reception quality due to the influence of disturbance noise in a general remote control device using infrared rays applied to home electric appliances and the like, that is, a remote control receiving device. Circuit.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a circuit configuration of a general infrared remote control receiver conventionally used. In the figure, 1 is a light receiving element such as a photodiode, 2
Is an IV amplifier for converting a current signal into a voltage signal, 3 and 4 are first and second amplifiers A and B, 5 is a BPF
(Band pass filter), 6 is a detection circuit, 7 is an integration circuit including an integration capacitor 8, 9 is a comparison circuit, and 10 is a Vo terminal (output terminal) inverted and output by an output transistor.

In this conventional circuit, a control signal light modulated by a carrier of a predetermined frequency (generally 30 kHz to 60 kHz) output from a remote control transmitter (not shown) is electrically converted by a light receiving element 1 of a remote control receiver. Converted to a signal. Since this electric signal is a current output,
The signal is converted into a voltage signal by the amplifier 2. The output signal of the IV amplifier 2 is sequentially amplified by the first amplifier A3 and the second amplifier B4, and is input to the BPF 5. The BPF 5 extracts and outputs a frequency component of a carrier wave from the electric signal.

The detection circuit 6, the integration circuit 7, and the comparison circuit 9
It constitutes a demodulation circuit. The output signal of the BPF 5 is input to the detection circuit 6, which is the first stage of the demodulation circuit. Detection circuit 6
Outputs a detection signal, which is a result of comparing the output signal of the BPF 5 with a predetermined reference voltage, to the integration circuit 7. The integration circuit 7 charges and discharges the integration capacitor 8 in response to the detection signal. The potential of the integration capacitor 8 is compared with a predetermined reference voltage by a comparison circuit 9, and a demodulated control signal pulse is output from a Vo terminal 10.

[0005] Such a demodulation operation will be described in more detail with reference to FIG.

The output signal of the BPF 5 oscillates at the frequency of the carrier wave, and has a large amplitude when there is a control signal and a small amplitude when there is no control signal (ideally, amplitude = 0).
Become. Comparing this with the reference voltage Vth, if the BPF output potential> Vth, the charging current i1 to the integrating circuit 7 is output. Conversely, when the BPF output potential <Vth, the charging current i1 to the integration circuit 7 is not output.

[0007] The potential of the integrating capacitor 8 in the integrating circuit 7 is represented by Vcint. In the example of FIG.
Has been reset to level.

When a signal is input, the BPF output potential> Vth
In this case, the integration capacitor 8 is charged with the current of i1-i2, and Vcint rises. On the other hand, when the BPF output potential <Vth, the current is discharged by the current i2 and Vcint falls.

If Vth, i1, i2 and the capacity of the integrating capacitor 8 are set to appropriate values, Vcint at the time of signal input can be obtained.
Are as shown in FIG. At the start of signal input, V
The cint rises as a whole while repeating rising and falling. This rise is limited at a predetermined potential by a limiter circuit (not shown). Even at the signal input tail, Vci
nt goes down as a whole while repeating rising and falling.

[0010] Vcint is input to the comparison circuit 9.
The comparison circuit 9 is a hysteresis comparator. When the output level of the Vo terminal 10 is "H", the threshold value is Vre.
f_H is set. Vcint at the start of signal input
Rises, and when Vcint> Vref_H, the output level of the Vo terminal 10 is switched to “L”, and at the same time, the threshold value is set to Vref_L.

Vcint falls at the signal input tail, and Vcint
When int <Vref_L, the output level of the Vo terminal 10 is switched to “H”, and at the same time, the threshold value becomes Vr.
ef_H is set.

As described above, the reference voltage Vth, the integration speed (time constant), and the hysteresis width (Vref
_H-Vref_L) can remove the frequency component of the carrier wave and extract the control signal pulse.

[0013]

In the infrared remote control receiver as described above, the integral waveform of the integrating capacitor 8 has a sawtooth shape oscillating at the frequency of the carrier wave as shown in FIG. By giving the comparison circuit 9 a sufficiently wide hysteresis width with respect to this waveform, the frequency component of the carrier can be reliably removed.

However, in recent years, the power supply design has been reduced in voltage due to the energy saving of home electric appliances, and the remote control receiving module which has conventionally been driven at 5V is also shifting to 3V driving.

As the operating voltage is lowered, the hysteresis width of the comparison circuit cannot be increased, and it becomes difficult to remove the frequency component of the carrier.

In such an operating environment, when disturbance noise is added, the integration waveform of the integration capacitor 8 easily exceeds the hysteresis width of the comparison circuit.

FIG. 9 shows an example in which the integrated waveform is distorted by disturbance noise.

If Vcint is distorted in the course of rising and instantaneously exceeds the hysteresis width, there is a problem that a whisker pulse is generated immediately before the Vo terminal outputs a normally demodulated control signal pulse. The same is true even when Vcint is falling.

A typical disturbance noise that poses a problem in an infrared remote control receiver is optical noise at the lighting frequency of an inverter fluorescent lamp. The frequency distortion of the difference between the lighting frequency of the inverter fluorescent lamp and the carrier frequency of the remote control signal is generated.

FIG. 10 shows an example in which a measure for preventing a mustache pulse in FIG. 9 is taken.

When the integral charging current is narrowed down and the sawtooth-shaped vibration amplitude is reduced to prevent the above-mentioned whisker pulse, the pulse width of the control signal pulse output from the Vo terminal becomes narrower, and the maximum receiving distance is reduced. There is a problem that the effect will appear.

An object of the present invention is to provide a remote control receiving circuit capable of performing a stable demodulation operation with respect to disturbance noise even at a low operation power supply voltage.

[0023]

In a remote control signal receiving circuit according to the present invention, an integrating circuit provided between a detecting circuit and a comparing circuit is connected to a first integrating circuit connected to an output of the detecting circuit. A second integration circuit connected to an input of a comparison circuit, wherein the integration time constant of the first integration circuit is set smaller than the integration time constant of the second integration circuit; Are separated by a PN junction of a transistor or a diode.

According to the present invention, it is possible to obtain a remote control receiving circuit capable of performing a stable demodulation operation with respect to disturbance noise even at a low operating power supply voltage.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a light receiving element for converting a control signal pulse into an electric signal in response to an optical remote control signal modulated with a predetermined frequency pulse as a carrier. An amplifier circuit for amplifying an electric signal converted by the light receiving element, a band-pass filter for extracting a frequency component of a carrier wave from the electric signal output from the amplifier circuit, an electric signal output from the band-pass filter and a reference voltage A detection circuit that controls the charge / discharge operation of the next-stage integration circuit; an integration circuit that performs a charge / discharge operation on an integration capacitor in accordance with an output signal of the detection circuit; and an output signal of the integration circuit. A comparison circuit for comparing the modulated control signal pulse with a predetermined reference voltage and outputting the modulated control signal pulse as a demodulated pulse train. In one embodiment, the integration circuit has a first integration circuit connected to the output of the detection circuit and a second integration circuit connected to the input of the comparison circuit. The constant is set smaller than the integration time constant of the second integration circuit, and the two integration circuits are separated by a PN junction of a transistor or a diode. Second
Can be set to different integration time constants (charging speeds) by the integration circuits described above. Here, since the charging speed of the first integration circuit is set so as to satisfy the charging speed of the second integration circuit, the sawtooth integration waveform of the integration capacitor entering the comparison circuit is converted into a linear integration waveform. Can be converted.

Therefore, a stable demodulated pulse without noise can be output even in a circuit in which the hysteresis width of the threshold value of the comparison circuit is limited.

According to a second aspect of the present invention, a parasitic capacitance formed on a circuit is used as an integrating capacitor of a first integrating circuit in the integrating circuit. In order to make the charging speed of the first integrating circuit higher than the charging speed of the second integrating circuit, it is necessary to make the integrating capacitor of the first integrating circuit smaller than the integrating capacitor of the second integrating circuit. In reality, the parasitic capacitance between the wiring patterns or in the transistor acts as a minute capacitor, so that the parasitic capacitance can be used.

According to a third aspect of the present invention, the time constant of the first integration circuit in the integration circuit is 0, that is, the first integration circuit has no integration capacitor element. If the charging speed of the first integrating circuit is simply set to be faster than the charging speed of the second integrating circuit, the response speed of the circuit obtained by removing the integrating capacitor of the first integrating circuit will be equal to that of the second integrating circuit. Since the charging speed is sufficiently higher than the charging speed, the same effect as that of the first aspect can be obtained. Furthermore, the chip size can be reduced by removing one integration capacitor.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of a demodulation circuit according to Embodiment 1 of the present invention.

The demodulation circuit roughly includes a detection circuit 6
, A first integrating circuit A11, and a second integrating circuit B12
And a comparison circuit 9, and the demodulated control signal pulse is output from a Vo terminal 10.

The detection circuit 6 compares a BPF output (not shown) with a predetermined threshold value Vt, and outputs the detection result to a first integration circuit A11 via a transistor Tr_A connected as an output circuit of the detection circuit 6. Output.

A second integrating circuit B12 is connected to the next stage of the first integrating circuit A11.

The first integration circuit A11 comprises a first integration capacitor A13 and a constant current source i2.
Is always connected in the direction of discharging the first integration capacitor A13. The potential of the first integration capacitor A13 is indicated by VcintA.

The second integrating circuit B12 comprises a second integrating capacitor B14 and a constant current source i1.
Is always connected in a direction to charge the second integration capacitor B14. The potential of the second integration capacitor B14 is indicated by VcintB.

The transistor Tr_B connects the first integration capacitor A13 and the second integration capacitor B14 with an emitter follower. The first integration capacitor A13 is connected to the base of the transistor Tr_B, and the second integration capacitor A13 is connected to the emitter. Is connected, and the collector is grounded to GND.

Therefore, when the first integration capacitor A13 is completely discharged, VcintB = Vcint
A + (Vbe of Tr_B). At this time, the charging current of the second integration capacitor B14 (the constant current source i
1) is mostly extracted as the collector current of the transistor Tr_B.

FIG. 2 shows the case where the control signal is input.
3 shows the waveforms of cintA and VcintB.

The initial state is the first integration capacitor A13
Have completely discharged, and VcintA = 0.1 V (corresponding to the saturation voltage of the constant current source i2). Also Vcin
tB ≒ 0.8 V (VcintA + Vbe of Tr_B). The comparison circuit 9 outputs an “H” level signal from the Vo terminal 10.

When a control signal is input here, the first integration circuit A11 charges the first integration capacitor A13 with a current equal to the difference between the output current of the detection circuit 6 and the constant current source i1. Since the output current of the detection circuit 6 is set to be larger than that of the constant current source i1, the charging speed (time constant) of the first integration capacitor A13 is fast, and sharply as shown in the rising waveform of VcintA in FIG. stand up.

When the waveform of VcintA sharply rises, the transistor Tr_B becomes a reverse bias between BE and becomes in a cut-off state. From here the charging current (constant current source i1)
Starts to be supplied to the second integrating capacitor B14, and the integrating operation of the second integrating circuit B12 is started. The constant current source i1 is set to a sufficiently small current value and Vcint
B rises slowly. The integration speed is 3
The threshold value (V
ref_H).

When VcintB> Vref_H, the output of the comparison circuit 9 is inverted, and a low level signal is output from the Vo terminal 10.

VcintB> VcintA + (Tr_B
Since VbetB linearly increases up to Vbe), no erroneous pulse is generated in the comparison circuit 9 and Vo
The terminal 10 can output a stable falling pulse.

Thereafter, when the input of the control signal stops, the output current of the detection circuit 6 stops, and the first integration capacitor A13 is discharged by the current of the constant current source i1. A constant current discharge occurs and the waveform of VcintA slowly drops at a speed of about 10 mV / μs. Synchronously with this, VcintB
Also falls, and when VcintB <Vref_L, the output of the comparison circuit 9 is inverted and “H” is output from the Vo terminal 10.
Output level signal. Since the discharge also decreases linearly, the Vo terminal 10 can output a stable rising pulse.

As described above, the rising and falling edges of the integrated waveform are sufficiently slow and linear when viewed from the comparison circuit 9. Therefore, the possibility of occurrence of an erroneous pulse is low, and a stable demodulation operation is performed.

FIG. 3 shows the waveforms of VcintA and VcintB when a control signal enters under a noise environment.

Assuming that the noise is an inverter fluorescent lamp, the amplitude of the BPF output fluctuates at a frequency equal to the difference between the carrier of the control signal and the lighting frequency of the inverter fluorescent lamp. For example, carrier frequency = 40 kHz, inverter fluorescent lamp lighting frequency = 4
In the case of 7 kHz, the BPF output amplitude fluctuates at a period of 7 kHz.

Under such an environment, the waveform of VcintA becomes unstable in synchronization with the frequency of the difference as shown in FIG. In VcintB, the charging operation is stopped in synchronization with the frequency of the difference, and the discharging operation is started. However, Vcint
The variation width of B is determined by the hysteresis width (Vref
−H−Vref_L), so that a stable demodulation operation is performed without erroneous determination.

(Embodiment 2) FIG. 4 is a block diagram showing an electrical configuration according to the second aspect of the present invention.

In FIG. 1, a transistor Tr is removed from the first integrating circuit A11 except for the first integrating capacitor A13.
_B is also changed to the diode Di. Diode Di
Has an anode connected to the integration capacitor 8 and a cathode connected to the constant current source i2.

The potential on the cathode side of the diode Di is Vk
Then, the initial state is Vk ≒ 0.1 V (constant current source i2
Corresponding to the saturation voltage). Also Vcint ≒
0.8 V (Vk + Vf of Di). The comparison circuit 9 outputs an “H” level signal from the Vo terminal 10.

When a control signal is input here, the detection circuit 6
Since the output current is set to be larger than that of the constant current source i2, Vk rises sharply like the rising waveform of VcintA in FIG.

When Vk rises rapidly, the diode D
i is a cutoff state becomes reverse biased. From here, the charging current (constant current source i1) starts to be supplied to the integration capacitor 8, and the integration operation of the integration circuit 7 is started. Constant current source i
1 is set to a sufficiently small current value and Vcint
Rises slowly. The integration speed is between 3 and
The threshold value (Vr
ef_H).

When Vcint> Vref_H, the output of the comparison circuit 9 is inverted, and a signal of “L” level is output from the Vo terminal 10.

Since Vcint rises linearly until Vcint> Vk + (Vf of Di), no erroneous pulse is generated in the comparison circuit 9 and the Vo terminal 10 can output a stable falling pulse.

The operation after the control signal is no longer input is the same as that described with reference to FIG.

In such a configuration, since the first integration capacitor A13 of the first integration circuit A11 is removed, the original integration operation cannot be performed, and the output of the detection circuit 6 appears as it is on Vk. The amplitude will increase. Therefore, there is a possibility that a stable charging operation may not be performed due to a discharging operation during the charging operation of the integrating capacitor 8, but the diode Di is always maintained during the charging operation by optimizing the threshold value Vt of the detection circuit 6. Control can be performed so that reverse bias occurs.

(Embodiment 3) FIG. 5 is an inverted version of the polarity relating to the integration of FIG. 1 and 4 are based on the ground point, but FIG. 5 is based on the power supply potential. Also in this case, the operation is the same as that described with reference to FIG.

[0059]

As described above, according to the first aspect of the present invention, the integration circuit includes the first integration circuit connected to the output of the detection circuit and the second integration circuit connected to the input of the comparison circuit. Wherein the integration time constant of the first integration circuit is set smaller than the integration time constant of the second integration circuit, and the two integration circuits are separated by a PN junction of a transistor or a diode. As a result, it is possible to improve the noise removal capability of the demodulation circuit against disturbance noise such as an inverter fluorescent lamp and to stabilize demodulated pulses. As a result, when receiving a remote control signal in a noise environment, it is possible to realize an excellent remote control receiving device capable of preventing a malfunction and extending a maximum receiving distance.

According to the second and third aspects of the present invention, it is preferable to use a parasitic capacitance formed on a circuit as an integrating capacitor of the first integrating circuit in the integrating circuit.
By constructing the first integrating circuit so as not to have the integrating capacitor element, the time constant of the first integrating circuit becomes minute or zero, and the effect on the characteristic can be obtained as in the first aspect of the invention. An object of the present invention is to realize an excellent remote control receiving device which can reduce the number of components and prevent an increase in chip size.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an electrical configuration of a demodulation circuit of an infrared remote control receiver according to an embodiment of the present invention.

FIG. 2 is a waveform chart illustrating the operation of the integration circuit of the infrared remote control receiver according to one embodiment of the present invention.

FIG. 3 is a waveform chart for explaining the operation of the integration circuit when there is disturbance noise in the infrared remote control receiver according to one embodiment of the present invention;

FIG. 4 is a block diagram showing an electrical configuration of the demodulation circuit of the infrared remote control receiver according to the embodiment of the present invention, in which an integration capacitor is omitted.

FIG. 5 is a block diagram showing an electrical configuration of the demodulation circuit of the infrared remote control receiver according to the embodiment of the present invention, in which an integration capacitor is deleted and the polarity of integration is inverted.

FIG. 6 is a block diagram showing an electrical configuration of a conventional infrared remote control receiver.

FIG. 7 is a block diagram showing an electrical configuration of a demodulation circuit of a conventional infrared remote control receiver.

FIG. 8 is a waveform chart for explaining the operation of the integration circuit of the conventional infrared remote control receiver.

FIG. 9 is a waveform diagram illustrating the operation of the integration circuit when there is disturbance noise in the conventional infrared remote control receiver.

FIG. 10 is a waveform chart for explaining the operation of the integration circuit when the integration speed is reduced in order to reduce disturbance noise of the conventional infrared remote control receiver.

[Explanation of symbols]

 Reference Signs List 1 light receiving element 2 IV amplifier 3 amplifier A 4 amplifier B 5 BPF 6 detection circuit 7 integration circuit 8 integration capacitor 9 comparison circuit 10 Vo terminal 11 first integration circuit A 12 second integration circuit B 13 first integration capacitor A 14 Second integrating capacitor B i1 Integrating circuit charging constant current source i2 Integrating circuit discharging constant current source

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04B 10/04 10/06

Claims (3)

[Claims] 1. A light receiving element for converting a control signal pulse into an electric signal in response to an optical remote control signal modulated using a predetermined frequency pulse as a carrier, and an amplifier for amplifying the electric signal converted by the light receiving element. Circuit, a band-pass filter for extracting a frequency component of a carrier wave from the electric signal output from the amplifier circuit, and a comparison between the electric signal output from the band-pass filter and a reference voltage, and a charging / discharging operation of a next-stage integration circuit And an integration circuit that performs a charging / discharging operation on an integration capacitor in accordance with an output signal of the detection circuit, and comparing the output signal of the integration circuit with a predetermined reference voltage,
A comparison circuit that outputs the modulated control signal pulse as a demodulated pulse train, wherein the integration circuit is connected to an output of the detection circuit.
And a second integration circuit connected to the input of the comparison circuit, wherein the time constant of the first integration circuit is set to the second integration circuit.
Is set to be smaller than the time constant of the integrating circuit, and a PN of a transistor or a diode is provided between the two integrating circuits.
A remote control signal receiving circuit, which is configured to be separated by joining. 2. The remote control signal receiving circuit according to claim 1, wherein the first integrating circuit in the integrating circuit utilizes a parasitic capacitance formed on the circuit. 3. The remote control signal receiving circuit according to claim 1, wherein a time constant of a first integrating circuit in said integrating circuit is set to 0.