JP2002280895A - Level shifter circuit and image display application equipment - Google Patents

Abstract

(57) [Summary] [PROBLEMS] A conventional level shifter circuit has an input signal voltage,
Small margin for fluctuations in frequency and power supply voltage,
Stable driving could not be performed. A current mirror circuit for converting a low-amplitude input signal having a transistor having a predetermined threshold value to a high-amplitude output signal, and an offset added to the input signal to provide a current mirror circuit A circuit comprising source follower circuits 12a and 12b to be supplied and current source transistor circuits 13a and 13b, and a bias supplied to current source transistor circuits 13a and 13b by changing a bias for determining an offset to be added based on an input signal A level shifter circuit including variable circuits 14a and 14b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shifter circuit for converting a low-amplitude input signal into a high-amplitude output signal, for example, incorporated in a low-temperature polysilicon TFT display device or the like.
And image display application equipment.

[0002]

2. Description of the Related Art First, a low-temperature polysilicon TF will be described with reference to FIG.
A configuration of a conventional level shifter circuit which is built in a horizontal scanning circuit of T and used as a level shifter circuit with a clock input stop function will be described.

A level shifter circuit includes a pair of input transistors MN1, MN4 and a pair of load transistors MP.
4, a source follower circuit 42a and 42b including a pair of transistors MP2 and MP8 each having an input terminal IN and an input inversion terminal INB as gate inputs, and a source follower circuit 42.
current source circuits 43a and 43b each including a pair of transistors MP1 and MP7 serving as current sources for driving a and 42b.
It is composed of Further, in the current mirror circuit 41, operation stopping transistors MP3, MP5, MN2 and MN3 are connected to the drains of the load transistors MP4 and MP6 and the gates of the input transistors MN1 and MN4.

Next, the operation of the conventional level shifter circuit will be described with reference to FIGS.
5A is an explanatory diagram of the input signal VIN input to the input terminal IN, FIG. 5B is an explanatory diagram of the input inverted signal VINB input to the input inverting terminal INB, and FIG. FIG. 5D is an explanatory diagram of a control signal (control signal) VCTL input to the control terminal CTL, and FIG. 5D is an explanatory diagram of a waveform VLS of each node (nodes a to c) in the level shifter circuit.

As the input signal VIN and the input inversion signal VINB, two-phase low-voltage signals whose phases are inverted by 180 ° are input.

Further, the operation stopping transistors MP3, M
P5, MN2, and MN3 (see FIG. 4) are controlled by the control signal VCT.
When the state of L is H, all the states are turned on, and the state of the level shifter output signal VOUT is fixed to H. Conversely, when the control signal VCTL is L, the operation stopping transistor MP
3, MP5, MN2, and MN3 are all turned off. In this case, the input signal VIN and the input inverted signal VINB input from the input terminal IN and the input inverted terminal INB are:
A high voltage output signal VOUT is output from the output terminal OUT.

[0007] The input inverted signal VINB is connected to the gate of the source follower transistor MP2. Also,
The drain of the source follower transistor MP2 is connected in series with the drain of the current source transistor MP1.

For this reason, at a point a in FIG. 4, as shown in FIG. 5, the threshold of the source follower transistor MP2 according to the voltage of the input inversion signal VINB and the driving capability of the current source transistor MP1. A value voltage (an offset voltage generated between the gate and the source of the source follower transistor MP2) is added as a DC offset.

Next, since the source of the input transistor MN1 of the current mirror circuit 41 is connected to the input terminal IN, an input signal V is applied between the gate and the source of MN1.
The potential difference between the potential of IN and the potential at point a is given.

In this level shifter circuit, since each transistor has a pair configuration, the potential at point b in FIG. 4 can be considered in the same manner as at point a. That is, a DC offset is added to the input signal VIN by the source follower transistor MP8 and the current source transistor MP7. Further, since the source of the input transistor MN4 is connected to the input inversion terminal INB, M
A potential difference between the potential of the input inversion signal VINB and the potential at the point b is applied between the gate and the source of N4.

Since the input signal VIN and the inverted input signal VINB are two-phase signals as described above, the gate-source voltages of the input transistors MN1 and MN4 are changed according to the input signal as described above. Change each other.

For example, during a period in which the potential at point a is higher than point b, the relationship between the gate bias voltages of the input transistors is MN1> MN4, and the potential at point c decreases in the direction of zero. Then load transistors MP4, MP6
Is applied with a larger gate bias voltage, and as a result, the output signal VOUT becomes H level. Conversely, M
When N1 <MN4, the output signal VOUT becomes L level.

As described above, by inputting a low voltage signal from each of the input terminal IN and the input inversion terminal INB, the signal level is converted, and the high voltage output signal VOUT is output.
Can be obtained.

[0014]

However, in such a conventional level shifter circuit, there is a problem that a margin for fluctuations of an input signal voltage, a frequency, and a power supply voltage is small, and a sufficiently stable drive cannot be performed.

In view of the above-mentioned conventional problems, the present invention provides a level shifter circuit which has a larger margin for fluctuations in input signal voltage, frequency and power supply voltage and can perform sufficiently stable driving, and an image. It is intended to provide a display application device.

[0016]

Means for Solving the Problems The first invention (claim 1)
A) a level conversion unit having a current mirror circuit for converting a low-amplitude input signal into a high-amplitude output signal having a transistor having a predetermined threshold value, and an offset for the input signal. An offset adding unit that adds and supplies the offset to the level converting unit; and a bias variable unit that changes a bias for determining the offset to be added based on the input signal and supplies the bias to the offset adding unit. Level shifter circuit.

According to a second aspect of the present invention (corresponding to claim 2), the offset adding section includes a source follower transistor which is a Pch transistor having the input signal as a gate input, and a Pch transistor for driving the source follower transistor. A current source transistor which is a transistor, wherein the offset is an offset voltage generated between a gate and a source of the source follower transistor in accordance with a state of the current source transistor. is there.

According to a third aspect of the present invention (corresponding to claim 3), the bias variable section has a Pch transistor and an Nch transistor connected in series for forming an inverter configuration, and forms the inverter configuration. Nc to do
The source of the h transistor is connected to the input terminal to which the input signal is input, and the drain of the Nch transistor for forming the inverter configuration and the drain of the Pch transistor for forming the inverter configuration are connected to the current 10 is a second level shifter circuit of the present invention connected to the gate of the source transistor.

A fourth aspect of the present invention (corresponding to claim 4) comprises a control unit for outputting a control signal for controlling at least an on / off state of an Nch transistor for forming the inverter configuration, Is a bias voltage applied from the drain of the Nch transistor to form the inverter configuration to the gate of the current source transistor, and the bias variable section includes:
(A) during a period in which an Nch transistor for forming the inverter configuration is in an on state, the bias voltage is changed based on a state of an input signal to bring the current source transistor into an operating state; In a third period of the present invention, the current source transistor is turned off during periods other than the above.

According to a fifth aspect of the present invention (corresponding to claim 5), there is provided a fourth circuit connected to the current mirror circuit for controlling the output signal regardless of the state of the input signal based on the control signal. 14 is a fourth level shifter circuit of the present invention having four transistors.

A sixth invention (corresponding to claim 6) is an image display application device using the level shifter circuit according to any one of the first to fifth inventions.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

First, the configuration of the level shifter circuit according to the present embodiment will be described with reference to FIG. 1, which is a configuration diagram of the level shifter circuit according to the present embodiment.

The level shifter circuit of this embodiment has a configuration similar to that of the above-described conventional level shifter circuit, and is built in, for example, a horizontal scanning circuit of a low-temperature polysilicon TFT and serves as a level shifter circuit with a clock stop function. Function.

More specifically, the level shifter circuit according to the present embodiment includes (1) a pair of input transistors M
N1, MN4 and a pair of load transistors MP4, MP
6, a current mirror circuit 11 (level conversion unit) including
(2) Source follower circuits 12a and 12b each including a pair of transistors MP2 and MP8 each having an input terminal IN and an input inversion terminal INB as gate inputs, and a pair of current sources for driving the source follower circuits 12a and 12b. (Offset adding section) including current source transistor circuits 13a and 13b including the transistors MP1 and MP7, and (3) an inverted signal of the control terminal CTL as a gate input, and the Pch transistors MP13 and N
ch transistor MN8, Pch transistor MP14
And Nch transistor MN9 are connected in series, respectively (Pch transistors MP13 and MP14 form a pair,
The channel transistors MN8 and 9 form a pair), a bias variable circuit 14a forming a part of the inverter INV1,
14b (bias variable section), the operation stopping transistors MP3, MP5, MN2, and the gates of the input transistors MN1 and MN4 are connected to the drains of the load transistors MP4 and MP6 of the current mirror circuit 11, respectively.
MN3 (transistor for controlling the output signal based on the control signal regardless of the state of the input signal) is connected.

The input terminal IN (input inverting terminal IN)
B) directly from the transistors MP1 and MP8 (MP2 and M
P7) may be used as a gate input, but the bias variable circuits 14a and 14b are provided as described above, and a control signal (control signal) VCTL input from a control unit (not shown) to the control terminal CTL is used. By controlling the state of the output signal irrespective of the state of the input signal, low power consumption can be promoted.

Next, the operation of the level shifter circuit according to the present embodiment will be described with reference to FIGS. FIG. 2A is an explanatory diagram of an input signal VIN input to the input terminal IN, and FIG.
FIG. 2 is an explanatory diagram of an input inverted signal VINB input to the NB, FIG.
(C) is a control signal VCTL input to the control terminal CTL.
FIG. 2D is an explanatory diagram of a waveform VLS at each node (nodes a to c) in the level shifter circuit.

As in the case of the above-described conventional level shifter circuit, two-phase low-voltage signals whose phases are inverted are input as the input signal VIN and the input inverted signal VINB. The operation stopping transistors MP3 and MP
5, MN2 and MN3 are all turned on when the state of the control signal VCTL is H, and the level shifter output signal VOUT
Is fixed at H. Conversely, when the control signal VCTL is L
, The operation stopping transistors MP3, MP5, MN
2 and MN3 are all turned off. In this case, the input signal V input from the input terminal IN and the input inversion terminal INB is input.
IN, the input inverted signal VINB is a high voltage output signal VO
It becomes a UT and is output from the output terminal OUT (note that the case where the control signal VCTL is L is mainly described below).

The input inversion signal VINB is a gate input of the source follower transistor MP2. Also,
The drain of the source follower transistor MP2 is connected in series with the drain of the current source transistor MP1. Therefore, at the point a in FIG. 1, as shown in FIG. 2, the input inversion signal VINB and the current source transistor M
The threshold voltage of the source follower transistor MP2 corresponding to the driving capability of P1 is added as a DC offset.

Up to this point, it is the same as the conventional case described above. However, in the present embodiment, (1) the gate of the current source transistor MP1 is connected to the bias variable transistor MP
13 is connected to the drain of MN8. (2) The gate of the current source transistor MP7 is connected to the drains of the bias variable transistors MP14 and MN9. Further, the bias variable transistors MN8, MN9
Are the input terminal IN and the input inversion terminal IN, respectively.
B.

By using such a circuit configuration,
It is possible to vary the gate bias voltages of the current source transistors MP1 and MP7.

More specifically, when the control signal VCTL is L, the gates of the bias variable transistors MP13 and MN8 become H, and MN8 is turned on (conducting). At this time, the power supply voltage VDD is applied to the current source transistor MP1.
And the input signal VIN is supplied as a gate bias.

Therefore, for example, when the power supply voltage VDD is set to 1
When the input signal INB is 2 V, (A) when the input inversion signal INB is 3 V (this is H), and when the input signal IN is 0 V (this is L), the gate bias voltage of the current source transistor MP1 becomes 12 V, which is opposite. And (B) the input inverted signal I
When NB is L and the input signal IN is H, the gate bias voltage is 9V. As described above, it is possible to vary the gate bias voltage of the current source transistor MP1 by 3V according to the state of the input signal.

Therefore, if the input inversion signal is H (or L)
In the case of (1), the voltage of the point a can be set higher (or lower) by increasing (or decreasing) the current of the current source transistor MP1.

On the other hand, since the voltage between the power supply voltage VDD and the input inversion signal INB is supplied as a gate bias to the gate of the current source transistor MP7, during the period when the voltage at the point a is set high (or low). , B are set low (or high) on the contrary.

Therefore, by using the circuit configuration of the present embodiment, when the control signal VCTL becomes L,
The voltage difference ΔV2 between the point a and the point b is reduced by the conventional voltage difference ΔV1.
(See FIG. 5). When the control signal VCTL becomes H, the bias variable transistors MP13 and MP14 are turned on (conduction state), so that the current source transistors MP1 and MP7 are turned on. Turns off and no current flows).

Since the source of the input transistor MN1 of the current mirror circuit is connected to the input terminal IN, a potential difference between the potential of the input signal VIN and the potential at point a is applied between the gate and the source of MN1. become.

Of course, since the level shifter circuit of the present embodiment has a configuration in which the input transistors MN1 and MN4 form a pair, the potential at point b in FIG. 1 can be considered in the same manner as point a. That is, the input signal VIN
Is given a DC offset by the source follower transistor MP8 and the current source transistor MP7.
Further, since the source of the input transistor MN4 is connected to the input inversion terminal INB, a potential difference between the potential of the input inversion signal VINB and the potential at the point b is applied between the gate and the source of MN4.

Since the input signal VIN and the inverted input signal VINB are two-phase signals as described above, as described above, the gate-source voltage applied to the input transistors MN1 and MN4 is equal to the input signal. Change with each other.

For example, during a period in which the potential at point a is higher than point b, the relationship of the gate bias voltage of the input transistor is MN1> MN4, and the potential at point c decreases in the direction of zero. Then load transistors MP4, MP6
Is applied with a larger gate bias voltage, and as a result, the output signal VOUT becomes H level (conversely, M
When N1 <MN4, the output signal VOUT becomes L level).

Thus, the input terminal IN and the input inversion terminal I
The low voltage signal input from the NB is a high voltage output signal V
The level is converted to OUT.

In the level shifter circuit according to the present embodiment, as shown in FIG.
It can be seen that the amplitude at points a and b is larger than the amplitude of B compared to the conventional case. And point a and b
By increasing the amplitude of the point, the input transistor M
The difference between the gate bias voltages of N1 and MN4 also increases,
The dynamic range of the output signal VOUT can be increased.

As a result, FIG. 3 shows a comparison of the maximum operating frequency characteristics of a horizontal scanning circuit in a TFT active matrix type liquid crystal display device manufactured using the conventional level shifter circuit and the level shifter circuit of the present embodiment. As described above, it can be understood that the horizontal scanning circuit using the level shifter circuit of the present embodiment (the present invention) can operate at higher speed than the horizontal scanning circuit using the conventional level shifter circuit (the conventional configuration). FIG. 3 is a characteristic comparison diagram between a horizontal scanning circuit using a level shifter circuit according to the present embodiment and a horizontal scanning circuit using a conventional level shifter circuit.

As described above, by using the level shifter circuit of the present invention, it is possible to secure a stable driving margin with respect to fluctuations of the input signal, the frequency and the power supply voltage.

In the conventional level shifter circuit, as shown in FIG. 5, the amplitude .DELTA.V1 at the points a and b with respect to the amplitudes of the input signal VIN and the input inverted signal VINB.
Becomes extremely small. When the amplitude at the points a and b decreases, the difference between the gate bias voltages applied to the input transistors MN1 and MN4 also decreases.

As described above, since the output level of the output signal VOUT is determined by the difference between the ON currents of the input transistors MN1 and MN4, a decrease in the difference means that the dynamic range of the output signal VOUT is reduced. Is shown. The potentials at points a and b are determined by the balance between the source follower transistors MP2 and MP8 and the current source transistors MP1 and MP7.

Therefore, in the conventional circuit configuration, since the bias voltages of the current source transistors MP1 and MP7 are fixed, even if the voltage amplitude of the input signal VIN and the input inversion signal VINB changes, a constant current is always used. Only driving can be performed, and for the input transistors MN1 and MN4,
A phenomenon occurs that the amplitude of the input signal cannot be transmitted reliably.

The inventor of the present invention has focused on such a phenomenon and its mechanism, and has carried out the present invention as described above. The present invention provides a level shifter circuit which can operate stably even when the driving conditions fluctuate. It was intended to do so.

Accordingly, the present invention provides, for example, a level conversion unit including a current mirror circuit including a transistor element having a predetermined threshold value and converting a low-amplitude input signal into a high-amplitude output signal; An offset adding section that applies an offset voltage according to a signal level and supplies the offset converting section with a bias voltage that determines the level of the offset voltage in conjunction with an input signal level to supply the offset voltage to the offset adding section. A variable section, and a control section for controlling the state of the output signal irrespective of the state of the input signal, wherein the offset adding section has a Pch transistor comprising a source follower circuit using the input signal as a gate input; Pch which is connected to a follower transistor and includes a current source for driving the transistor Consists transistors, the bias changing unit includes an inverter configured whereby a Pch transistor and an Nch transistor in series, Nch
The source of the transistor is connected to the input terminal and Nch,
The drain of the Pch transistor is connected to the gate of the Pch transistor constituting the current source, the bias variable section is also controlled by a control signal from the control section, and the Nch transistor of the bias variable section is turned on. The bias voltage of the current source transistor is changed in conjunction with the state of the input signal only during the period during which the current source transistor is turned off, and the current source transistor is stopped during other periods. Further, the control unit includes four transistors connected to the level conversion unit, and has a function of stopping an output signal regardless of a state of an input signal by a control signal.

The present invention also provides, for example, a level conversion section including a current mirror circuit including a transistor element having a predetermined threshold value and converting a low-amplitude input signal into a high-amplitude output signal; Adding an offset voltage according to the signal level, and changing an offset adding unit to be supplied to the level conversion unit and a bias voltage for determining the level of the offset voltage in conjunction with the input signal level;
The level shifter circuit includes a bias variable unit that supplies the offset adding unit and a control unit that controls the state of the output signal regardless of the state of the input signal.

Further, according to the present invention, for example, the offset adding section includes a Pch transistor comprising a source follower circuit using an input signal as a gate input, and a current source connected to the source follower transistor for driving the transistor. The above-described level shifter circuit is characterized by being constituted by Pch transistors.

Further, according to the present invention, for example, the bias variable section has an inverter configuration in which a Pch transistor and an Nch transistor are connected in series, a source of the Nch transistor is connected to an input terminal, and Nch, P
The above-described level shifter circuit is characterized in that the drain of the channel transistor is connected to the gate of the Pch transistor constituting the current source.

Further, according to the present invention, for example, the bias variable section is controlled by a control signal from the control section, and the bias variable section interlocks with the state of the input signal only while the Nch transistor of the bias variable section is turned on. The above level shifter circuit is characterized in that the bias voltage of the current source transistor is changed and the current source transistor is stopped in other periods.

Further, according to the present invention, for example, the control unit includes four transistors connected to the level conversion unit, and has a function of stopping an output signal by a control signal regardless of the state of an input signal. The above-described level shifter circuit is provided.

Note that an image display application device using the level shifter circuit of the present invention is included in the present invention.

As described above, according to the present invention, the bias voltage of the current source transistor is varied according to the input signal VIN and the input inversion signal VINB.
The signal amplitude for input to the input transistor of the current mirror circuit can be made larger than that of the conventional circuit, and as a result, the dynamic range of the output signal VOUT can be increased. Therefore, by using the level shifter circuit of the present invention, there is an effect that a sufficient margin for driving the circuit can be obtained. As a result, it becomes possible to realize a level shifter circuit that operates more stably with respect to fluctuations of the input signal, the frequency, and the power supply voltage as compared with the related art.

[0057]

As is apparent from the above description,
The present invention has an advantage that a margin for fluctuations of an input signal voltage, a frequency, and a power supply voltage is increased, and a level shifter circuit can be driven sufficiently stably.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a level shifter circuit according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of an input signal VIN input to an input terminal IN of the level shifter circuit according to the embodiment of the present invention (FIG. 2A), and an explanation of an input inverted signal VINB input to an input inverted terminal INB; Figure (FIG. 2 (b)), control terminal C
FIG. 2 is an explanatory diagram of a control signal VCTL input to the TL (FIG. 2)
(C)) and an explanatory diagram of the waveform VLS of each node (nodes a to c) inside the level shifter circuit (FIG. 2 (d))

FIG. 3 is a characteristic comparison diagram between a horizontal scanning circuit using a level shifter circuit according to the embodiment of the present invention and a horizontal scanning circuit using a conventional level shifter circuit;

FIG. 4 is a configuration diagram of a conventional level shifter circuit.

FIG. 5 is an explanatory diagram of an input signal VIN input to an input terminal IN of the conventional level shifter circuit (FIG. 5A), and an explanatory diagram of an input inverted signal VINB input to an input inverting terminal INB (FIG. 5 ( b)), an explanatory diagram of the control signal VCTL input to the control terminal CTL (FIG. 5C), and the waveform VLS of each node (nodes a to c) inside the level shifter circuit
Illustration (Fig. 5 (d))

[Explanation of symbols]

11, 41 Current mirror circuit 12a, 12b, 42a, 42b Source follower circuit 13a, 13b, 43a, 43b Current source transistor 14a, 14b Bias variable circuit MP3, MP5, MN2, MN3 Operation stop transistor MP4, MP6 Load transistor MN1, MN4 input transistor INV1 inverter circuit IN input terminal INB input inversion terminal CTL control terminal OUT output terminal VIN input signal VINB input inversion signal VCTL control signal VLS level shifter internal waveform VOUT output signal VDD power supply voltage VSS ground

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C006 AA11 AC11 AF42 BB16 BC03 BF34 FA26 5C080 AA10 BB05 DD09 DD30 EE29 FF11 GG09 JJ03 JJ04 5J056 AA32 BB40 CC02 CC21 CC25 DD13 DD28 FF07 FF09 GG06 KK01 KK03

Claims (6)

[Claims] A level conversion unit having a transistor having a predetermined threshold value and having a current mirror circuit for converting a low-amplitude input signal into a high-amplitude output signal; An offset adding unit that adds and supplies the offset to the level conversion unit; and a bias variable unit that changes a bias for determining the offset to be added based on the input signal and supplies the bias to the offset adding unit. Level shifter circuit. 2. The offset adding section includes a source follower transistor which is a Pch transistor having the input signal as a gate input, and a current source transistor which is a Pch transistor for driving the source follower transistor. 2. The level shifter circuit according to claim 1, wherein “と” is an offset voltage generated between the gate and the source of the source follower transistor according to the state of the current source transistor. 3. 3. The variable bias section includes a Pch transistor and an Nch transistor connected in series for forming an inverter configuration, and a source of the Nch transistor for forming the inverter configuration includes the input signal. Is connected to an input terminal to which is input. A drain of an Nch transistor for forming the inverter configuration and a drain of a Pch transistor for forming the inverter configuration are connected to a gate of the current source transistor. The level shifter circuit according to claim 2. 4. A control unit for outputting a control signal for controlling an on / off state of at least an Nch transistor for forming the inverter configuration, wherein the bias is an Nch for forming the inverter configuration. A bias voltage applied from a drain of the transistor to a gate of the current source transistor, wherein the bias variable section includes: (a) the bias voltage during a period in which an Nch transistor for forming the inverter configuration is on; Is changed based on the state of the input signal to bring the current source transistor into an operating state,
4. The level shifter circuit according to claim 3, wherein (b) the current source transistor is stopped in other periods. 5. The level shifter circuit according to claim 4, further comprising four transistors connected to said current mirror circuit for controlling said output signal based on said control signal regardless of a state of said input signal. . 6. An image display application device using the level shifter circuit according to claim 1.