JP2002280882A - Signal waveform shaping circuit, drive circuit, and display device provided with this drive circuit - Google Patents

Abstract

(57) Abstract: In a driving circuit of a display device, an n-ch TF is provided.
It suppresses deterioration of T and improves reliability and durability. SOLUTION: At least one of a plurality of stages of inverter circuits 21 constituting a clock buffer unit 121 of a scanning line driving circuit 12 is constituted by a NAND circuit 22, and an n-
The voltage applied to the drain of the chTFT was divided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an n-ch TFT
The present invention relates to a signal waveform shaping circuit composed of a TFT and a p-ch TFT thin film transistor, a driving circuit including the signal waveform shaping circuit, and a display device including the driving circuit.

[0002]

2. Description of the Related Art In recent years, liquid crystal display devices have been used as display devices for various devices because of their thinness, light weight, and low power consumption. Among them, an active matrix type liquid crystal display device in which a switch element is arranged for each display pixel is becoming widespread as a display of a notebook PC or a portable information terminal.

At present, as a liquid crystal display device using a thin film transistor (TFT) as a switching element, an amorphous silicon TF in which a driving circuit is arranged outside a glass substrate is used.
And a polysilicon TFT (hereinafter referred to as p-SiT) in which a driving circuit can be arranged around a pixel portion on a glass substrate.
FT). Among them, in the liquid crystal display device using the p-Si TFT, as the screen size becomes larger and the definition becomes higher, the display uniformity and the high quality display within the screen are required, of course.
High reliability and durability are required from the viewpoint of global environmental issues.
Development of products with a long life is essential.

[0004] In a driving circuit arranged on a glass substrate as described above, an n-ch TFT and a p-ch TFT are used as basic elements, and an inverter circuit (NOT circuit), a NAND circuit, a clocked inverter circuit, A NOR circuit and the like are configured.

[0005]

As described above, p-
In a liquid crystal display device using a SiTFT, the number of elements constituting a drive circuit has been increased with the increase in screen size and definition. For example, in the scanning line driving circuit, the output timing of the control signal output from the shift register unit to the level shift unit is controlled by the clock signal supplied from the clock buffer unit. The output timing of the signal has become longer, and the number of stages of the inverter circuit constituting the clock buffer unit has also increased. This inverter circuit is composed of, for example, a CMOS switch composed of an n-ch TFT 1 and a p-ch TFT 2 as shown in FIG. 6A, and when the input (in) becomes a high level as shown in FIG. n-chTF
When T1 is turned on and the potential of the VSS (ground voltage) level is reached and the input (in) is at the low level, the p-ch
The TFT 2 is turned on and becomes the potential of the VDD (power supply voltage) level. By such an operation, an output waveform in which the potential of the input waveform is inverted is extracted from the output (out).

As described above, since the operation timing of the inverter circuit becomes longer as the output timing of the control signal becomes longer, the on-period of the n-ch TFT is shorter than that of the p-ch TFT, and conversely, the off-period is shorter than that of the p-ch TFT. Very long. In the off period, the voltage is continuously applied to the drain of the n-ch TFT, so that the TFT is liable to be deteriorated, causing a change in threshold voltage and a decrease in electron mobility.
In the degraded n-ch TFT, as shown in FIG. 6B, the time until it is actually turned on is delayed, and a large distortion occurs in the output waveform, which hinders stable operation. Also,
Avalanche breakdown occurs depending on the degree of deterioration, and T
The reliability and durability of the FT may be extremely reduced, and the operation of the drive circuit itself may not be guaranteed. And
Due to such deterioration of the TFT, flickering of the screen, display unevenness, line defects, or display failure occur, and the display quality is significantly reduced.

An object of the present invention is to provide a signal waveform shaping circuit that suppresses deterioration of an n-ch TFT, a drive circuit having improved reliability and durability by including the signal waveform shaping circuit, and a drive circuit having the same. It is an object of the present invention to provide a display device having improved reliability and durability, high quality display, and long life.

[0008]

In order to achieve the above object, the invention of claim 1 comprises an n-ch TFT and a p-ch TF.
In a signal waveform shaping circuit in which an inverter circuit formed by combining T and a plurality of inverter circuits is connected and a signal waveform of an input clock is shaped through the plurality of inverter circuits, at least one of the plurality of inverter circuits is configured by a NAND circuit. It is characterized by having done.

According to a second aspect of the present invention, in the first aspect, the NAND circuit includes two p-ch TFTs connected in parallel with a common drain and two n-ch TFTs connected in series. , The two p-chTs
The drain of the FT and the drain of the two n-ch TFTs are shared, the sources of the two p-ch TFTs are connected to a first potential, and the sources of the two n-ch TFTs are connected to a second potential, respectively. It is characterized by the following.

Here, the first potential means a potential level of a power supply voltage, and the second potential means a potential level of a ground voltage. However, the second voltage is not limited to the potential level of 0V.

According to a third aspect of the present invention, in the second aspect, the n-ch transistor constituting the NAND circuit is a single-gate transistor, and the gate electrode of the n-ch transistor has a low level.
The length is longer than the L length of the gate electrode of the p-ch transistor.

According to a fourth aspect of the present invention, in the second aspect, the n-ch transistor constituting the NAND circuit is a double-gate transistor.

According to a fifth aspect of the present invention, in the driving circuit, the output timing of a control signal output from the shift register to the level shifter is controlled by a clock signal supplied from a clock buffer. The clock buffer unit is constituted by the signal waveform shaping circuit of claim 1.

According to a sixth aspect of the present invention, there is provided a first electrode substrate including a pixel electrode connected to each intersection of a plurality of signal lines and a plurality of scanning lines which intersect with each other via a switch element. Display panel having a second substrate including a counter electrode electrically connected to the substrate, a light modulation layer interposed between the substrates, and a scanning line driving circuit for outputting a row selection signal for turning on the switch element to the scanning line And a signal line driving circuit for sequentially sampling a video signal on the signal line, wherein at least the scanning line driving circuit includes a driving circuit according to claim 5.

In a preferred embodiment, the display device includes a driving circuit according to claim 1 in the scanning line driving circuit and the signal line driving circuit.

In a preferred embodiment, the display device is configured as a liquid crystal display device having the light modulation layer as a liquid crystal layer.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to an active matrix type liquid crystal display device using a p-Si TFT will be described below.

FIG. 2 is a circuit diagram showing a liquid crystal display device 100 according to the present embodiment. Here, the pixel unit 1
1, the configuration of an array substrate 10 on which a scanning line driving circuit 12, a signal line driving circuit 13, etc. are formed, and a control circuit 14 are shown.

The pixel section 11 includes a plurality of signal lines 102.
(1st, 2st... Nth) and a plurality of scanning lines 103
(Only one is shown in the figure) are arranged so as to intersect each other, and a p-Si TFT is provided at the intersection of these two electrodes.
Are arranged. The gate electrode of the switch element 104 is commonly connected to the scanning line 103 every horizontal line, and the source electrode is connected to the signal line 102 every vertical line. The drain electrode is connected to the pixel electrode 106, and the auxiliary capacitance 10 electrically connected in parallel with the pixel electrode 106.
7 is connected. The auxiliary capacitance 107 is connected to the scanning line 1
The storage capacitor 107 is connected to a storage capacitor line 108 disposed in parallel with the storage capacitor 03, and a storage capacitor 107 is supplied with a storage capacitor voltage from a power supply circuit (not shown) via the scanning line driving circuit 12 (or directly).

Although not shown, a counter electrode electrically facing the pixel electrode 106 is formed on the surface of the counter substrate bonded to the array substrate 10, and a liquid crystal layer is held between the two substrates. In the present embodiment, the array substrate 10 is defined as a first substrate, the counter substrate is defined as a second substrate, and the liquid crystal layer is defined as a light modulation layer.

The pixel 101 includes the switch element 10 described above.
4, a unit including a pixel electrode 106, an auxiliary capacitor 107, a counter electrode (not shown) and a liquid crystal layer.

The scanning line drive circuit 12 includes a clock buffer unit, a shift register unit, a level shift unit, and an output buffer unit to be described later. A vertical start signal and a vertical clock signal are supplied from the control circuit 14 to the scanning line drive circuit 12 as control signals. Based on these control signals, the scanning lines 10 are controlled.
3 outputs a row selection signal every horizontal scanning period.

The signal line driving circuit 13 includes an analog switch (ASW) 110, a shift register (S / R) 111,
The circuit includes a video bus 112, clock buses 113 and 114, and the like.

The analog switch 110 is connected to the video bus 1 by a column selection signal output from the shift register 111.
12 and the signal line 102 to make the video bus 1
The video signal (Video) supplied through 12 is sampled on a signal line 102. Shift register 111
Converts the horizontal start signal (STU) supplied from the control circuit 14 into the vertical clock signals (CKU, / CK).
The column selection signal is sequentially output to the analog switch 110 by shifting rightward step by step in accordance with the clock cycle of U).

Here, the operation of the liquid crystal display device 100 will be simplified. From the signal line driving circuit 13 to each signal line 102
When the row signal is output to one of the scanning lines 103 from the scanning line driving circuit 12 in synchronization with this, the switching elements 104 existing in the scanning line direction are simultaneously turned on. As a result, the signal line 102 is electrically connected to the pixel electrode 106, and the video signal sampled on the signal line 102 is written to the pixel 101 in the scanning line direction via the switch element 104. The video signal is charged as a signal voltage between the pixel electrode 106 and a counter electrode (not shown), and an image is displayed by a liquid crystal layer (not shown) responding thereto.

Next, the circuit configuration of the scanning line driving circuit 12 will be described with reference to FIG. The scanning line driving circuit 12 includes a clock buffer unit 121, a shift register unit 122, a level shift unit 123, and an output buffer unit 124.

The clock buffer unit 121 includes a plurality of stages of inverter circuits 21 and one NAND circuit connected thereto.
This is a signal waveform shaping circuit configured by the circuit 22. The signal waveform of YCKU (reference clock) supplied from the control circuit 14 (FIG. 2)
And YCLK, / Y
CLK (transfer clock). The description of the other functions of the clock buffer unit 121 is omitted. In the shift register unit 122, the externally supplied YSTU (start signal) is output from the clock buffer unit 121 to YCLK (Φ) and / YCLK (/
Φ), and is output to the level shift unit 123 as a row selection signal (control signal) every horizontal scanning period. “SHUT” is a shut signal input when the operation of the shift register unit 122 is stopped. The row selection signal output from the shift register unit 122 is boosted to a voltage level required for driving the scanning line by the level shift unit 123, and is further current-amplified by the output buffer unit 124. 13 is output. In addition,
“YVSS”, “Y” input to the level shift unit 123
“VDD”, “YGVSS”, and “YGVDD” are power supply voltages supplied from a power supply circuit (not shown).

FIG. 3A is a circuit configuration diagram of the NAND circuit 22. The NAND circuit 22 includes two p-ch TFTs 221 and 22 connected in parallel with a common drain.
2, two n-ch TFTs 223 connected in series,
224, and a p-ch TFT 221;
The drain of 222 and the drain of n-ch TFT 224 are shared, the sources of p-ch TFTs 221 and 222 are connected to VDD (power supply voltage), and the source of n-ch TFT 223 is connected to VSS (ground voltage).
Inputs (in) are given to the gates of the TFTs 221 to 224. In this circuit, when the input (in) becomes high level, the n-ch TFTs 223 and 224 are turned on (the p-ch TFTs 221 and 222 are turned off) and the VSS is turned off.
When the input (in) goes to a low level, the p-ch TFTs 221 and 222 turn on (the n-ch TFTs 223 and 224 turn off) and VDD.
(Power supply voltage) level potential.

Here, looking at the period in which the n-ch TFTs 223 and 224 are turned off,
Since 23 and 224 are connected in series, FIG.
As compared with the case where one n-ch TFT is used, the applied voltage is divided by half. Thus, in the present embodiment, the n-ch TFTs 223 and 22
Since the voltage applied to the drain can be reduced during the period in which the TFT 4 is off, deterioration of the TFT can be suppressed. As a result, as shown in FIG.
The delay of the time until the TFT is actually turned on is reduced, and the distortion of the output waveform can be reduced.

Although the voltage applied to the two n-ch TFTs is not necessarily divided into 1: 1, it is considered that the voltage is divided into about 2: 1 to 4: 1 depending on circuit conditions. Even with such a ratio, the TFT
Needless to say, it is possible to suppress the deterioration of.

In the circuit configuration of the above embodiment, p-
Since the deterioration of the n-ch TFT having a longer off-period than that of the chTFT is suppressed, a stable operation can be obtained for a long period without a change in the threshold voltage and a decrease in the electron mobility. The reliability and durability of the scanning line driving circuit 12 can be improved. Therefore, in the liquid crystal display device 100 including such a scanning line driving circuit 12, high display quality can be obtained without causing flickering of the screen, display unevenness, line defect, display failure, and the like. That is, in the liquid crystal display device 100 of the present embodiment,
It is possible to improve reliability and durability, and achieve high quality display and long life. In addition, since the semiconductor device has such reliability and durability, it can be applied to a driving circuit having a higher driving voltage and a high withstand voltage.

FIG. 4 is a schematic plan view of another embodiment of the NAND circuit shown in FIG. 3, and shows an electrode pattern of a TFT constituting the NAND circuit. In the embodiment shown in FIG. 4, the n-ch TFTs 223 and 224 are constituted by single-gate transistors, and
The channel length L2 of the gate electrodes 233 and 234 of the n-ch TFTs 223 and 224 is longer than the channel length L1 of the gate electrodes 231 and 232 of the gate electrodes 221 and 222.
In general, it is considered that the cause of deterioration of a TFT is hot carriers generated near the drain region, and the magnitude of an electric field for accelerating the deterioration is determined by the channel length L of the gate electrode.
The relationship becomes smaller as the length becomes longer. Therefore, in the case of the electrode configuration as shown in FIG. 4, hot carriers generated near the drain region are reduced, and
Since the deterioration of the FT can be further suppressed, the reliability and durability of the scanning line driving circuit can be further improved. In addition, as shown in FIG.
When the transistors 3 and 224 are formed of double-gate transistors, the same effect can be obtained without increasing the channel length L of the gate electrode.

In the embodiment shown in FIG. 1, a plurality of inverter circuits 21
An example in which one of the NAND circuits 22 is replaced with the NAND circuit 22 has been described. However, the number and connection positions of the NAND circuits 22 are not limited to this embodiment, and can be appropriately changed according to the circuit configuration and circuit design. It is. Further, such a circuit configuration can be applied to the signal line driving circuit 13 in addition to the scanning line driving circuit 12, and the n-ch TFT and the pc
It can be applied to all circuits configured by combining hTFTs.

[0034]

As described above, according to the present invention,
Since deterioration of the TFT in the signal waveform shaping circuit can be suppressed, the reliability and durability of the drive circuit including the signal waveform shaping circuit can be improved, and stable operation can be obtained for a long period of time. Therefore, when this drive circuit is applied to a display device, screen flicker, display unevenness, line defects,
Since high display quality can be obtained without causing display failure or the like, improvement in reliability and durability, high quality display, and long life can be achieved.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a scanning line driving circuit.

FIG. 2 is a circuit configuration diagram showing a liquid crystal display device according to the embodiment.

FIG. 3A is a circuit configuration diagram of a NAND circuit. (B) is an explanatory view showing an input waveform and an output waveform.

FIG. 4 is a schematic plan view of another embodiment of the NAND circuit shown in FIG. 3;

FIG. 5 is a schematic plan view when the n-ch TFT of the NAND circuit shown in FIG. 3 is configured by a double-gate transistor.

FIG. 6A is a circuit configuration diagram of an inverter circuit. (B)
FIG. 3 is an explanatory diagram showing an input waveform and an output waveform.

[Explanation of symbols]

11: pixel portion, 12: scanning line driving circuit, 13: signal line driving circuit, 14: control circuit, 100: liquid crystal display device, 101: pixel, 102: signal line, 103: scanning line,
221, 222 ... p-ch TFT, 223, 224 ... n
-Ch TFT

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/36 H03K 5/01 Z F-term (Reference) 2H093 NC16 NC22 NC34 ND09 ND10 ND47 ND48 5C006 AC11 AC22 AC25 AF50 BB16 BC03 BC20 BF03 BF26 BF27 BF34 FA31 FA33 5C080 AA10 BB05 DD09 EE01 EE17 FF11 GG02 JJ02 JJ03 JJ04 JJ06 KK02 KK07 5J039 BC06 KK10 KK22 KK26 KK34 MM14

Claims (6)

[Claims] 1. A signal waveform shaping circuit in which an inverter circuit formed by combining an n-ch TFT and a p-ch TFT is connected in a plurality of stages, and a signal waveform of an input clock is shaped through the plurality of inverter circuits. NAN at least one of the inverter circuits
A signal waveform shaping circuit comprising a D circuit. 2. The NAND circuit includes two p-ch TFTs connected in parallel with a common drain, and two n-ch TFTs connected in series, and a drain of the two p-ch TFTs. The two n-ch
The drain of the TFT is shared and the two p-ch
The source of the TFT is at the first potential and the two n-chT
The signal waveform shaping circuit according to claim 1, wherein the sources of the FTs are connected to the second potentials, respectively. 3. An n-ch transistor constituting the NAND circuit is a single-gate transistor, and an L length of a gate electrode thereof is longer than an L length of a gate electrode of the p-ch transistor. Item 3. A signal waveform shaping circuit according to Item 2. 4. The signal waveform shaping circuit according to claim 2, wherein the n-ch transistor forming the NAND circuit is a double-gate transistor. 5. A driving circuit configured to control an output timing of a control signal output from a shift register unit to a level shift unit by a clock signal supplied from a clock buffer unit, wherein the clock buffer unit comprises: A drive circuit comprising the signal waveform shaping circuit according to claim 1. 6. A first electrode substrate including a pixel electrode connected to each intersection of a plurality of signal lines and a plurality of scanning lines intersecting each other via a switch element, and a counter electrode electrically connected to the pixel electrode. And a display panel having a light modulation layer interposed between the substrates, a scanning line driving circuit that outputs a row selection signal for turning on the switch element to the scanning lines, and the signal line A signal line driving circuit for sequentially sampling video signals, wherein at least the scanning line driving circuit includes the driving circuit according to claim 5.