JP2002280466A - Semiconductor device - Google Patents

Abstract

(57) Abstract: νMOS which is a semiconductor device for multi-signal input threshold value processing which is easy to manufacture and enables high integration of elements
To provide a transistor. A νMOS transistor circuit including a gate electrode of a CMOS circuit formed on a Si substrate as a floating gate electrode and a plurality of signal input electrodes coupled capacitively to the floating gate electrode via an insulating film. , A plurality of signal input electrodes 5 are formed on the Si substrate to constitute a νMOS transistor circuit. By forming the signal input electrode 5 on the Si substrate, the insulating film between the signal input electrode 5 and the floating gate electrode 3 can be made extremely thin,
High integration of the device becomes possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a floating gate electrode.

[0002]

2. Description of the Related Art In recent years, a neural network, which is a system for exchanging a large amount of data with each other, has been actively studied. As a component of this system, a circuit for performing a product-sum operation of multiple input signals and threshold processing is required. A neuro MOS transistor (νMOS transistor) circuit capable of performing such a multiply-add signal product-sum operation and threshold processing with a simple circuit configuration has been devised.
It is registered under Patent No. 2662559.

FIGS. 6A and 6B show the configuration of a typical νMOS transistor. (A) is a plan view,
(B) is a sectional view. This νMOS transistor is
Reference 1 “Tadashi Shibata and Tadahiro Ohmi, A Funct
ional MOS Transistor Featuring Gate-Level Weighted
Sum and Threshold Operations, IEEE Transactionson
Electron Devices, Vol. 39, No. 6, pp. 1444-1455,
1992 ", and shown in FIGS. 6 (a) and 6 (b).
It is realized by such a structure and layout. ν
The electrode structure of the MOS transistor is similar to that of the EEPROM. The MOS transistor has a floating gate electrode 3 separated by a gate oxide film 2 from a Si substrate 1, and a plurality of signal input electrodes 5 separated by a further interlayer film 4 from the floating gate electrode 3. There is. Structurally, it can be divided into two portions in the direction perpendicular to the surface of the Si substrate 1 in order from an upper layer farther from the Si substrate 1. The first part is a capacitive coupling part between the signal input plural electrodes 5 and the floating gate electrode 3, and the second part is a general MO having the floating gate electrode 3 as an input gate electrode.
It is an S-type field effect transistor (MOSFET).

[ΝMOS Manufacturing Process] When manufacturing a νMOS, an ordinary semiconductor device manufacturing process is used.

[0005] Among the conventional semiconductor device manufacturing techniques, those related to the manufacture of the semiconductor device according to the present invention will be described below.

First, SOI (Semiconductor-On-Silico)
n) SO for manufacturing transistors and integrated circuits on a substrate
I technology will be described. Reference 2 “S. Nakashima, et a
l., Thickness Increment of Buried Oxide in a SIMOX
Wafer by High-temperature Oxidation, IEEE Interna
SIMOX (Separation by IMplanted OXygen) described in National SOI Coference, pp. 71-72, 1994 ".
Substrate, Reference 3 “T. Yonehara, K. Sakaguchi and N. Sat
o, Epitaxial layer transfer by bond and etchback o
f porous Si, Appl. Phys. Lett., Vol. 64, No. 16, 1
8 April, pp. 2108-2110, 1994 ”
ELTRAN (Ep) which is SOI (Bond and Etchback SOI)
itaxial Layer TRANsfer), Reference 4 “M. Bruel, Silicon
on insulator material technology, Electronics Let
ters, Vol. 31, No. 14, pp. 1201-1202, 6th July 199
SO represented by UNIBOND described in 5 "
The I-substrate has been developed and the quality and quantity of the substrate have been improved.

FIG. 9 shows an n-type semiconductor device fabricated on a SIMOX substrate.
FIG. 2 is a cross-sectional view illustrating the structure of a channel MOS transistor. A typical MOS transistor manufactured on a bulk substrate includes a buried oxide layer (buried oxide layer) 6.
Exists, active silicon layer (active Si layer)
7 is different from that of FIG. A microprocessor using a MOS transistor on an SOI substrate as shown in FIG. 9 is also disclosed in Reference 5 “DH Allen, AG Aippers.
pach, DT Cox, NV Phan and SN Storino, A
0.2μm 1.8V SOI 550MHz 64b Power PC Microprocesso
r with Copper Interconnects, IEEE International So
lid-State Circuit Conference, WP 25.7 438-439, 199
It has been developed as represented by 9 ".

A MOS transistor on an SOI substrate has characteristics such as high-speed operation, high integration, and high reliability as compared with a conventional MOS transistor.
Is highly likely to be a basic element and has high marketability. For this reason, it is expected that the price of the SOI substrate will be reduced, the quality will be improved, and the integrated circuit manufacturing technology will be improved.

Although the manufacture of a νMOS transistor on an SOI substrate is suggested in the seventh embodiment of Japanese Patent No. 2666259, the νMOS transistor of this embodiment has the same structure as the above νMOS transistor on the SOI substrate. It was made in.

Next, an electrode wiring embedding technique will be described.

In recent years, in order to improve the degree of integration of LSI,
In order to reduce the wiring delay, which is becoming a dominant factor in increasing the speed of LSIs, various technologies for multi-layer wiring have been researched, developed, and used. One of the technologies that realizes six-layer Cu wiring is Reference 6 “S. Venkatesan, et al., A Hig
h Performance 1.8V, 0.20 μm CMOS Technology with
Copper Metallization, IEEE Int. Electron Devices
Meeting, Tech. Dig., Pp. 769-772, 1997 ”and Reference 7“ D. Edelstein, et al., Full Copper Wiring in
a Sub-0.25 μm CMOS ULSI Technology, IEEE Int. El
ectron DevicesMeeting, Tech.Dig., pp. 773-776, 19
97 ". There is a Damasine technology as described in" Electrical Cu Plating Method and CMP (Chemical
This is a combination of mechanical polishing technology and was developed to use Cu having a lower specific resistance than Al as a wiring material.

The outline of the damascene technology is as follows. A groove in the wiring region is formed in the interlayer insulating film for forming a wiring, a barrier metal for preventing diffusion of Cu is deposited on the bottom and side surfaces of the groove, and Cu is buried in the groove by electroplating. Cu is polished and removed by CMP to form a wiring.

As described above, the technique of wafer polishing has been incorporated into the LSI manufacturing process, so that not only Si wafer vendors but also LSI manufacturers can perform polishing.

[Operation Principle of νMOS Transistor] The operation principle when the νMOS transistor is used as a threshold element will be described below.

First, a threshold element is defined as an element realizing the threshold function of the equation (1), and a negative output type threshold element is defined as a logical inversion of the output value of the equation (1). Is defined as an element. However, x _i is the input value, the w _i weight coefficient to be multiplied to an input value, th is the threshold, f is representative of the output value.

[0016]

(Equation 1)Next, the relationship between the νMOS transistor and the threshold element is explained.
I will tell. FIG. 6C shows the νMOS shown in the above reference 1.
Circuits for realizing threshold elements using transistors
FIG. This circuit is based on the floating gate
N-channel MOSFET with gate electrode as gate electrode
CMOS inverter using p-channel MOSFET
Circuit. FIG. 7 is a circuit diagram showing the circuit of FIG.
is there. V _ddIs the supply voltage, V_ssTo
Ground potential (GND) V₁~ V _nTerminal to input the potential of
The terminals were input [1] to input [n] terminals. This inverter
The circuit is hereinafter referred to as a νMOS inverter.

Operation of νMOS inverter and standard CM
The difference in the operation of the OS inverter lies in the operation of the input unit which is the first part. The input part of the νMOS inverter is formed by capacitive coupling between a plurality of signal input electrodes (terminals) and a floating gate electrode. The second gate is connected to the second gate by the potential of the floating gate electrode related to the potential of the plurality of signal input terminals. The MOS inverter which is a part is driven.

Attention is paid to a capacitance having an important meaning in the input section. FIG. 8 is a diagram illustrating a capacitance component equivalent circuit focusing on the capacitance component of the νMOS inverter. In FIG. 8, the potential of the floating gate electrode is represented by V _fg , the potential of each signal input terminal is represented by V _{1 to} V _n , and the potential of the output terminal is represented by V _out , and the capacitance value between each signal input terminal and the floating gate electrode To C _{1 to} C _n , the floating gate electrode and p
The capacitance value between each terminal of -νMOS, that is, the source, the substrate (or well), and the drain is represented by C _p1 and C _p , respectively.
_p2 , C _p3 , and similarly, the capacitance value between n-νMOS
_n1, was _{C n2, C n 3.} The capacitance between the floating gate electrode and each terminal of the transistor has potential dependence, but here, for simplicity, the description is made as a fixed capacitance value in order to focus on explaining the principle. Various combinations of the relationship between the charge amount and the potential of the floating gate electrode can be considered. In this case, the charge amount on the floating gate electrode is “0” in a state where the floating gate electrode is completely insulated ( 2) Consider the case where the equation holds.

[0019]

(Equation 2) Even with the above limitations, the description of the operating principle does not lose generality.

From the equation (2), the floating gate electrode potential V _fg is expressed by the following equations (3) and (4).

[0021]

(Equation 3) The input value x _i as the threshold element is changed to the input signal potential V _i ,
The weight w _{i is made} to correspond to each input gate capacitance value C _i , and a nonlinear function for performing threshold processing is made to correspond to the input / output characteristics of the p-νMOS and the n-νMOS. Here, V _fg is represented by equation (5), if the threshold for potential (floating gate potential) of the floating gate electrode and V _{ft h,} a value representing the output potential as a logical value was f _out, ν
The relationship between the input and output of the MOS inverter coincides with the relationship between the negative output type threshold elements expressed by equation (6).

[0022]

(Equation 4) Therefore, in order for the νMOS inverter to realize a general threshold element as defined above, it is necessary that linear addition be performed at the input unit.
In the expression (4), it is necessary that the expression (7) is satisfied.

[0023]

(Equation 5) In other words, when the equation (7) holds, the νMOS inverter implements a typical threshold element represented by the equation (1).

Next, the problem of reducing the area of the νMOS will be described.

The equation (7) represents the capacitance value between the floating gate electrode and each electrode of the transistor, C _p1 , C _p2 , C _p
The capacitance C _i between the floating gate electrode and the signal input electrode is made very large as compared with _{p 3} , C _n1 , C _n2 , and C _n3 , and the former is made negligible. , That means. If C _pi is described as a representative of the capacitance value between the floating gate electrode and each electrode of the transistor, C _pi is expressed by equation (8). Here, S _pi is the area of the capacitor, tox ₁ is the gate oxide film thickness which is the distance between the electrodes, and ε ₁ is the dielectric constant of the gate oxide film.

[0026]

(Equation 6) On the other hand, C _i is represented by equation (9). However, S _i is the area of the capacitor, tox ₂ interlayer thickness is the distance between the floating gate electrode and the signal input electrode, epsilon ₂ denotes the dielectric constant of the interlayer film.

[0027]

(Equation 7) In the process for producing the current of the transistor, Si (in the case of νMOS transistors, corresponding to the floating gate electrode) substrate surface and the gate electrode a gate oxide film thickness tox ₁ interlayer thickness between (e.g., tox ₂₎ such as Thinner than other insulating films. This is for the following reason. In an LSI manufacturing process, an insulating film is formed on a Si substrate,
In order to stack a semiconductor material, a metal material, and the like, it is necessary to planarize a two-dimensional plane parallel to the substrate. However, since it is difficult to completely flatten the two-dimensional surface, it is difficult to make the thickness between the upper layers thinner than that of the gate oxide film as the lowermost layer. For this reason, equation (10) holds.

Tox ₁ <tox ₂ (10) Further, since SiO _2, which is the same material as the gate oxide film, is often used as the interlayer film, the dielectric constant is generally ε ₁ = ε ₂ It is.

Therefore, assuming that the area of the transistor is optimized to be as small as possible in order for C _i and C _pi to satisfy the equation (7), as shown in the equation (11), The sum of the area of the capacitance between the electrode and the floating gate electrode needs to be much larger than the sum of the area of the capacitance between the floating gate electrode and the transistor. Here, S _ni represents the area of C _ni which is a representative value of the capacitance value between the n-νMOS electrode and the floating gate electrode.

[0030]

(Equation 8) [Barrier to high integration of νMOS transistor] Currently, νMO
When the S inverter is used as a threshold element, (1
In circuit design, C _i is large, that is, the area occupied by C _i in the layout is large so that the expression 1) is satisfied. Therefore, the layout area is large as compared with a standard CMOS inverter. There is a problem,
This is an obstacle to high integration of νMOS.

[0031] As already mentioned, for reasons of LSI manufacturing process, since it possible to reduce the tox ₂ from tox ₁ is very difficult, in terms of acknowledged this fact, in order to solve the above problems A policy similar to the following technique which is adopted for high integration of DRAM memory cells and reduction in layout area can be considered.

Firstly, as the first proposal is much larger than the dielectric constant epsilon ₁ of the gate oxide film dielectric constant epsilon ₂ of the interlayer film. This is because the insulating film of the DRAM memory cell
Ta, a high dielectric material having a higher dielectric constant than O ₂
Similar to the research and development of ₂ O ₅ film and Ba _x Sr _1-x TiO ₃ film (BST), it is a policy to use a high dielectric material as an interlayer film. For the Ta ₂ O ₅ film, see, for example, Reference 8 “H. Miki, et al., Leakage-current mechan.
ism of a tantal-pentoxide capacitor on rugged Si w
ith a CVD-TiN plate electrode for high-density DRA
Ms, Symposiumon VLSI Technology Digest of Technica
l Papers, pp. 99-100, in _{1999 ", Ba x Sr 1-} x T
iO ₃ for the film literature 9 "K. Ono, et al ., (Ba, Sr) T
_{iO 3 Capacitor Technology for Gbit-Scale} DRAMs, IE
EE Int. Electron Devices Meeting, Tech. Dig., Pp.
803-806, 1998 ".

Next, as a second proposal, the structure of the electrode is devised to increase the effective capacitance value. This is a DRAM
From a planar capacitor structure in which a memory cell is a simple planar type, to a trench structure, a stack structure, and an H structure in which an effective area is increased while suppressing an increase in layout area.
The policy is to use a method similar to that in which various structural devices are devised from a structure based on SG (Hemi-Spherical Grained) technology and a two-dimensional structure to a three-dimensional structure. Reference 10 “H. Sunami, e” describes a trench structure that increases the surface area of an electrode by using the side surface of a moat dug in a substrate as an electrode.
t al., A Corrugated Capacitor Cell (CCC) for Megab
it Dynamic MOS Memories, IEEE Int. Electron Device
s Meeting, Tech. Dig., pp. 806-808, 1982. For a stack structure in which the surface area is increased by extending electrodes in a vertical direction as well as a simple plane, see Reference 11 “M. Koyanagi, H. Sunami, N. Hashimoto
and M. Ahikawa, Novel High Density, Stacked Capac
itor MOS RAM, IEEE Int.Electron Devices Meeting, T
ech. Dig., pp. 348-351, 1978 ". HSG that increases the electrode surface area by about twice by forming a hemispherical convex shape on the surface of Si, which is a capacitor electrode.
For technology, see Reference 12 “H. Watanabe, N. Aoto, S. Adac
hi and T. Kikkawa, Device application and structur
e observation for hemispherical-grained Si, J. App
l. Phys., Vol. 71, No. 7, 1 April, pp. 3538-3543,
1992 ".

[0034]

However, the above policy of using a high dielectric material requires a drastic change in the method of manufacturing a circuit composed of νMOS transistors (νMOS circuit). In addition, even when the electrode structure is devised, methods such as a trench structure and HSG are forced to research and develop a new manufacturing method.

Therefore, it is still an important task to construct a νMOS transistor which is easy to manufacture and enables high integration of elements.

An object of the present invention is to provide a νMOS transistor which is a semiconductor device for multi-signal input threshold value processing which solves the above-mentioned problems, is easy to manufacture, and enables high integration of elements. .

[0037]

In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising the steps of:
Having a semiconductor region of a second conductivity type provided in the semiconductor region and having a semiconductor of a second conductivity type different from the first conductivity type. On the region separating from the drain region, an electrically insulating state provided through an insulating film or a floating gate electrode which can at least transiently be electrically insulated is provided. And a plurality of gate electrodes that are capacitively coupled to the floating gate electrode via an insulating film on the substrate.

According to the present invention, there is provided a semiconductor device having a semiconductor region of a first conductivity type on a substrate, which is different from the first conductivity type provided in the semiconductor region. An electrically insulating state provided with a first insulating film on a region separating the source region and the drain region, the source region and the drain region being semiconductors of a second conductivity type; Or a floating gate electrode capable of at least transiently taking an electrically insulating state, wherein the floating gate electrode and a second insulating film different from the first insulating film are formed. A semiconductor device having a plurality of gate electrodes on the substrate that are capacitively coupled through the substrate.

According to the present invention, there is provided a semiconductor device having a semiconductor region of a first conductivity type on a substrate, which is different from the first conductivity type provided in the semiconductor region. A second conductive type semiconductor having a source region and a drain region, and an insulating state provided over a region separating the source region and the drain region with an insulating film interposed therebetween; Or, having a floating gate electrode capable of at least transiently taking an electrically insulating state, the floating gate electrode, and a plurality of gate electrodes capacitively coupled via an insulating film, on the substrate A semiconductor device is characterized in that the semiconductor device is formed in an upper layer of the floating gate electrode.

According to a fourth aspect of the present invention, the substrate has an insulator layer immediately below the semiconductor region of the first conductivity type. Is constituted.

Further, according to the present invention, as set forth in claim 5, the substrate has an insulator layer directly below the semiconductor region of the first conductivity type, and the semiconductor region is formed immediately below the insulator layer. A semiconductor device according to claim 4 is provided.

According to the present invention, as set forth in claim 6, the plurality of gate electrodes are semiconductor regions formed on the substrate.
Is constituted.

According to a seventh aspect of the present invention, the plurality of gate electrodes are conductor regions embedded on a substrate. A semiconductor device is formed.

According to a further aspect of the present invention, the plurality of gate electrodes are a semiconductor region or a conductor formed on a substrate, and at least one layer is provided immediately below the semiconductor region or the conductor. 4. The semiconductor device according to claim 1, wherein the insulator layer is present.

[0045]

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulating film forming a capacitance between a signal input electrode and a floating gate electrode, and an insulating film forming a capacitance between a floating gate electrode and each electrode of a transistor. The most important feature is that the signal input electrode is formed on a Si substrate. Conventional technology is νMOS
The structure of the capacitance between the signal input electrode and the floating gate electrode in the transistor is different from the structure of the signal input electrode.

In the case where the νMOS inverter is used as a general negative output type threshold element, it is necessary to satisfy the constraint shown in the equation (7). The capacitance value between the signal input electrode and the floating gate electrode is proportional to the area and the dielectric constant, and inversely proportional to the distance between the electrodes, as represented by equation (9). The capacitance value between the floating gate electrode and each electrode of the transistor is represented by equation (8). conventionally,
By extremely increasing the area of the capacitance related to C _i on the layout, the constraint condition of the expression (7) was satisfied. In order to minimize the increase in the area on the layout, it is effective to reduce the inter-electrode distance tox ₂ relates C _i. However, as already mentioned, L
For reasons of the SI manufacturing process, an interlayer film (thin FIG. 6) that is thinner than the insulating film (gate oxide film 2 in FIG. 6) between the Si substrate and the floating gate electrode and has a certain size of area. It is difficult to form the interlayer film 4).

In the present invention, the insulating film between the floating gate electrode and the transistor, that is, the general M
By sharing the gate oxide film in the case of the OS transistor and the insulating film between the signal input electrode and the floating gate electrode, the distance (tox)
₁ and tox ₂ ) can be equal. Further, in the constraint condition, the total value of the capacitance values between the signal input electrode and the floating gate electrode is a comparison target, and since a normal threshold element has a plurality of signal inputs, one signal input The capacitance value between the electrode and the floating gate electrode may be equal to or less than the sum of the capacitance values between one floating gate electrode and each electrode of the transistor. As described above, the use of a common insulating film also leads to a reduction in the number of manufacturing steps.

On the other hand, also by embedding the signal input electrode in the surface of the Si substrate, the channel of the transistor and each electrode and the signal input electrode are formed on the same Si surface, and the gap between the floating gate electrode and the floating gate electrode is formed. The insulating film can be shared.

By forming a signal input electrode similar to a signal input electrode buried on the surface of a Si substrate in the upper layer of a floating gate electrode as in a typical νMOS transistor, the area can be further reduced. Become.

As described above, by implementing the present invention, a large increase in the layout area of the threshold element can be suppressed.

Hereinafter, embodiments of the present invention will be described with reference to a first embodiment, a second embodiment, and a third embodiment.

[First Embodiment] In the first embodiment, a threshold element having a signal input electrode formed on a standard Si substrate will be described. That is, the present disclosure discloses a structure in which a νMOS transistor has a wiring formed on a Si substrate by using the same manufacturing method as that for forming a diffusion layer. This embodiment makes it possible to share an insulating film between the signal input electrode and the floating gate electrode and an insulating film between the floating gate electrode and each electrode of the transistor. It contributes to high integration of the configured threshold element.

FIG. 1 is a conceptual diagram showing a νMOS inverter formed on a Si substrate 1 using a signal input electrode 5 as an n ⁺ diffusion layer. FIG. 1A is a layout diagram showing a portion from a Si substrate 1 to a first-layer polysilicon (Poly-Si) wiring, that is, a floating gate electrode 3, and FIG. N-channel νMOS (n-ν
2 is a cross-sectional view along XY of a (MOS) transistor 11. FIG. In FIG. 1, reference numeral 12 denotes a p-channel νMOS (p-νMOS) transistor combined with an n-νMOS transistor 11, and 13 denotes an n-νMOS transistor 1.
N ⁺ diffusion layers serving as source and drain of No. 1;
Is a p-type well for forming the n-νMOS transistor 11, and 15 is an insulator that separates the two transistors 11 and 12 from each other. Insulating films 16 and 17 exist between the region between the source and the drain and the floating gate electrode 3 and between the signal input electrode 5 and the floating gate electrode 3, respectively (FIG. Only those positions are shown). The p-type well 14 corresponds to the semiconductor region of the first conductivity type according to claim 1, 2 or 3, and the n ⁺ diffusion layer 11 is the semiconductor region of the second conductivity type according to claim 1, 2 or 3. The insulating films 16 and 17 correspond to the insulating film according to claim 1, 2 or 3 (claim 2).
, The floating gate electrode 3 corresponds to the floating gate electrode according to claim 1, 2 or 3, and the signal input electrode 5
Corresponds to the plurality of gate electrodes according to claim 1, 2, 3, or 6.

The source, drain, and signal input electrode 5 can be formed by the same n ⁺ diffusion process, and the insulating films 16 and 17 can be formed by the same process, for example,
Since it can be formed by an oxide film forming process, the manufacturing process can be shortened.

The circuit diagram and the capacitance component equivalent circuit of the circuit having the structure of FIG. 1 are the same as those of FIGS. 7 and 8, respectively. Conventional ν
The MOS transistor, the capacitance value between the signal input electrode and the floating gate electrode shown in FIG. 8 (hereinafter referred to as an input gate capacitance value) interlayer thickness tox for use in C _i
2, the gate oxide film thickness tox ₁ for use in the capacitance value C _pj and C _nj between the floating gate electrode and each of the transistors were different. However, in the structure of a semiconductor device according to the present invention, the insulating film 17 used in C _i is not a interlayer film, a gate oxide film of the transistor, i.e., it is possible to use the equivalent of Enmaku 16, above Tox ₁ and tox ₂ are equal,
_(10): tox 1 <becomes possible to suppress an increase in the input gate capacitance area due to tox _2.

FIG. 2 shows a νMOS inverter in which a first signal input electrode is formed on a Si substrate 1 and a polysilicon or metal wiring above the floating gate electrode 3 is used as a second signal input electrode 18. FIG. FIG. 2A is a layout diagram from the Si substrate 1 to the second-layer polysilicon wiring or the first-layer metal wiring, that is, the signal input electrode 5, and FIG. 2B is a layout diagram. 3A is a cross-sectional view along XY of an n-channel νMOS (n-νMOS) transistor 11 in FIG. The second signal input electrode 18 corresponds to a gate electrode formed in an upper layer portion of the floating gate electrode according to claim 3.

The circuit diagram and the capacitance component equivalent circuit of the circuit having the structure of FIG. 2 are the same as those of FIGS. 7 and 8, respectively. Like the first-layer signal input electrode 5 described above, the electrode in the Si substrate 1 has an effect of reducing the layout area with respect to the signal input electrode of the conventional νMOS transistor. Second signal input electrode
By using the signal input electrode 18 described above, the area can be reduced.

The second signal input electrode 18 can be easily formed because a polysilicon electrode or a metal wiring used in a conventional νMOS transistor is used. Here, the formation of the first signal input electrode 5 will be described.

FIGS. 1 and 2 show an n-νMOS transistor 11 and a p-channel νMOS formed in a double well.
This is an example of a (p-νMOS) transistor 12. The first signal input electrode 5 is formed by implanting and diffusing impurity ions into the surface of the Si substrate, similarly to the source and drain of the MOS transistor. In FIG. 1B and FIG. 2B, a high concentration n ⁺ diffusion layer is formed in the p-type well 14,
Electrodes. The polarity of the electrodes can be roughly classified into a case where the electrodes of the different polarity diffusion layer are present in the plurality of electrodes and a case where all the electrodes have the same polarity. When the different polarity diffusion layer is used, the first signal input electrode 5 adjacent to the n-νMOS transistor 11 is
Similarly, the first signal input electrode 5 adjacent to the p-νMOS transistor 12 is formed as an n ⁺ diffusion layer in the p-type well 14.
This is the case where a p ⁺ diffusion layer is formed in an n-type well as in the case of FIG. When the same polarity electrode is used, the case where the electrode region is element-isolated from at least one of the transistor regions and is formed in one of the two wells by a diffusion layer having a polarity opposite to that of the well is used. It is.

Next, LOCOS (LOCal
An electrode forming procedure when using Oxidation of Silicon) will be described. The same applies to the case where trench isolation and STI (Shallow Trench Isolation), which are isolation methods other than LOCOS, are used.

The point that a diffusion layer is used as the first signal input electrode 5 is the same as the source and drain of the MOS transistor, but the forming procedure is different from that of the source and drain. The source and the drain are ion-implanted using the floating gate electrode 3 as a mask. The first signal input electrode 5 is formed using a dedicated mask at a stage prior to the formation of the floating gate electrode 3. This makes it possible to form the first signal input electrode 5 directly below the floating gate electrode 3.

There are the following problems when the diffusion layer is used as an electrode. That is, since the diffusion layer is used as an electrode, the resistance value of the diffusion layer becomes larger than that of the metal wiring, a PN junction capacitance is generated between the diffusion layer and the well, and a parasitic capacitance exists. In other words, a problem arises in that the RC of the wiring is increased, which leads to an increase in signal delay, and hinders high-speed operation.

As described above, there is a trade-off between high-speed operation and reduction in area.

As described above in the present embodiment,
By forming the first signal input electrode 5 in the Si substrate 1, it becomes possible to share the gate oxide film between the input gate capacitance and the capacitance between the floating gate electrode 3 and the transistor. As a result, it is possible to suppress a large increase in the area cost of the layout of the input gate capacitance, and it is possible to highly integrate the threshold element.

[Second Embodiment] In the second embodiment, a threshold having a signal input electrode formed on a standard Si substrate by applying a technique similar to the damascene technique. The element will be described. That is, the present invention discloses a structure in which a νMOS transistor has a wiring formed on a Si substrate by applying a technique similar to the damascene technique. In this embodiment, as in the first embodiment, not only the insulating film is made common, but also the metal wiring is buried, so that the resistance of the signal input line can be reduced, which contributes to high-speed operation. I do.

FIG. 3 is a conceptual diagram showing a νMOS inverter formed by embedding a metal after forming a barrier metal layer 20 by digging a Si substrate 1 for a signal input electrode. FIG. 1A is a layout diagram showing from the Si substrate 1 to the first-layer polysilicon wiring, that is, from the floating gate electrode 3, and FIG.
FIG. 3A is a cross-sectional view along XY of the n-νMOS transistor 11 in FIG.

The structure of the present embodiment is similar to the structure of the first embodiment. However, instead of using a diffusion layer formed by ion implantation as the signal input electrode 5, metal is used. The difference is that it is embedded in the Si substrate 1 and used as a wiring. The structure of the signal input electrode 5 is Si
Lamination of an insulator thin film 19 typified by SiO ₂ formed on a well of the substrate 1, a barrier metal layer 20 for suppressing diffusion of metal into Si as an upper layer, and a metal electrode (signal input electrode 5) Structure. Depending on the substance used, the insulator thin film 19 and the barrier metal layer 20 can be realized by the same thin film. The signal input electrode 5 corresponds to a plurality of gate electrodes described in claims 1, 2, 3, 7, or 8, and the insulator thin film 19 corresponds to the insulator layer described in claim 8.

In the structure of this embodiment, since the metal is used as the signal input electrode 5, the resistance and the parasitic capacitance of the signal input electrode which are the problems of the first embodiment are reduced. Effective for reduction.

The resistance value is greatly improved. Si
The resistivity of the substrate when boron or phosphorus is doped with impurities is in the order of 1 × 10 ⁻⁴ (Ω · cm) to 1 × 10 ⁻³ , whereas the resistivity of Cu is 2 × 10 ^−6.
(Ω · cm), the resistivity of A1 is 3 × 10 ⁻⁶ (Ω · c
m), and an improvement of two orders or more can be expected.

Next, the parasitic capacitance value is compared between the case where the diffusion layer of the first embodiment is used as an electrode and the case where a metal is laminated on an insulating thin film. FIG. 4 (a) shows the first
N ⁺ diffusion layer and p-type well PN
FIG. 4B is a diagram showing a junction, and FIG. 4B shows a MIS (metal-metal) when SiO ₂ is used as the insulator thin film of the present embodiment.
FIG. 3 is a diagram illustrating an Insulator-Semiconductor junction. Assuming that the gate oxide film thickness between the signal input electrode and the floating gate electrode is SiO ₂ having a thickness of 5 nm to 10 nm, the well has an impurity concentration of 1 × 10 ¹⁶ (cm ⁻³ ).
If the concentration is lower than that, the parasitic capacitance between the signal input electrode and the well becomes about 1/10 of the gate oxide film capacitance,
In addition, even if the MIS structure is used, the depletion layer capacitance in the well becomes dominant, and the effect of reducing the parasitic capacitance by the MIS structure is small. However, if the impurity concentration at the interface between the well and the electrode is about 1 × 10 ¹⁷ (cm ⁻³ ), the MIS structure is effective for reducing the parasitic capacitance.

Hereinafter, an example in which the parasitic capacitance is specifically calculated will be described.

4A and 4B both show the impurity concentration.
The fabric is a staircase junction, and the depletion layer extends only in the well
And the following physics under the assumption that there is no fringe effect
Use a constant. Built-in potential V_bIs 0.8
V, the impurity concentration N near the junction surface of the well is 1 × 10¹⁷
(Cm^-3), SiO₂Permittivity ε_oxIs 3.45 × 1
0 ^-11(F / m), dielectric constant ε of Si_sIs 1 × 10
^-10(F / m). The unit of the PN junction in FIG.
The capacitance value per area is C_PNThen

[0073]

(Equation 9) Holds, and when the junction voltage V is 0 V to 3 V, 4.6 ×
10 ⁻⁴ ≦ C _PN (F / m ² ) ≦ 1.0 × 10 ⁻³ . On the other hand, the capacitance value per unit area of the M1S joint shown in FIG. 4 (b) and C _MIS, and the capacitance value per unit area of the insulating thin film alone and C _{o x,}

[0074]

(Equation 10) Holds, and the voltage V applied between the well and the metal is reduced to 0.
When V to 3 V, when the thickness of the insulating thin film is 10 nm, 4.5 × 10 ⁻⁴ ≦ C _MIS (F / m ² ) ≦ 9.6 ×
10 ⁻⁴ and 3.8 × 10 when the film thickness is 50 nm.
⁻⁴ ≦ C _MIS (F / m ² ) (F / m ² ) ≦ 5.7 × 10
^-4 . Thus, when the impurity concentration is high,
The MIS structure is effective.

Instead of embedding a metal as the signal input electrode, a SiO ₂ thin film is used as an insulator thin film.
Polysilicon can be used instead of metal. Can not be to reduce the resistance value of the electrode, S as SiO ₂ thin film thicker or, Si ₃ relative dielectric constant of about 7 N ₄
By using a material having a higher dielectric constant than iO ₂ , the parasitic capacitance can be suppressed.

As in the case of the first embodiment, a polysilicon layer or a metal wiring layer is provided on the upper layer of the floating gate electrode 3, and the polysilicon layer or the metal wiring layer is provided on the second signal input electrode 18.
And a structure in which the floating gate electrode 3 is sandwiched.

Next, as an example of the formation of the signal input electrode 5 structure, the formation of the signal input electrode using the damascene technique used when forming the multilayer Cu wiring will be described.

First, a groove is formed by etching a predetermined position of the Si substrate. After that, SiO ₂ or Si ₃ N
₄ is formed, and a barrier metal layer for preventing metal diffusion is formed. Next, a metal is applied or deposited or plated to fill the grooves. The metal other than the predetermined area is removed by CMP and smoothed. This allows
An embedded metal electrode is formed. Finally, an oxide film constituting the input gate capacitance is deposited.

As described above, as described in the present embodiment,
By forming the signal input electrode in the Si substrate by the metal embedding technique, it becomes possible to share the gate oxide film between the input gate capacitance and the capacitance between the floating gate electrode and the transistor. As a result, it is possible to suppress a large increase in the area cost of the layout of the input gate capacitance, and it is possible to highly integrate the threshold element.

[Third Embodiment] In the third embodiment, a description will be given of a threshold element having a structure having a signal input electrode formed on an active silicon layer 7 of an SOI substrate. That is, a structure of a νMOS transistor having a wiring formed on an SOI substrate is disclosed. This embodiment is different from the first embodiment and the second embodiment.
In addition to the common use of the insulating film, the parasitic capacitance is reduced because the signal input electrode is separated from the Si substrate, which contributes to the high-speed operation. Also, S
The advantages of the transistor formed on the OI substrate, such as high speed and high density, and the ability to use a low power supply voltage can be inherited.

FIG. 5 shows a SIMO which is one of the SOI substrates.
FIG. 4 is a conceptual diagram illustrating a νMOS inverter in which a signal input electrode 5 is formed on an active silicon layer 7 on an X substrate. FIG. 5A is a layout diagram from the SIMOX substrate to the first-layer polysilicon wiring, that is, the signal input electrode 5, and FIG. 5B is a diagram showing n-ν in FIG. 1A.
FIG. 4 is a cross-sectional view of the MOS transistor 11 at XY.
The source of the transistor in the structure shown in FIG.
The drain region (n ⁺ diffusion layer 13) is in contact with the buried oxide layer 6, and the parasitic capacitance of the source and the drain is equal to the series capacitance of the capacitance sandwiching SiO ₂ of the buried oxide layer 6 and the depletion layer capacitance in the substrate. This is the sum of the PN junction capacitance in the horizontal direction of the substrate. Therefore, the parasitic capacitance of the source and drain of the MOS transistor on the SIMOX substrate is very small. When the signal input electrode 5 has the same structure as the above-described source and drain, the parasitic capacitance can be extremely reduced. The buried oxide layer 6 corresponds to the insulator layer according to claim 4 or 5.

Further, the transistor and the signal input electrode 5 can be easily separated from each other by using the transistor separation technique on the SIMOX substrate (forming the element isolation insulator 15).

The signal input electrode 5 used in this embodiment is similar in structure to the source and drain of the MOS transistor, but is different in the procedure of formation. The source and the drain are formed using the gate electrode 3 as a mask after the floating gate electrode 3 is formed, whereas the signal input electrode 5 is ion-implanted using another mask before the floating gate electrode 3 is formed. You. With this procedure,
An electrode can be formed immediately below the floating gate electrode 3.

As described above in this embodiment,
By forming the signal input electrode 5 on the active silicon layer 7 of the SOI substrate, the gate oxide film can be shared between the input gate capacitance and the capacitance between the floating gate electrode 3 and the transistor. As a result, it is possible to suppress a large increase in the area cost of the layout of the input gate capacitance, and it is possible to highly integrate the threshold element. In addition, M fabricated on an SOI substrate
Features of the OS transistor such as high speed, high density, high integration, and high reliability can be inherited by a νMOS transistor manufactured using an SOI substrate. The performance of the device can be improved.

The production of a νMOS transistor on an SOI substrate is suggested in the seventh embodiment of Japanese Patent No. 2662559. The νMOS transistor of this embodiment has the same structure as the νMOS transistor shown in FIG. SO
ΝMO of the present embodiment manufactured on an I substrate and actively utilizing a unique structure of the SOI substrate.
No proposal has been made for the S circuit, and no proposal has been made to form a wiring in the active silicon layer 7 shown in the sectional structure of FIG.

In each of the above embodiments, the insulating film between the signal input electrode 5 and the floating gate electrode 3 and the insulating film between the floating gate electrode 3 and each electrode of the transistor are common. However, even if different insulating films are used as the two insulating films, there is no problem. The two insulating films in this case correspond to the first and second insulating films described in claim 2.

In each of the above embodiments, as illustrated in FIG. 2, the second layer is formed on the floating gate electrode 3 in the same manner as in a typical νMOS transistor.
And the second signal input electrode 18 provided on the upper layer has a sandwich type structure in which the floating gate electrode 3 is sandwiched by the signal input electrode 18 embedded in the surface of the Si substrate. You can also.

The floating gate electrode 3 in the transistor structure described in the embodiment of the present invention means not only an electrode having a completely floating structure having no terminal connected to the electrode, but also a high impedance And an element or a circuit having a switching function having two or more states of low impedance, and a structure capable of adopting a state that can be regarded as transiently insulated from the viewpoint of the operation speed of the transistor. It should be added that the above-mentioned electrode is also included.

[0089]

According to the present invention, it is possible to provide a νMOS transistor which is a semiconductor device for multi-signal input threshold value processing which is easy to manufacture and enables high integration of elements.

[Brief description of the drawings]

FIG. 1 shows a νMO in which a signal input electrode is formed in a Si substrate.
It is a conceptual diagram of an S inverter, where (a) is a layout diagram and (b) is a sectional view.

FIG. 2 is a diagram illustrating a first signal input electrode formed in a Si substrate;
FIG. 3 is a conceptual diagram of a νMOS inverter in which polysilicon or metal on a floating gate electrode is used as a second signal input electrode, in which (a) is a layout diagram and (b)
Is a sectional view.

FIGS. 3A and 3B are conceptual diagrams of a νMOS inverter in which a signal input electrode is formed on an insulating thin film formed in a Si substrate, wherein FIG. 3A is a layout diagram and FIG. .

4A and 4B are cross-sectional views illustrating an interface between a signal input electrode and a well, wherein FIG. 4A illustrates a PN junction and FIG. 4B illustrates a MIS junction.

FIGS. 5A and 5B are conceptual diagrams of a νMOS inverter in which a signal input electrode is formed in an active silicon layer of a SIMOX substrate, wherein FIG. 5A is a layout diagram and FIG.

FIG. 6 is a conceptual diagram of a typical νMOS inverter,
In the figure, (a) is a layout diagram, (b) is a cross-sectional diagram, (c)
Is a circuit diagram.

FIG. 7 is a circuit diagram of a typical νMOS inverter.

FIG. 8 is an equivalent circuit diagram of a capacitance component of a νMOS inverter.

FIG. 9 shows an n-channel MO manufactured on a SIMOX substrate.
FIG. 3 is a cross-sectional view of an S transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Si substrate, 2 ... Gate oxide film, 3 ... Floating gate electrode, 4 ... Interlayer film, 5 ... Signal input electrode, 6 ... Buried oxide layer, 7 ... Active silicon layer, 8 ... Sapphire, 9 ... p- Si, 10 ... insulator, 11 ... n-νMO
S transistor, 12 ... p-νMOS transistor, 1
3 ... n ⁺ diffusion layer, 14 ... p-type well, 15 ... insulator for element isolation, 16 ... insulating film, 17 ... insulating film, 18 ... second signal input electrode, 19 ... insulating thin film, 20 ... barrier Metal layer.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/792 H01L 29/78 622 29/786 F term (Reference) 5F048 AA01 AA09 AB01 AB04 AC03 AC10 BA16 BB01 BB02 BB05 BB11 BB13 BB19 BE02 BE03 BF03 BF07 5F083 EP02 EP22 EP28 EP48 EP53 GA09 HA02 JA37 PR40 ZA30 5F101 BB12 5F110 AA08 AA30 BB04 BB13 CC02 DD05 DD13 EE24 EE27 EE37 GG02 GG12 NN62

Claims (8)

[Claims] 1. A source region and a drain having a semiconductor region of a first conductivity type on a substrate, wherein the source region and the drain are semiconductors of a second conductivity type provided in the semiconductor region and different from the first conductivity type. And a region, the region separating the source region and the drain region,
An electrically insulating state provided through an insulating film, or a floating gate electrode capable of at least transiently taking an electrically insulated state, wherein the floating gate electrode is insulated. A semiconductor device having a plurality of gate electrodes capacitively coupled via a film on the substrate. 2. A source region and a drain having a semiconductor region of a first conductivity type on a substrate, wherein the source region and the drain are semiconductors of a second conductivity type provided in the semiconductor region and different from the first conductivity type. And a region, the region separating the source region and the drain region,
A floating gate electrode provided through a first insulating film and having an electrically insulated state or at least capable of at least transiently insulated electrically; And a plurality of gate electrodes that are capacitively coupled via a second insulating film different from the first insulating film on the substrate. 3. A source region and a drain having a semiconductor region of a first conductivity type on a substrate, and a semiconductor region of a second conductivity type provided in the semiconductor region and different from the first conductivity type. And a region, the region separating the source region and the drain region,
An electrically insulating state provided through an insulating film, or a floating gate electrode capable of at least transiently taking an electrically insulated state, wherein the floating gate electrode is insulated. A semiconductor device, wherein a plurality of gate electrodes capacitively coupled via a film are formed on the substrate and an upper layer of the floating gate electrode. 4. The semiconductor device according to claim 1, wherein the substrate has an insulator layer immediately below the semiconductor region of the first conductivity type.
4. The semiconductor device according to 2 or 3. 5. The semiconductor according to claim 4, wherein said substrate has an insulator layer immediately below said first conductivity type semiconductor region, and has a semiconductor region immediately below said insulator layer. apparatus. 6. The semiconductor device according to claim 1, wherein said plurality of gate electrodes are semiconductor regions formed on said substrate.
Or the semiconductor device according to 3. 7. The semiconductor device according to claim 1, wherein said plurality of gate electrodes are conductor regions embedded on a substrate. 8. The semiconductor device according to claim 1, wherein said plurality of gate electrodes are semiconductor regions or conductors formed on a substrate, and at least one insulator layer exists immediately below said semiconductor regions or conductors. Item 4. The semiconductor device according to item 1, 2 or 3.