JP2002271030A - Printed wiring board and method of manufacturing printed wiring board - Google Patents

Abstract

(57) Abstract: A printed wiring board capable of reducing loop inductance and a method of manufacturing the printed wiring board are proposed. A chip capacitor is provided in a core substrate of a printed wiring board. This allows I
The distance between the C chip 90 and the chip capacitor 20 is reduced, and the loop inductance can be reduced. Also, since the conductive paste 26 is applied to the surfaces of the electrodes 21 and 22 made of metallized,
The connection resistance on the adhesive material 36 can be increased because the connection resistance on the surface of the substrate 22 can be reduced, and in particular, the unevenness on the surface can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board on which electronic components such as IC chips are mounted and a method of manufacturing the same, and more particularly to a printed wiring board having a built-in capacitor and a method of manufacturing the same.

[0002]

2. Description of the Related Art At present, in a printed wiring board for a package substrate, a chip capacitor is sometimes mounted on a surface for the purpose of, for example, smoothly supplying power to an IC chip.

Since the reactance of the wiring from the chip capacitor to the IC chip depends on the frequency, a sufficient effect cannot be obtained even if the chip capacitor is surface-mounted with the increase in the driving frequency of the IC chip. For this reason, the present applicant has proposed a technique in Japanese Patent Application No. 11-248311 in which a recess is formed in a core substrate and a chip capacitor is accommodated in the recess. Japanese Patent Application Laid-Open No. 6-326472 discloses a technique for embedding a capacitor in a substrate.
JP-A-7-263519, JP-A-10-256429
JP-A-11-45555, JP-A-11-1269
No. 78 and JP-A-11-31868.

Japanese Patent Application Laid-Open No. 6-326472 discloses a technique for embedding a capacitor in a resin substrate made of glass epoxy. With this configuration, power supply noise is reduced, and a space for mounting a chip capacitor is not required, and the size of the insulating substrate can be reduced. In addition, Japanese Patent Application Laid-Open
No. 263619 discloses a technique for embedding a capacitor in a substrate made of ceramic, alumina, or the like. With this configuration, by connecting between the power supply layer and the ground layer, the wiring length is shortened and the wiring inductance is reduced.

[0005]

However, the above-mentioned Japanese Patent Application Laid-Open No. 6-326472 and Japanese Patent Application Laid-open No.
Cannot reduce the distance between the IC chip and the capacitor too much, and could not reduce the inductance as required at present in the higher frequency range of the IC chip. In particular, in the case of a resin-made multilayer build-up wiring board, disconnection between a terminal of a chip capacitor and a via due to a difference in the coefficient of thermal expansion between a capacitor made of ceramic and a core substrate made of resin and an interlayer resin insulating layer. Peeling occurred between the capacitor and the interlayer resin insulation layer, cracks occurred in the interlayer resin insulation layer, and high reliability could not be achieved for a long period of time.

On the other hand, in the invention of Japanese Patent Application No. 11-248311, when there is a displacement in the arrangement of the capacitor, the connection between the terminal of the capacitor and the via cannot be made accurately, and the power supply from the capacitor to the IC chip is not possible. There was a fear that it would not be possible.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a printed wiring board having a built-in capacitor and improved connection reliability, and a method of manufacturing the printed wiring board. It is in.

[0008]

According to a first aspect of the present invention, there is provided a printed wiring board in which an interlayer resin insulating layer and a conductive circuit are alternately laminated on a core substrate containing a capacitor. The core substrate for housing the capacitor is formed by laminating a first resin substrate, a second resin substrate having an opening for housing the capacitor, and a third resin substrate with an adhesive plate interposed therebetween. A technical feature is that a conductive paste is applied to the surface of the electrode formed by metallizing the capacitor.

A technical feature of a method of manufacturing a printed wiring board according to the present invention is characterized in that the method includes at least the following steps (a) to (d): (a) a conductive pad is provided on a first resin substrate; Forming a portion; (b) connecting a capacitor coated with a conductive paste on a metallized electrode via a conductive adhesive to the conductive pad portion of the first resin substrate; 3 and a second resin substrate having an opening for accommodating the capacitor, and the first resin substrate, by connecting the capacitor of the first resin substrate to the opening of the second resin substrate. (C) laminating the third resin substrate with an adhesive plate interposed therebetween so as to close the opening of the second resin substrate; and (d) the first resin substrate and the second resin substrate. Heat the resin substrate and the third resin substrate Step of pressing to form a core substrate.

According to the printed wiring board of the first aspect and the method of manufacturing the printed wiring board of the nineteenth aspect, the capacitor can be accommodated in the core substrate, and the distance between the IC chip and the capacitor is reduced. The loop inductance of the printed wiring board can be reduced. Further, since the resin substrate is laminated, sufficient strength can be obtained for the core substrate. Furthermore, since the first resin substrate and the third resin substrate are provided on both surfaces of the core substrate to make the core substrate smooth, it is necessary to appropriately form an interlayer resin insulating layer and a conductive circuit on the core substrate. As a result, the defective product occurrence rate of the printed wiring board can be reduced.

A circuit formed by a build-up method in which an interlayer resin insulating layer is provided on a core substrate, a via hole or a through hole is formed in the interlayer resin insulating layer, and a conductive circuit as a conductive layer is formed. I have. They include
Either a semi-additive method or a full-additive method can be used.

It is desirable to fill the void with a resin. By eliminating the gap between the capacitor and the core substrate, the built-in capacitor is less likely to behave, and even if a stress originating from the capacitor is generated, the stress can be reduced by the filled resin. The resin also has the effect of reducing adhesion and migration between the capacitor and the core substrate.

Further, since the conductive paste is applied to the surface of the metallized electrode of the capacitor, the electrical connectivity of the metallized electrode having a high surface resistance can be improved. The metallized electrode has irregularities on the surface and cannot be completely adhered even if it is directly connected with a conductive adhesive.However, the irregularity can be eliminated by the conductive paste to improve the adhesion. , Connection resistance can be reduced. In addition, since the metallized electrode is in contact with the surrounding resin layer via the conductive paste, the generation of stress due to the difference in thermal expansion between the electrode and the resin layer is suppressed, and cracks and peeling of the resin layer are eliminated.

According to the second aspect, since the metal layer is provided on the conductive paste of the electrode of the capacitor, it is possible to prevent the occurrence of migration at the electrode and to further reduce the connection resistance. The metallized electrode has irregularities on the surface and cannot be completely adhered even if it is directly connected with a conductive adhesive.However, applying a conductive paste and further providing a metal layer can reduce irregularities. It can be completely eliminated, adhesion can be enhanced, and connection resistance can be reduced.

According to a third aspect, the surface of the capacitor is subjected to a roughening treatment. Thereby, the adhesion between the chip capacitor made of ceramic and the adhesive layer made of resin and the interlayer resin insulating layer is increased, and the adhesive layer and interlayer resin insulating layer are separated at the interface even when the heat cycle test is performed. Nothing.

In the present invention, the surface of the capacitor is subjected to a wettability improving treatment such as silane coupling or application of a resin film. Thereby, the adhesion between the chip capacitor made of ceramic and the adhesive layer made of resin and the interlayer resin insulating layer is increased, and the adhesive layer and interlayer resin insulating layer are separated at the interface even when the heat cycle test is performed. Nothing.

According to the fifth aspect, since the adhesive plate is formed by impregnating the core material with a thermosetting resin, the core substrate can have high strength.

According to the sixth aspect, the first, second, and third resin substrates are obtained by impregnating the core material with a resin, so that the core substrate can have high strength.

According to the seventh aspect, since a plurality of capacitors are accommodated in the core substrate, high integration of the capacitors becomes possible.

In the eighth aspect, since the conductive circuit is formed on the second resin substrate, the wiring density of the substrate can be increased, and the number of interlayer resin insulating layers can be reduced.

In the ninth aspect, a capacitor is provided on the surface in addition to the capacitor housed in the substrate. Since the capacitor is housed in the printed wiring board, the distance between the IC chip and the capacitor is shortened, the loop inductance is reduced, and power can be supplied instantaneously. Because a capacitor is provided, a large-capacity capacitor can be attached.
Large power can be easily supplied to the IC chip.

According to the tenth aspect, since the capacitance of the capacitor on the surface is larger than the capacitance of the capacitor in the inner layer,
There is no shortage of power supply in the high frequency range, and the desired IC
The operation of the chip is ensured.

According to the eleventh aspect, since the inductance of the capacitor on the surface is equal to or greater than the inductance of the capacitor in the inner layer, there is no shortage of power supply in a high frequency region, and a desired operation of the IC chip is ensured.

In the twelfth aspect, the coefficient of thermal expansion of the insulating adhesive is set to be smaller than that of the housing layer, that is, close to that of a capacitor made of ceramic. For this reason, in the heat cycle test, even if internal stress is generated due to a difference in the coefficient of thermal expansion between the core substrate and the capacitor, cracks, peeling, and the like hardly occur on the core substrate, and high reliability can be achieved.

According to the thirteenth aspect, since a chip capacitor having an electrode formed inside the outer edge is used, a large external electrode can be obtained even when conduction is established through a via hole, and the allowable range of alignment is widened. Disappears.

In the fourteenth aspect, since a capacitor having electrodes formed in a matrix is used, it is easy to accommodate a large chip capacitor in the core substrate. Therefore, the capacitance can be increased, so that an electrical problem can be solved. Further, even after various thermal histories, the printed wiring board is less likely to warp.

In the fifteenth aspect, a plurality of chip capacitors for multi-cavity may be connected to the capacitor. As a result, the capacitance can be adjusted appropriately, and I
The C chip can be operated.

In the present invention, the resin film used as the interlayer resin insulating layer and the connecting layer is made of a resin (hereinafter, referred to as a soluble particle) which is soluble in an acid or an oxidizing agent. (Referred to as a soluble resin). The terms "sparingly soluble" and "soluble" used in the present invention are referred to as "soluble" for convenience when those immersed in a solution comprising the same acid or oxidizing agent for the same time have a relatively high dissolution rate. Those having a relatively low dissolution rate are referred to as "poorly soluble" for convenience.

Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble resin particles”), inorganic particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble inorganic particles”), and an acid or an oxidizing agent. Soluble metal particles (hereinafter referred to as “soluble metal particles”) and the like. These soluble particles may be used alone or in combination of two or more.

The shape of the soluble particles is not particularly limited.
Spherical, crushed and the like. The shape of the soluble particles is desirably a uniform shape. This is because a roughened surface having unevenness with a uniform roughness can be formed.

The average particle size of the soluble particles is 0.1.
1 to 10 μm is desirable. Within this particle size range, 2
More than one kind of particles having different particle sizes may be contained. That is, it contains soluble particles having an average particle size of 0.1 to 0.5 μm and soluble particles having an average particle size of 1 to 3 μm.
Thereby, a more complicated roughened surface can be formed,
Excellent adhesion to conductor circuits. In the present invention, the particle size of the soluble particles is the length of the longest portion of the soluble particles.

Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like. When immersed in a solution containing an acid or an oxidizing agent, the soluble resin particles have a higher dissolution rate than the hardly soluble resin. If it is, there is no particular limitation. Specific examples of the soluble resin particles include, for example, those made of epoxy resin, phenol resin, polyimide resin, polyphenylene resin, polyolefin resin, fluororesin, and the like, and may be made of one of these resins. Alternatively, it may be composed of a mixture of two or more resins.

As the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, various modified polybutadiene rubbers such as epoxy-modified, urethane-modified, (meth) acrylonitrile-modified, and (meth) acrylonitrile-butadiene rubber containing a carboxyl group. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. In other words, when dissolving the soluble resin particles using an acid, an acid other than a strong acid can be dissolved, and when dissolving the soluble resin particles using an oxidizing agent, permanganese having a relatively weak oxidizing power is used. Acid salts can also be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, the acid or the oxidizing agent does not remain on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after forming the roughened surface, the catalyst is not applied or the catalyst is oxidized. Or not.

Examples of the soluble inorganic particles include particles made of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds and silicon compounds.

Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and
Examples of the potassium compound include potassium carbonate.Examples of the magnesium compound include magnesia, dolomite, and basic magnesium carbonate.Examples of the silicon compound include silica and zeolite. Is mentioned. These may be used alone or in combination of two or more.

Examples of the soluble metal particles include, for example,
Copper, nickel, iron, zinc, lead, gold, silver, aluminum,
Examples include particles made of at least one selected from the group consisting of magnesium, calcium, and silicon. These soluble metal particles may have a surface layer coated with a resin or the like in order to ensure insulation.

When two or more of the above-mentioned soluble particles are used in combination, the combination of the two types of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both have low conductivity, so that the insulation of the resin film can be ensured, and thermal expansion can be easily adjusted with the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin film. This is because peeling does not occur between the interlayer resin insulating layer and the conductor circuit.

The hardly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed using an acid or an oxidizing agent in the interlayer resin insulating layer. Examples thereof include thermosetting resins, thermoplastic resins, and composites thereof. Further, a photosensitive resin obtained by imparting photosensitivity to these resins may be used. By using a photosensitive resin, an opening for a via hole can be formed in an interlayer resin insulating layer by using exposure and development processes. Among these, those containing a thermosetting resin are desirable. Thereby, the shape of the roughened surface can be maintained even by the plating solution or various heat treatments.

Specific examples of the hardly soluble resin include, for example, epoxy resin, phenol resin, polyimide resin,
Examples thereof include polyphenylene resin, polyolefin resin, and fluorine resin. These resins may be used alone or in combination of two or more. Further, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the above-described roughened surface be formed, but also excellent in heat resistance, etc., even under heat cycle conditions, stress concentration does not occur in the metal layer, and peeling of the metal layer does not easily occur. Because.

Examples of the epoxy resin include cresol novolak type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolak type epoxy resin, alkylphenol novolak type epoxy resin, biphenol F type epoxy resin, and naphthalene type epoxy resin. Resin, dicyclopentadiene type epoxy resin, epoxidized product of condensate of phenols and aromatic aldehyde having phenolic hydroxyl group,
Triglycidyl isocyanurate, alicyclic epoxy resin and the like. These may be used alone or in combination of two or more. Thereby, it becomes excellent in heat resistance and the like.

In the resin film used in the present invention, the soluble particles are desirably substantially uniformly dispersed in the hardly-soluble resin. It is possible to form a roughened surface with unevenness of uniform roughness, and even if via holes and through holes are formed in the resin film, it is possible to secure the adhesion of the metal layer of the conductor circuit formed thereon. Because you can. Alternatively, a resin film containing soluble particles only in the surface layer forming the roughened surface may be used. Thereby,
Since the portions other than the surface layer of the resin film are not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulating layer is reliably maintained.

In the above resin film, the amount of the soluble particles dispersed in the poorly soluble resin is desirably 3 to 40% by weight based on the resin film. If the amount of the soluble particles is less than 3% by weight, it may not be possible to form a roughened surface having desired irregularities. If the amount exceeds 40% by weight, the soluble particles may be dissolved using an acid or an oxidizing agent. In addition, there is a case where the resin film is melted to a deep portion of the resin film and the insulation between the conductor circuits via the interlayer resin insulating layer made of the resin film cannot be maintained, which may cause a short circuit.

The resin film desirably contains a curing agent and other components in addition to the soluble particles and the hardly-soluble resin. As the curing agent, for example,
Imidazole-based curing agents, amine-based curing agents, guanidine-based curing agents, epoxy adducts of these curing agents and microcapsules of these curing agents, and organic materials such as triphenylphosphine, tetraphenylphosphonium, and tetraphenylborate. Phosphine compounds and the like can be mentioned.

The content of the curing agent is desirably 0.05 to 10% by weight based on the resin film. 0.
If the amount is less than 05% by weight, the resin film is insufficiently cured, so that the degree of penetration of the acid or the oxidizing agent into the resin film is increased, and the insulating property of the resin film may be impaired. On the other hand, when the content exceeds 10% by weight, an excessive curing agent component may modify the composition of the resin, which may cause a decrease in reliability.

The other components include, for example, fillers such as inorganic compounds or resins which do not affect the formation of the roughened surface. As the inorganic compound, for example,
Examples of the resin include silica, alumina, and dolomite. Examples of the resin include a polyimide resin, a polyacryl resin, a polyamideimide resin, a polyphenylene resin, a melanin resin, and an olefin resin. By incorporating these fillers, the performance of the printed wiring board can be improved by matching the thermal expansion coefficient, improving heat resistance and chemical resistance, and the like.

Further, the resin film may contain a solvent. As the solvent, for example, acetone,
Ketones such as methyl ethyl ketone and cyclohexanone,
Ethyl acetate, butyl acetate, cellosolve acetate, and aromatic hydrocarbons such as toluene and xylene. These may be used alone or in combination of two or more.

[0047]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. First, the configuration of the printed wiring board according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 7 shows a cross section of the printed wiring board 10, and FIG. 8 shows a state where the IC chip 90 is mounted on the printed wiring board 10 shown in FIG.

As shown in FIG. 7, the printed wiring board 10
Is composed of a core substrate 30 accommodating a plurality of chip capacitors 20, and build-up wiring layers 80A and 80B. The build-up wiring layers 80A and 80B are
And interlayer resin insulating layers 140 and 240. A conductor circuit 58 and a via hole 60 are formed in the upper resin layer 40, and a conductor circuit 158 and a via hole 160 are formed in the upper and lower interlayer resin insulation layers 140. The insulating layer 240 includes a conductor circuit 258
And via holes 260 are formed. A solder resist layer 70 is formed on interlayer resin insulation layer 240. The build-up wiring layer 80A and the build-up wiring layer 80B are connected via a through hole 56 formed in the core substrate 30.

The chip capacitor 20 includes a first electrode 21 and a second electrode 22 as shown in FIG.
A first conductive film 24 connected to the first electrode 21 side and a second conductive film 25 connected to the second electrode 22 side. A plurality of sheets are arranged facing each other. The surfaces of the first electrode 21 and the second electrode 22 are coated with a conductive paste 26.

Here, the first electrode 21 and the second electrode 22
Consists of a metallization of Ni, Pb or Ag metal.
The conductive paste 26 is made of a paste containing metal particles such as Cu, Ni or Ag. Here, the particle size of the metal particles is desirably 0.1 to 10 μm, and most preferably 1 to 5 μm. As the conductive paste, an organic conductive paste obtained by adding a thermosetting resin such as an epoxy resin or a polyphenylene sulfide (PPS) resin to metal particles is preferable. The thickness of the conductive paste 26 is 1 to 30 μm.
m is desirable. If the thickness is less than 1 μm, unevenness on the electrode surface cannot be eliminated, while if it exceeds 30 μm, the effect is not particularly improved. Here, a thickness of 5 to 20 μm is most desirable. Note that a paste in which two or more kinds of particles having different diameters are mixed can be used, and further, a metal paste having two or more kinds of different diameters can be coated.

In the first embodiment, since the conductive paste 26 is applied to the surfaces of the electrodes 21 and 22 made of metallized capacitor 20, the electrical connection between the electrodes 21 and 22 made of metallized and having high resistance is improved. can do. The electrodes 21 and 22 made of metallized
Although there is unevenness on the surface, even if a direct connection is made with the adhesive material 36, complete adhesion cannot be achieved. However, unevenness can be eliminated by the conductive paste 26, thereby improving adhesion and reducing connection resistance. . Also, the electrodes 21 and 22 made of metallization are used as prepregs 38 serving as a resin filler.
a, 38b, and the core substrate 30 are in contact with each other via the conductive paste 26, so that the generation of stress due to the difference in thermal expansion between the electrodes 21, 22 and the resin filler and the core substrate 30 is suppressed, and the resin filler is separated, The occurrence of cracks in the core substrate 30 is eliminated.

As shown in FIG. 8, pads 92P1, 9 of IC chip 90 are provided on upper build-up wiring layer 80A.
A solder bump 76U for connection to 2P2 is provided. On the other hand, on the lower build-up wiring layer 80B, solder bumps 76D for connection to the pads 94P1 and 94P2 of the daughter board 95 are provided.

Grounding pad 92P1 of IC chip 90
Means bump 76U-conductor circuit 258-via hole 26
0-conductor circuit 158-via hole 160-conductor circuit 5
It is connected to the first electrode 21 of the chip capacitor 20 via the 8-via hole 60. Meanwhile, daughter board 9
The fifth grounding pad 94P1 is connected to the first electrode 21 of the chip capacitor 20 via the bump 76D-via hole 260-conductor circuit 158-via hole 160-through hole 56-conductor circuit 58-via hole 60. .

Power supply pad 92P2 of IC chip 90
Means bump 76U-via hole 260-conductor circuit 15
It is connected to the second electrode 22 of the chip capacitor 20 via the 8-via hole 160-the conductor circuit 58-the via hole 60. On the other hand, the power supply pad 94P2 of the daughter board 95 has a bump 76D, a via hole 260, a conductor circuit 158, a via hole 160, a through hole 56,
The second connection of the chip capacitor 20 through the via hole 60
It is connected to the electrode 22. Although not shown, an IC
Chip signal pads are printed circuit board conductor circuits,
It is connected to signal pads on the daughter board via via holes and through holes.

As shown in FIG. 7, the core substrate 30 of the present embodiment has a first resin substrate 30a having a conductive pad portion 34 connected to the chip capacitor 20 formed on one side, and a first resin substrate 30a for bonding to the first resin substrate 30a. A second resin substrate 30b connected via a resin layer (adhesive plate) 38a and a second resin substrate 30b
And a third resin substrate 30c connected to the third resin substrate via an adhesive resin layer (adhesive plate) 38b. An opening 30 </ b> B that can accommodate the chip capacitor 20 is formed in the second resin substrate 30 b.

As a result, the chip capacitor 20 can be accommodated in the core substrate 30, so that the IC chip 9
Since the distance between 0 and the chip capacitor 20 becomes shorter, the loop inductance of the printed wiring board 10 can be reduced. Also, the first resin substrate 30a, the second resin substrate 30b,
Since the third resin substrate 30c is laminated, the core substrate 30
Sufficient strength can be obtained. Further, the core substrate 30
The first resin substrate 30a and the third resin substrate 30c are disposed on both surfaces of the core substrate 30 so that the core substrate 30 can be formed smoothly. Therefore, the resin layers 40, 140, 240 and the conductor circuits 58, 158, 258 can be formed appropriately, and the defective product occurrence rate of the printed wiring board can be reduced.

Further, in the present embodiment, as shown in FIG. 1D, an insulating adhesive 34 is interposed between the first resin substrate 30a and the chip capacitor 20. Here, the coefficient of thermal expansion of the adhesive 34 is set to be smaller than that of the core substrate 30, that is, close to the chip capacitor 20 made of ceramic. Therefore, in the heat cycle test, the core substrate and the adhesive layer 40 and the chip capacitor 20
Even if internal stress is generated due to the difference in the coefficient of thermal expansion between the core substrate and the core substrate, cracks, peeling, and the like hardly occur on the core substrate, and high reliability can be achieved. Further, occurrence of migration can be prevented.

Next, a method of manufacturing the printed wiring board described above with reference to FIG. 7 will be described with reference to FIGS.

(1) A copper-clad laminate in which a copper foil 32 is laminated on one surface of a first resin substrate 30a obtained by impregnating a core material such as a glass cloth having a thickness of 0.1 mm with a BT (bismaleimide triazine) resin and curing the resin. A laminate is used as a starting material (see FIG. 1A). Next, a conductive pad portion 34 is formed on one surface of the first resin substrate 30a by etching the copper foil 32 side of the copper-clad laminate in a pattern.
(B)).

Note that a substrate made of ceramic, AIN, or the like could not be used as the core substrate. This is because the substrate has poor external formability, and may not be able to accommodate a capacitor, and may cause voids even when filled with resin.

(2) Thereafter, an adhesive material 36 such as a solder paste or a conductive paste is applied to the conductive pad portion 34 using a printing machine (see FIG. 1C). At this time, potting may be performed in addition to the application. Examples of the solder paste include Sn / Pb, Sn / Sb, Sn / Ag, and Sn.
Any of / Ag / Cu can be used. Then, a filler 33 is disposed between the conductive pads 34 (FIG. 1).
(D)). This makes it possible to fill the gap between the chip capacitor 20 and the first resin substrate 30a as described later. Next, the chip capacitors 20 made of a plurality of ceramics are placed on the conductive pad portions 34, and the chip capacitors 20 are connected to the conductive pad portions 34 via the adhesive material 36 (see FIG. 2A). One or a plurality of chip capacitors 20 may be used, but using a plurality of chip capacitors 20 enables high integration of the capacitors.

(3) Next, a prepreg (adhesive resin layer) 38 in which a core material such as glass cloth is impregnated with an epoxy resin.
a, 38b and a core material such as glass cloth impregnated with a BT resin and cured to form a second resin substrate 30b (0.4 m thick).
m), a third resin substrate 30c (0.1 mm thick) is prepared. The prepreg 38a and the second resin substrate 30b include:
Through holes 38A, 30B capable of accommodating chip capacitor 20
Is formed. First, the second resin substrate 30b is mounted on the third resin substrate 30c via the prepreg 38b.
Next, the first resin substrate 30a is inverted and placed on the second resin substrate 30b via the prepreg 38a. That is,
Chip capacitor 20 connected to first resin substrate 30a
Are oriented so as to face the prepreg 38a side so that the chip capacitor 20 can be accommodated in the through hole formed in the second resin substrate 30b (see FIG. 2B). Thereby, the chip capacitor 20 can be accommodated in the core substrate 30, and a printed wiring board with reduced loop inductance can be provided.

(4) Then, the first, second, and third resin substrates 30a, 30b, and 30c are integrated in a multilayer shape by pressing the superposed substrates by using a hot press. Core substrate 3 having chip capacitor 20
0 is formed (see FIG. 2C). Here, first, the epoxy resin (insulating resin) is extruded from the prepregs 38a and 38b to the surroundings by being pressurized to fill the gap between the opening 30B and the chip capacitor 20. Furthermore,
The epoxy resin is cured by being heated at the same time as the pressurization, and the prepregs 38a and 38b are interposed as adhesive resins, so that the first resin substrate 30a and the second resin substrate 30 are interposed.
b and the third resin substrate 30c are firmly bonded. In addition,
In the present embodiment, the gap in the opening 30B is filled with the epoxy resin coming out of the prepreg.
It is also possible to arrange a filler in the opening 30B. Here, since the first resin substrate 30a and the third resin substrate 30c have smooth surfaces on both sides of the core substrate 30, the smoothness of the core substrate 30 is not impaired, and the resin layer 40 and the conductor The circuit 58 can be formed appropriately, and the occurrence rate of defective products on the printed wiring board can be reduced. Further, sufficient strength can be obtained for the core substrate 30.

(5) A thermosetting resin film, which will be described later, is vacuum-press-laminated on the substrate 30 having undergone the above steps at a pressure of 5 kg / cm ² while the temperature is raised to a temperature of 50 to 150 ° C.
An interlayer resin insulating layer 40 is provided (see FIG. 2D). The degree of vacuum during vacuum compression is 10 mmHg.

(6) Next, a via hole opening 42 is formed in the interlayer resin insulation layer 40 on the first resin substrate 30a side and the first resin substrate 30a by laser to reach the conductor pad portion 34 (FIG. 3A). reference).

(7) Then, through holes 44 for through holes are formed in the core substrate 30 by using a drill or a laser (see FIG. 3B). Thereafter, desmear treatment is performed using oxygen plasma. Alternatively, desmear treatment with a chemical such as permanganate may be performed.

(8) Next, S manufactured by Japan Vacuum Engineering Co., Ltd.
Plasma processing is performed using V-4540, and core substrate 3
A roughened surface 46 is formed on the entire surface of 0. At this time, argon gas is used as an inert gas, and plasma processing is performed for 2 minutes under the conditions of power 200 W, gas pressure 0.6 Pa, and temperature 70 ° C. After that, sputtering using Ni and Cu as targets is performed to form a Ni / Cu metal layer 48 on the surface of the interlayer resin insulating layer 40 (see FIG. 3C).
Here, sputtering is used, but a metal layer such as copper or nickel may be formed by electroless plating. Also,
In some cases, the electroless plating film may be formed after the formation by sputtering. Roughening treatment may be performed with an acid or an oxidizing agent. The roughened layer has a thickness of 0.1 to 5 μm.
Is desirable.

(9) Next, a photosensitive dry film is stuck on the surface of the Ni / Cu metal layer 48, a mask is placed, and exposure and development are performed to form a resist 50 having a predetermined pattern (FIG. 3). (D)). Then, the core substrate 30 is immersed in an electrolytic plating solution, an electric current is passed through the Ni / Cu metal layer 48, and an electrolytic plating is performed on the non-formed portion of the resist 50 under the following conditions to form an electrolytic plated film 52 (FIG. 4
(A)).

[Aqueous electrolytic plating solution] Sulfuric acid 2.24 mol / l Copper sulfate 0.26 mol / l Additive (manufactured by Atotech Japan, Capparaside HL) 19.5 ml / l [Electroplating conditions] Current density 1 A / dm ² Time 120 minutes Temperature 22 ± 2 ℃

(10) After removing and removing the resist 50 with 5% NaOH, the Ni—Cu alloy layer 48 under the resist 50 is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid, and hydrogen peroxide. 16-μm-thick through-hole 56 formed of a Cu alloy layer 48 and an electrolytic plating film 52
And a conductor circuit 58 (including the via hole 60). Then, after the substrate is washed with water and dried, an etching solution is sprayed on both surfaces of the substrate by spraying to etch the surfaces of the through-hole 56 and the conductor circuit 58 (including the via-hole 60). A roughened surface 62 is formed on the entire surface of the conductor circuit 58 (including the via hole 60) (see FIG. 4B). As an etching solution, a mixture of 10 parts by weight of an imidazole copper (II) complex, 7 parts by weight of glycolic acid, 5 parts by weight of potassium chloride, and 78 parts by weight of ion-exchanged water is used.

(11) A resin filler 64 containing an epoxy resin as a main component is filled in the through hole 56, and is dried by heating. (See FIG. 4C).

(12) Thereafter, the thermosetting resin film used in the step (5) is vacuum-press-laminated at a pressure of 5 kg / cm ² while raising the temperature to a temperature of 50 to 150 ° C., and an interlayer resin insulating layer 140 is provided. (See FIG. 4D). The degree of vacuum during vacuum compression is 10 mmHg.

(13) Next, a via hole opening 142 is formed in the interlayer resin insulating layer 140 by laser (see FIG. 5A).

(14) Thereafter, the steps (8) to (10) are repeated, so that N
A 16 μm-thick conductor circuit 158 (including the via hole 160) and a roughened surface 162 composed of the i-Cu alloy layer 148 and the electrolytic plating film 152 are formed (see FIG. 5B).

(15) Further, by repeating the steps (12) to (14), an interlayer resin insulating layer 240, a conductor circuit 258 (including a via hole 260) and a roughened surface 262 are formed as upper layers (FIG. 5). (C)).

(16) Next, a cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) so as to have a concentration of 60% by weight was used. Oligomer for imparting properties (molecular weight 4000) 46.67
15 parts by weight of a bisphenol A type epoxy resin (trade name: Epicoat 1001 manufactured by Yuka Shell Co., Ltd.) of 80% by weight dissolved in methyl ethyl ketone, imidazole hardener (trade name: 2E4MZ-CN)
1.6 parts by weight, 3 parts by weight of a polyfunctional acrylic monomer (manufactured by Kyoei Chemical Co., trade name: R604) as a photosensitive monomer,
Similarly, polyvalent acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., trade name:
1.5 parts by weight of DPE6A) and 0.71 part by weight of a dispersant antifoaming agent (manufactured by San Nopco, trade name: S-65) are placed in a container, stirred and mixed to prepare a mixed composition. Of benzophenone (manufactured by Kanto Kagaku) and 0.2 parts by weight of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer were added to give a viscosity of 25.
A solder resist composition (organic resin insulating material) adjusted to 2.0 Pa · s at ° C is obtained. The viscosity was measured using a B-type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.) at 60 rpm with rotor No. 4, and at 6 rpm with rotor N.
According to o.3.

(17) Next, the solder resist composition is applied on both sides of the substrate 30 to a thickness of 20 μm,
After performing a drying process under the conditions of 20 ° C. for 20 minutes and 70 ° C. for 30 minutes, a 5 mm-thick photomask on which a pattern of the solder resist opening is drawn is applied to the solder resist layer 70.
And exposed to ultraviolet light of 1000 mJ / cm ² ,
An opening 71 is formed by developing with a DMTG solution (FIG. 6).
(A)).

(18) Next, the substrate on which the solder resist layer (organic resin insulating layer) 70 has been formed is coated with nickel chloride (2.3 × 10 ^-1 mol / l) and sodium hypophosphite (2.8 × 10 ^-1 mol / l). 10 ^-1 mol / l) and an electroless nickel plating solution having a pH of 4.5 containing sodium citrate (1.6 × 10 ^-1 mol / l) for 20 minutes.
Then, a nickel plating layer 72 having a thickness of 5 μm is formed. Further, the substrate was subjected to potassium gold cyanide (7.6 × 10 ^−3).
mol / l), ammonium chloride (1.9 × 10 ^-1 mo)
1 / l), sodium citrate (1.2 × 10 ^-1 mol)
/ L), sodium hypophosphite (1.7 × 10 ^-1 mol)
/ L) is immersed for 7.5 minutes at 80 ° C. in an electroless plating solution containing
An m-th gold plating layer 74 is formed (see FIG. 6B).

(19) Thereafter, the solder resist layer 70
The solder paste is printed on the opening 71 of
Reflow solder bumps (solder bodies) 7
6U and 76D are formed. Thereby, the solder bumps 76
The printed wiring board 10 having U and 76D can be obtained (see FIG. 7).

Next, mounting of the IC chip 90 on the printed wiring board 10 completed in the above-described steps and mounting on the daughter board 95 will be described with reference to FIG. The IC chip 90 is placed so that the solder pads 92P1 and 92P2 of the IC chip 90 correspond to the solder bumps 76U of the completed printed wiring board 10, and the IC chip 90 is mounted by performing reflow. Similarly, a daughter board 95 is attached to the solder bump 76D of the printed wiring board 10.
Are reflowed so that the pads 94P1 and 94P2 correspond to the printed wiring board 10
Attach.

Next, a printed wiring board according to a modification of the first embodiment of the present invention will be described with reference to FIG. The printed wiring board of the modified example is substantially the same as the above-described first embodiment. However, in the printed wiring board of this modified example, the conductive pins 84 are provided, and are formed so as to be connected to the daughter board via the conductive pins 84.

FIG. 13B shows a cross section of a chip capacitor 20 according to a first modification. In the first embodiment, the surface of the capacitor is subjected to a roughening treatment to improve the adhesiveness with the resin, but in a modified example, a polyimide film 23b is formed instead to improve the surface wettability. I have. Instead of the polyimide film, the surface of the capacitor may be subjected to a silane coupling treatment.

In the first modification, the conductive paste 2
6, a composite metal film 28 composed of an electroless copper plating film 28a and an electrolytic copper plating film 28b is formed. The thickness of the composite metal film 28 is desirably 0.1 to 10 μm.
５5 μm is optimal. Instead of a composite metal film, it is also possible to form a single-layer metal film.

In the first modification, the electrode 2 of the capacitor 20
Since the metal layer 28 is provided on the conductive pastes 1 and 22, the occurrence of migration at the electrodes 21 and 22 can be prevented, and the connection resistance can be further reduced. The electrodes 21 and 22 made of metallized
Although there is unevenness on the surface, even if a direct connection is made with the adhesive material 36, it cannot be completely adhered. However, it is possible to completely eliminate the unevenness by applying the conductive paste 26 and further providing the metal layer 28. It is possible to increase the adhesion and lower the connection resistance.

In the first embodiment described above, only the chip capacitor 20 housed in the core substrate 30 is provided. However, in the first modification, a large-capacity chip capacitor 86 is mounted on the front and back surfaces. I have.

The IC chip instantaneously consumes a large amount of power and performs complicated arithmetic processing. Here, in order to supply a large electric power to the IC chip side, in a modified example, a chip capacitor 20 and a chip capacitor 86 for power supply are provided on the printed wiring board. The effect of the chip capacitor will be described with reference to FIG.

FIG. 12 shows the voltage supplied to the IC chip on the vertical axis and the time on the horizontal axis. Here, the two-dot chain line C
Indicates voltage fluctuation of a printed wiring board without a power supply capacitor. When the power supply capacitor is not provided, the voltage greatly decreases. A broken line A indicates a voltage fluctuation of a printed wiring board having a chip capacitor mounted on the surface. Although the voltage does not drop much as compared with the two-dot chain line C, the rate-limiting power supply cannot be performed sufficiently because the loop length is long. That is, the voltage drops at the start of power supply. The two-dot chain line B indicates the voltage drop of the printed wiring board having the chip capacitor described above with reference to FIG. Although the loop length has been shortened,
Since a large-capacity chip capacitor cannot be accommodated in the core substrate 30, the voltage fluctuates. here,
A solid line E indicates the voltage fluctuation of the printed wiring board of the modification in which the chip capacitor 20 in the core substrate described above with reference to FIG. 9 and the large-capacity chip capacitor 86 are mounted on the surface. A chip capacitor 20 near the IC chip
And a large-capacity (and relatively large inductance) chip capacitor 86 minimizes voltage fluctuations.

Next, a printed wiring board according to a second embodiment of the present invention will be described with reference to FIG. The configuration of the printed wiring board of the second embodiment is substantially the same as that of the above-described first embodiment. However, in the printed wiring board 210 of the second embodiment, the conductor circuit 35 is formed on one surface of the first resin substrate 30a and the third resin substrate 30c, and the second resin substrate 30b having the opening 30B for accommodating the chip capacitor 20 is provided. The conductor circuit 37 is formed on both surfaces of the substrate. In the second embodiment, the conductor circuit 35 is formed on one surface of the first resin substrate 30a and the third resin substrate 30c, and the conductor circuit 37 is formed on both surfaces of the second resin substrate 30b. This has the advantage that the number of interlayer resin insulation layers to be built up can be reduced. In addition,
The electrode is formed with a conductive paste as in the first embodiment, or a conductive paste and a composite metal layer as in the first modification of the first embodiment.

The manufacturing process of the printed wiring board according to the second embodiment of the present invention will be described with reference to FIGS.

(1) A first resin substrate 30a in which a core material such as a glass cloth having a thickness of 0.1 mm is impregnated with a BT (bismaleimide triazine) resin and cured is prepared. The first resin substrate 30a has a conductive pad portion 34 formed on one surface and a conductive circuit 35 formed on the other surface. Next, a plurality of chip capacitors 20 are mounted on the conductive pad portions 34 via an adhesive material 36 such as solder or conductive paste, and the chip capacitors 20 are connected to the conductive pad portions 34 (FIG. 10).
(A)).

(2) Next, a prepreg (adhesive resin layer) 38 in which a core material such as glass cloth is impregnated with an epoxy resin.
a, 38b and a core material such as glass cloth impregnated with a BT resin and cured to form a second resin substrate 30b (0.4 m thick).
m), a third resin substrate 30c (0.1 mm thick) is prepared. In the prepreg 38a and the second resin substrate 30b, through holes 38A and 30B capable of accommodating the chip capacitor 20 are formed. Further, the conductor circuits 37 are formed on both surfaces of the second resin substrate 30b, and the conductor circuits 35 are formed on one surface of the third resin substrate 30c. First, the prepreg 38b is placed on the surface of the third resin substrate 30c where the conductor circuit 35 is not formed.
The second resin substrate 30b is placed via the. The first resin substrate 30a is inverted and placed on the second resin substrate 30b via the prepreg 38a. That is, the first resin substrate 30a
The chip capacitor 20 connected to the second resin substrate 30
b) so as to be accommodated in the opening 30B formed in the opening b (see FIG. 10B).

(3) Then, the first, second, and third resin substrates 30a, 30b, and 30c are integrated into a multi-layer by pressing the superposed substrates using a hot press. Core substrate 3 having chip capacitor 20
0 is formed (see FIG. 10C). First, an epoxy resin (insulating resin) is extruded from the prepregs 38a and 38b to the surroundings by being pressurized to fill a gap between the opening 30B and the chip capacitor 20. Further, the epoxy resin is cured by being heated at the same time as the pressurization, and the prepregs 38a and 38b are interposed as adhesive resins, so that the first resin substrate 30a, the second resin substrate 30b, and the third resin substrate 30c Is firmly adhered.

(4) A thermosetting resin film is vacuum-press-laminated on the substrate having undergone the above steps at a pressure of 5 kg / cm ² while raising the temperature to a temperature of 50 to 150 ° C. to provide an interlayer resin insulating layer 40 (FIG. 10). (D)). The degree of vacuum during vacuum compression is 10 mmHg.

(5) Next, on the upper and lower surfaces of the substrate 30, the conductor pad portions 34 and the conductor circuits 35,
A via hole opening 42 to be connected to 37 is formed (see FIG. 10E). Subsequent steps are the same as steps (7) to (19) in the first embodiment described above, and thus description thereof is omitted.

Next, the configuration of the printed wiring board according to the third embodiment of the present invention will be described with reference to FIG. The configuration of the printed wiring board of the third embodiment is substantially the same as that of the above-described first embodiment. However, the core substrate 3
The chip capacitors 20 housed to 0 are different. Figure 1
4 shows a plan view of the chip capacitor. FIG.
(A) shows a chip capacitor for multi-piece cutting before cutting, and a dashed line in the drawing shows a cutting line. In the printed wiring board of the first embodiment described above, the first electrode 21 and the second electrode 22 are provided on the side edges of the chip capacitor as shown in the plan view of FIG. FIG. 14 (C)
Represents a chip capacitor for multi-piece cutting according to the third embodiment before cutting, and a dashed line in the drawing indicates a cutting line. In the printed wiring board of the third embodiment, FIG.
As shown in the plan view, a first electrode 21 and a second electrode 22 are provided inside the side edge of the chip capacitor. In addition,
The electrode is formed with a conductive paste as in the first embodiment, or a conductive paste and a composite metal layer as in the first modification of the first embodiment.

In the printed wiring board according to the third embodiment,
Since the chip capacitor 20 having the electrode formed inside the outer edge is used, a large-capacity chip capacitor can be used.

Next, a printed wiring board according to a first modification of the third embodiment will be described with reference to FIG. FIG.
Shows a plan view of the chip capacitor 20 housed in the core substrate of the printed wiring board according to the first modification. In the above-described first embodiment, a plurality of small-capacity chip capacitors are housed in the core substrate. In the first modification, a large-capacity large-format chip capacitor 20 is housed in the core substrate. Here, the chip capacitor 20 is connected to the first electrode 21.
, The second electrode 22, the dielectric 23, the first conductive film 24 connected to the first electrode 21, the second conductive film 25 connected to the second electrode 22, the first conductive film 24 and the first conductive film 24. 2 conductive film 25
And the connection electrodes 27 on the upper and lower surfaces of the chip capacitor not connected to the chip capacitor. The IC chip side and the daughter board side are connected via the electrodes 27.

In the printed wiring board of the first modified example, since the large-sized chip capacitor 20 is used, a large-capacity chip capacitor can be used. Further, since the large chip capacitor 20 is used, the printed wiring board does not warp even if the heat cycle is repeated. Note that a conductive paste is formed on the electrode as in the first embodiment, or a conductive paste and a composite metal layer are formed as in the first modification of the first embodiment.

A printed wiring board according to a second modification will be described with reference to FIG. FIG. 16A shows a chip capacitor before cutting for multi-cavity production, in which a dashed line indicates a normal cutting line, and FIG. 16B shows a plan view of the chip capacitor. . As shown in FIG. 16B, in the second modification, a plurality of (three in the example in the figure) multi-chip chip capacitors are connected and used in a large format.

In the second modification, a large-sized chip capacitor 20 is used, so that a large-capacity chip capacitor can be used. Further, since the large chip capacitor 20 is used, the printed wiring board does not warp even if the heat cycle is repeated. In addition, as in the first embodiment, a conductive paste or
The conductive paste and the composite metal layer are formed as in the first modification of the first embodiment.

In the above-described third embodiment, the chip capacitor is built in the printed wiring board. However, instead of the chip capacitor, it is also possible to use a plate-like capacitor in which a conductor film is provided on a ceramic plate. .

[0102]

According to the manufacturing method of the present invention, the capacitor can be accommodated in the core substrate, and the distance between the IC chip and the capacitor is shortened, so that the loop inductance of the printed wiring board can be reduced. Further, since the resin substrate is laminated, sufficient strength can be obtained for the core substrate. Furthermore, since the first resin substrate and the third resin substrate are provided on both surfaces of the core substrate to make the core substrate smooth,
The interlayer resin insulating layer and the conductor circuit can be appropriately formed on the core substrate, and the defective product occurrence rate of the printed wiring board can be reduced. In addition, since the conductive paste is applied to the surface of the metallized electrode of the capacitor, the electrical connectivity of the metallized electrode having a high surface resistance can be improved. The metallized electrode has irregularities on the surface and cannot be completely adhered even if it is directly connected with a conductive adhesive.However, the irregularity can be eliminated by the conductive paste to improve the adhesion. , Connection resistance can be reduced. In addition, since the metallized electrode is in contact with the surrounding resin layer via the conductive paste, the generation of stress due to the difference in thermal expansion between the electrode and the resin layer is suppressed, and cracks and peeling of the resin layer are eliminated.
Also, even when the capacitor is covered with copper, the occurrence of migration can be prevented.

[Brief description of the drawings]

FIGS. 1A, 1B, 1C, and 1D are manufacturing process diagrams of a printed wiring board according to a first embodiment of the present invention.

FIGS. 2A, 2B, 2C, and 2D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.

FIGS. 3A, 3B, 3C, and 3D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.

FIGS. 4A, 4B, 4C, and 4D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.

FIGS. 5A, 5B, and 5C are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.

FIGS. 6A and 6B are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.

FIG. 7 is a sectional view of the printed wiring board according to the first embodiment of the present invention.

8 is a cross-sectional view showing a state where an IC chip is mounted on the printed wiring board in FIG. 7 and attached to a daughter board.

FIG. 9 is a cross-sectional view showing a state in which an IC chip is mounted on a printed wiring board according to a modification of the first embodiment of the present invention.

FIG. 10 (A), (B), (C), (D), (E)
FIG. 7 is a manufacturing process diagram of the printed wiring board according to the second embodiment of the present invention.

FIG. 11 is a sectional view of a printed wiring board according to a second embodiment of the present invention.

FIG. 12 is a graph showing changes in supply voltage to an IC chip and time.

FIG. 13A is a cross-sectional view of a chip capacitor according to the first embodiment, and FIG. 13B is a cross-sectional view of a chip capacitor according to a first modification of the first embodiment.

FIGS. 14A, 14B, 14C, and 14D are plan views of a chip capacitor of a printed wiring board according to a third embodiment.

FIG. 15 is a plan view of a chip capacitor of a printed wiring board according to a third embodiment.

FIG. 16 is a plan view of a chip capacitor of a printed wiring board according to a modification of the third embodiment.

[Explanation of symbols]

 Reference Signs List 20 chip capacitor 21 first electrode 22 second electrode 23 dielectric 23a roughened surface 23b polyimid film 26 conductive paste 28a electroless copper plating film 28b electrolytic copper plating film 28 composite metal film 30 core substrate 30a first resin substrate 30b first 2 resin substrate 30c third resin substrate 30B opening 34 conductive pad portion 35 conductive circuit 36 adhesive material 37 conductive circuit 38a, 38b bonding resin layer (bonding plate) 40 interlayer resin insulating layer 56 through hole 58 conductive circuit 60 via hole 70 solder Resist layer 71 Opening 72 Nickel plating layer 74 Gold plating layer 76U, 76D Solder bump 80A, 80B Build-up wiring layer 90 IC chip 92P1, 92P2 Solder pad (IC chip side) 94P1, 94P2 Solder pad (daughter board side) 95 Daughter board Lead 96 Conductive connection pin 140 Interlayer resin insulation layer 158 Conductor circuit 160 Via hole 240 Interlayer resin insulation layer 258 Conductor circuit 260 Via hole

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) 5E336 AA04 AA08 BB03 BB15 BC26 CC32 CC36 CC43 CC53 CC55 EE07 EE08 EE17 GG05 GG09 GG11 GG16 5E346 AA02 AA05 AA06 AA12 AA15 AA22 AA32 AA41 BB16 EE31 DD32 CC32 EE33 EE35 EE38 FF04 FF07 FF12 FF45 GG15 GG17 GG18 GG19 GG25 GG27 GG28 HH02 HH11

Claims (16)

[Claims] 1. A printed wiring board comprising an interlayer resin insulating layer and a conductor circuit alternately laminated on a core substrate containing a capacitor, wherein the core substrate containing the capacitor comprises a first resin substrate and a first resin substrate. A second resin substrate having an opening for accommodating a capacitor, and a third resin substrate are laminated with an adhesive plate interposed therebetween.
A printed wiring board to which a conductive paste is applied. 2. The printed wiring board according to claim 1, wherein a metal layer is provided on the conductive paste of the electrodes of the capacitor. 3. The printed wiring board according to claim 1, wherein the surface of the capacitor is subjected to a roughening treatment. 4. The printed wiring board according to claim 1, wherein the surface of the capacitor is subjected to a surface wettability improving treatment. 5. The printed wiring board according to claim 1, wherein the adhesive plate is formed by impregnating a core material with a thermosetting resin. 6. The printed wiring board according to claim 1, wherein the first, second, and third resin substrates are obtained by impregnating a core material with a resin. 7. The printed wiring board according to claim 1, wherein a plurality of the capacitors are provided. 8. The method for manufacturing a printed wiring board according to claim 1, wherein a conductive circuit is formed on the second resin substrate. 9. The printed circuit board according to claim 1, wherein a capacitor is mounted on a surface of the printed wiring board.
A printed wiring board according to claim 1. 10. The printed wiring board according to claim 9, wherein the capacitance of the chip capacitor on the front surface is equal to or larger than the capacitance of the chip capacitor in the inner layer. 11. The printed wiring board according to claim 9, wherein the inductance of the chip capacitor on the surface is equal to or greater than the inductance of the chip capacitor in the inner layer. 12. The method according to claim 1, wherein the first resin substrate and the capacitor are joined with an insulating adhesive, and the insulating adhesive has a smaller coefficient of thermal expansion than the first resin substrate. The printed wiring board according to claim 1. 13. The printed wiring board according to claim 1, wherein a chip capacitor having an electrode formed inside an outer edge is used as the capacitor. 14. The printed wiring board according to claim 1, wherein a chip capacitor having electrodes formed in a matrix is used as said capacitor. 15. The printed wiring board according to claim 1, wherein a plurality of chip capacitors for multi-cavity are connected and used as the capacitor. 16. A method of manufacturing a printed wiring board, comprising at least the following steps (a) to (d): (a) forming a conductive pad portion on a first resin substrate; (b) A) connecting a capacitor having a conductive paste applied onto a metallized electrode via a conductive adhesive to the conductive pad portion of the first resin substrate; (c) a third resin substrate and the capacitor A second resin substrate having an opening for accommodating the first resin substrate and the capacitor of the first resin substrate in the opening of the second resin substrate, and a third resin substrate. A step of laminating the resin substrate with an adhesive plate interposed therebetween so as to cover the opening of the second resin substrate; (d) the first resin substrate, the second resin substrate, and the third To heat and press the resin substrate of .