JP2002270710A - Semiconductor package and its drive device - Google Patents

Abstract

An object of the present invention is to reduce the wiring inductance of a power semiconductor element and a drive device, particularly at a connection portion. SOLUTION: A gate wiring substrate 2 has a gate electrode side wiring 4.
a, 4b or emitter electrode side wirings 5a, 5b in each layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor package in which a power semiconductor element is packaged and a drive device for the semiconductor package.

[0002]

2. Description of the Related Art In recent years, power semiconductor devices have been increased in capacity and speed. To increase the speed, it is necessary to drive a drive device connected to the power semiconductor element at a high speed. However, if an inductance exists between the drive device and the gate electrode of the power semiconductor element, high-speed driving cannot be performed. In addition, the loss of the power semiconductor element increases due to the inability to perform high-speed driving, the size of a cooler for cooling the power semiconductor element increases, and the cost of the power semiconductor element and the power converter to which the drive device is applied is reduced. Will rise. Heretofore, the connection between the gate electrode of the power semiconductor element and the drive device has been made by a lead wire or the like, but the gate electrode and the emitter electrode wiring in the semiconductor package are formed into a substrate in order to reduce the inductance. Hereinafter, such a conventional connection structure between a power semiconductor element and a drive device will be described with reference to FIGS.

FIG. 8 shows a conventional connection between a power semiconductor device and a drive device in a power converter. In the figure, a gate electrode side wiring 14 from a gate electrode and an emitter electrode side wiring 15 from an emitter electrode in a power semiconductor element 11 are connected to a drive device 13 via a gate side connection terminal 16 and an emitter side connection terminal 17, respectively. Have been.

FIG. 9 shows a conventional connection structure between a power semiconductor device and a drive device. In the figure, when the gate electrode side wiring 14 and the emitter electrode side wiring 15 on the gate wiring substrate 12 in the power semiconductor element 11 are arranged in front and back in parallel, the current flowing through the gate electrode side wiring 14 and the emitter Since the currents flowing through the electrode side wirings 15 cancel the magnetic fluxes in opposite directions, the wiring inductance hardly increases. However, since the wiring is made to the connection terminals 16 and 17, the wiring cannot be made in parallel at the connection part of the gate wiring substrate 12 on the front and back. At least the gate electrode side wiring 14 and the emitter electrode side wiring 15 have a structure separated by at least two widths of the connection terminals 16 and 17. Also, since the drive device 13 to be connected is also wired to the connection terminals 16 and 17, the gate electrode side wire 14 and the emitter electrode side wire 15 cannot be wired in parallel on the drive device 13 on the front and back. , 17 are separated from each other by two or more widths.

[0005]

Conventionally, the wiring inductance of the power semiconductor element and the drive device, especially at the connection portion, becomes large. If the wiring inductance is large, an overvoltage occurs in the power semiconductor element, which may lead to element destruction. In addition, the power semiconductor element cannot be driven at high speed, and the loss of the power semiconductor element increases. When the loss of the power semiconductor element increases, the size of a cooler for cooling the power semiconductor element increases, and the cost of the power converter incorporating the power semiconductor element and the drive device increases.

[0006] The present invention has been made in view of the above,
It is possible to reduce the wiring inductance of the power semiconductor element and the drive device, particularly at the connection portion, suppress the occurrence of overvoltage applied to the power semiconductor element, drive the power semiconductor element at high speed, and further reduce the power consumption. It is an object of the present invention to provide a semiconductor package capable of reducing the loss of a semiconductor element for use, reducing the size of its cooler, and reducing the cost of a power converter, and a drive device for the same.

[0007]

According to a first aspect of the present invention, there is provided a semiconductor package comprising a power semiconductor element, a gate electrode side wiring from the gate electrode and an emitter electrode in the power semiconductor element. And a gate wiring board provided with the emitter electrode side wiring of the above, wherein the gate wiring board has the gate electrode side wiring or the emitter electrode side wiring in each layer.
The point is that it consists of layers or more. With this configuration, when the gate electrode side wiring and the emitter electrode side wiring of each layer are arranged in parallel, the current flowing through the gate electrode side wiring and the current flowing through the emitter electrode side wiring cancel out magnetic flux in mutually opposite directions. The inductance can be reduced.

According to a second aspect of the present invention, there is provided a semiconductor package according to the first aspect, wherein the gate wiring substrate comprises four layers. With this configuration, the canceling action of the magnetic flux increases and the wiring inductance can be further reduced.

According to a third aspect of the present invention, in the semiconductor package according to the second aspect, the first layer wiring and the third layer wiring of the gate wiring substrate are connected in parallel, and the second layer wiring and the third layer wiring are connected to each other. The gist is that four layers of wiring are connected in parallel. With this configuration, the current flowing through the wiring of each layer is alternately reversed, so that the magnetic flux canceling action is increased and the wiring inductance is reduced.

The semiconductor package according to claim 4 is the semiconductor package according to claim 2 or 3, wherein
The gist is that the layer and the third layer are used as a gate electrode side wiring or an emitter electrode side wiring, and the second layer and the fourth layer are used as an emitter electrode side wiring or a gate electrode side wiring. With this configuration, the gate electrode side wiring and the emitter electrode side wiring are alternately arranged in each layer, and the current flowing through the wiring in each layer is alternately reversed, so that the wiring inductance is reduced.

According to a fifth aspect of the present invention, in the semiconductor package according to the first to fourth aspects, external connection terminals of the gate electrode side wiring and the emitter electrode side wiring are arranged adjacent to an end of the gate wiring substrate. The gist is to arrange them. With this configuration, the inductance at the connection portion with the drive device or the like is reduced.

The semiconductor package according to claim 6 is the semiconductor package according to claims 2 to 5, wherein
The gist is that the wiring width in the vicinity of the external connection terminal in the gate electrode side wiring and the emitter electrode side wiring in the layer and the third layer is made wider than the wiring width in the first layer and the fourth layer. With this configuration, by increasing the wiring width near the external connection terminal in the wiring of the second layer and the third layer having a small interval in the stacking direction, the magnetic flux is sufficiently canceled out, and the inductance at the connection with the drive device or the like is further increased. Reduce.

According to a seventh aspect of the present invention, in the semiconductor package according to any one of the second to sixth aspects, the external connection terminals in the gate electrode side wiring and the emitter electrode side wiring of the second and third layers are provided. The wiring width in the vicinity is to be a wiring width equal to or greater than the maximum distance in the wiring width direction including the wiring widths of the first and fourth layers at the wiring width direction wiring ends of the first and fourth layers. Make a summary. According to this configuration, the same operation as the semiconductor package according to the sixth aspect is obtained.

According to an eighth aspect of the present invention, in the semiconductor package according to any one of the second to seventh aspects, the first layer wiring and the fourth layer wiring of the gate electrode side wiring and the emitter electrode side wiring are connected to the first layer. The gist of the present invention is that two layers and a third layer are accommodated in each wiring width and four layers are stacked. With this configuration, the wiring between the first and second layers and the third
An effective magnetic flux canceling action occurs between the wirings of the layer and the fourth layer, and the wiring inductance is further reduced.

According to a ninth aspect of the present invention, there is provided a drive device according to the first aspect.
A drive device connected to the semiconductor package according to any one of claims 1 to 8, wherein a structure of a connection portion with the gate wiring substrate has a structure according to any one of claims 1 to 7. . With this configuration, the inductance of the connection portion on the drive device side connected to the semiconductor package is also reduced.

According to a tenth aspect of the present invention, in the drive device according to the ninth aspect, the drive device is incorporated in a power converter. With this configuration, by incorporating the power semiconductor device and the drive device with the reduced inductance of the connection part and the like into the power converter, it is possible to suppress the occurrence of overvoltage applied to the power semiconductor device, drive the power semiconductor device at high speed, and use the power semiconductor. A power conversion device is realized that has a small element loss and enables a cooler to be downsized.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 and FIG. 2 are views showing a first embodiment of the present invention. First, the configuration of the semiconductor package of the present embodiment will be described. In FIG. 1, a gate wiring substrate 2 provided with a gate electrode side wiring from a gate electrode and an emitter electrode side wiring from an emitter electrode in a power semiconductor element 1 It is a four-layer substrate, the first layer to
It is the fourth layer. The first layer is a gate electrode side wiring 4a,
The second layer is the emitter electrode side wiring 5a, the third layer is the gate electrode side wiring 4b, and the fourth layer is the emitter electrode side wiring 5b.
A second-layer emitter electrode-side wiring 5a and a third-layer gate electrode-side wiring 4b are arranged between the first-layer gate-electrode-side wiring 4a and the fourth-layer emitter-electrode-side wiring 5b. The electrode side wiring 5a and the third layer gate electrode side wiring 4b are connected to the fourth layer emitter electrode side wiring 5b and the first layer gate electrode side wiring 4a, respectively. Connections may be made at 6a-6b and 7a-7b which are conducted through holes. The second layer and the third layer in the connection portion with the drive device
The wiring width “A” of the layer has the same wiring width as the maximum distance “B” in the wiring width direction including the wiring widths of the first and fourth layers at the wiring end portions in the wiring width direction of the first and fourth layers. ing. Thereby, the first
The wiring of the layer and the fourth layer are arranged within the wiring width of both the second layer and the third layer, and the wiring of the four layers is stacked.
The substrate may be turned upside down.

FIG. 2 shows the gate electrode side wirings 4a and 4b and the emitter electrode side wiring 5 on the gate wiring substrate 2 of FIG.
It is an exploded view of a and 5b. The wiring width “A” of the second layer and the third layer is set to the first width at the wiring width direction wiring ends of the first layer and the fourth layer.
It is equal to the maximum distance "B" in the wiring width direction including the wiring width of the layer and the fourth layer.

Next, the operation of the present embodiment configured as described above will be described. When the gate electrode side wirings 4a and 4b and the emitter electrode side wirings 5a and 5b are arranged in parallel, the current flowing through the gate electrode side wiring and the current flowing through the emitter electrode side wiring cancel magnetic flux in opposite directions. In addition, the wiring inductance hardly increases. However, since the wires are connected to the connection terminals 6a, 6b and 7a, 7b, they cannot be wired in parallel on the front and back sides of the gate wiring board 2, and the current flowing through the gate electrode side wiring and the current flowing through the emitter electrode side wiring are opposite to each other. However, the magnetic flux cannot be canceled out and the wiring inductance increases. In order to obtain a connection structure that does not increase inductance, if the connection structure shown in FIG. 1 is used, the second-layer emitter electrode-side wiring 5a and the third-layer gate electrode-side wiring 4b are respectively connected to the first-layer gate electrode-side wiring 4a. The magnetic flux of the fourth-layer emitter electrode-side wiring 5b can be offset, the positive mutual inductance between the parallel layers can be reduced, and the reduction in inductance due to the parallelization can be sufficiently exhibited.

FIG. 3 shows a second embodiment of the present invention. FIG. 3 shows the gate electrode side wirings 4a and 4b and the emitter electrode side wiring 5 provided on the gate wiring substrate 2 of FIG.
a, 5b correspond to the sectional views. In the present embodiment, the wiring width “A” of the second and third layers is larger than the wiring width “C” of the first and fourth layers. First layer gate electrode side wiring 4
a and the fourth-layer emitter-electrode-side wiring 5b cannot sufficiently cancel the magnetic flux because the distance in the stacking direction is wide. Therefore, the magnetic flux is canceled by the second-layer emitter electrode-side wiring 5a and the third-layer gate electrode-side wiring 4b which are connected in parallel and have a small interval in the stacking direction. Further, the magnetic flux can be sufficiently canceled by increasing the wiring width of the second layer and the third layer.

FIG. 4 shows a third embodiment of the present invention. FIG. 4 shows the gate electrode side wirings 4a and 4b and the emitter electrode side wiring 5 provided on the gate wiring substrate 2 of FIG.
a, 5b correspond to the sectional views. In this embodiment, the wiring width “A” of the second layer and the third layer is set to the wiring width including the wiring width of the first layer and the fourth layer at the wiring width direction wiring ends of the first layer and the fourth layer. The distance is equal to or longer than the maximum distance “B” in the direction.

The first-layer gate electrode side wiring 4a and the fourth-layer emitter electrode side wiring 5b have a large space in the stacking direction and are not wired in parallel on the front and back sides, so that the magnetic flux cannot be sufficiently canceled. Therefore, the magnetic flux can be sufficiently canceled by increasing the wiring width of the second layer and the third layer, which are connected in parallel and have a small interval in the stacking direction, so that A ≧ B.

FIG. 5 shows a fourth embodiment of the present invention. FIG. 5 shows the gate electrode side wirings 4a and 4b and the emitter electrode side wiring 5 provided on the gate wiring substrate 2 of FIG.
a and 5b correspond to a cross-sectional view taken along line XX 'in FIG. In the present embodiment, the wiring width “C” of the first layer and the fourth layer is changed to the third layer and the third layer.
The layers are arranged within the wiring width “A” of both layers, and four layers are stacked.

The first-layer gate electrode side wiring 4a and the fourth-layer emitter electrode side wiring 5b have a large space in the stacking direction and are not wired in parallel on the front and back sides, so that the magnetic flux cannot be sufficiently offset. Therefore, the second-layer emitter electrode-side wiring 5a and the third-layer gate electrode-side wiring 4b, which are connected in parallel and have a small interval in the stacking direction, are arranged as shown in FIG.
Magnetic flux can also be canceled between the first and second layers and between the third and fourth layers.

FIG. 6 shows a fifth embodiment of the present invention. In the present embodiment, the power semiconductor element 1 and the drive device 3 are connected by setting the structure of the connection portion between the drive device 3 and the gate wiring substrate 2 to be the same as any of the above-described FIGS. . Thus, the inductance of the connection portion on the drive device 3 side connected to the semiconductor package is also reduced.

By incorporating the power semiconductor element 1 having the reduced inductance at the connection portion and the drive device 3 into a power converter, the generation of overvoltage applied to the power semiconductor element 1 is suppressed, and the power semiconductor element 1 It is possible to realize a power converter that can be driven at high speed and has a small loss of the power semiconductor element 1 and a small cooler.

FIG. 7 shows a result of analysis of the wiring inductance of the connection portion in each of the above-described embodiments. An improvement of 10% can be seen when the same wiring width is used for all four layers as compared with the case where the gate wiring substrate has two layers. 1 to 6
(Fourth and fifth embodiments), the inductance of the connection portion is halved. The wiring width of the second and third layers is made wider than the wiring width of the first and fourth layers, and the wiring of the first and fourth layers is
It can be seen that the inductance can be greatly reduced by arranging four layers and arranging them within the wiring width of both the layer and the third layer.

[0029]

As described above, according to the invention of the semiconductor package, the gate wiring substrate has two or more layers, for example, four layers.
Since the gate electrode side wiring and the emitter electrode side wiring are arranged alternately in each layer, the current flowing in the wiring of each layer is alternately reversed, the magnetic flux is canceled out, and the wiring inductance can be reduced. it can.

Further, the wiring width in the vicinity of the external connection terminal in each wiring of the second layer and the third layer is equal to or greater than the wiring width of the first layer and the fourth layer. The magnetic flux is sufficiently canceled between the wirings of the second layer and the third layer, so that the inductance at the connection with the drive device or the like can be sufficiently reduced.

According to the invention of the drive device, the structure of the connection portion with the gate wiring substrate is made similar to the structure of the semiconductor package side described above, so that the inductance of the connection portion can be reduced also on the drive device side. .

Further, by incorporating the drive device connected with the above-mentioned semiconductor package into a power converter, it is possible to suppress the occurrence of overvoltage applied to the power semiconductor device and to drive the power semiconductor device at high speed. It is possible to reduce the loss of the semiconductor element for use, to reduce the size of the cooler, and to reduce the cost of the power converter.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a structure of a connection portion of a gate wiring board in a semiconductor package according to a first embodiment of the present invention.

FIG. 2 is an exploded view of a gate electrode side wiring and an emitter electrode side wiring of a gate wiring substrate connection portion in FIG.

FIG. 3 is a sectional view of a gate electrode side wiring and an emitter electrode side wiring provided on a gate wiring substrate according to a second embodiment of the present invention.

FIG. 4 is a cross-sectional view of a gate electrode side wiring and an emitter electrode side wiring provided on a gate wiring substrate according to a third embodiment of the present invention.

FIG. 5 is a sectional view showing a fourth embodiment of the present invention;
It is a figure corresponding to a middle XX 'cross section.

FIG. 6 is a perspective view showing a structure of a connection portion between a gate wiring board and a drive device according to a fifth embodiment of the present invention.

FIG. 7 is a diagram showing a wiring inductance analysis result of a connection portion in each embodiment of the present invention.

FIG. 8 is a diagram showing a connection between a conventional power semiconductor element and a drive device in a power converter.

FIG. 9 is a perspective view showing a structure of a connection portion between a conventional gate wiring substrate and a drive device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Power semiconductor element 2 Gate wiring board 3 Drive device 4a First layer gate electrode side wiring 4b Third layer gate electrode side wiring 5a Second layer emitter electrode side wiring 5b Fourth layer emitter electrode side wiring 6a, 6b Gate side connection Terminal 7a, 7b Emitter side connection terminal

Claims (10)

[Claims] 1. A semiconductor package comprising: a power semiconductor element; and a gate wiring substrate provided with a gate electrode side wiring from a gate electrode and an emitter electrode side wiring from an emitter electrode in the power semiconductor element. A semiconductor package, wherein the gate wiring substrate comprises two or more layers each having the gate electrode side wiring or the emitter electrode side wiring in each layer. 2. The semiconductor package according to claim 1, wherein said gate wiring substrate comprises four layers. 3. The gate wiring substrate according to claim 1, wherein a first layer wiring and a third layer wiring are connected in parallel, and a second layer wiring and a fourth layer wiring are connected in parallel. The semiconductor package according to claim 2. 4. The semiconductor device according to claim 1, wherein the first and third layers are a gate electrode side wiring or an emitter electrode side wiring, and the second and fourth layers are an emitter electrode side wiring or a gate electrode side wiring. The semiconductor package according to claim 2. 5. The semiconductor package according to claim 1, wherein external connection terminals of said gate electrode side wiring and said emitter electrode side wiring are arranged adjacent to an end of said gate wiring substrate. . 6. A wiring width in the vicinity of the external connection terminal in the gate electrode side wiring and the emitter electrode side wiring of the second and third layers is made wider than the wiring width of the first and fourth layers. 6. The semiconductor package according to claim 2, wherein: 7. The wiring width near the external connection terminal in the gate electrode side wiring and the emitter electrode side wiring of the second layer and the third layer is set at the wiring width direction wiring end of the first layer and the fourth layer. 7. The semiconductor package according to claim 2, wherein the wiring width is equal to or more than a maximum distance in a wiring width direction including the wiring widths of the first and fourth layers. 8. The wiring of the first layer and the fourth layer of the gate electrode side wiring and the emitter electrode side wiring are arranged within the respective wiring widths of the second layer and the third layer, and four layers are laminated. The semiconductor package according to claim 2, wherein: 9. A drive device connected to the semiconductor package according to claim 1, wherein a structure of a connection portion with the gate wiring substrate is configured as described in claim 1. A drive device having a structure. 10. The drive device according to claim 9, wherein the drive device is incorporated in a power conversion device.