JP2002268611A - Counter potential generation circuit, flat display device, and method of driving flat display device - Google Patents

Abstract

(57) Abstract: In a counter potential generating circuit for supplying a counter potential to a flat display device, power consumption for generating a counter potential to be supplied to a counter electrode in a standby state for displaying a still image is reduced. . SOLUTION: In a first display period (normal display state),
When the switches SW1 and SW2 are turned on by the switch control circuit 7, the power supply voltage VDD is supplied to the voltage dividing circuit 6, and the setting voltage of the divided common potential is input to the output amplifying circuit 1 so as to be opposed. A potential is generated, and in the second display period (still image display state), the switches SW1 and SW2 are turned off by the switch control circuit 7 so that no current is supplied to the voltage dividing circuit 6 from the power supply voltage VDD. The counter potential is generated by inputting the set voltage of the counter potential stored in the capacitor C to the output amplifier circuit 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a counter potential generating circuit and a flat panel display having the same, and more particularly to a driving circuit technique for reducing the power consumption of a portable information terminal.

[0002]

2. Description of the Related Art In recent years, among flat display devices, TFTs have been widely used.
Active-matrix liquid crystal display devices using (thin film transistors) are actively used as display elements for televisions, portable information devices, graphic displays, and the like, taking advantage of features such as light weight, thinness, and low power consumption. Recently, it has become possible to form a polysilicon TFT by a relatively low-temperature process, which has a higher electron mobility than conventional amorphous silicon and a complementary transistor (CMOS transistor) by introducing an impurity doping process. Due to the possibility of formation, a TFT type liquid crystal display device in which a drive circuit is integrally formed on a glass substrate has appeared.

Further, by utilizing the fact that a CMOS circuit can be formed, a TFT in which a so-called SRAM is formed, which can statically hold display data (liquid crystal application voltage) in one pixel.
Liquid crystal display (hereinafter referred to as SRAM built-in liquid crystal display)
Has also been developed. In such a liquid crystal display device with a built-in SRAM, the driver circuit and the system circuit are set in a standby state during a still image display (standby display state), and an image is displayed using display data held in the SRAM, thereby reducing power consumption. Can be reduced. Therefore, when such a liquid crystal display device with a built-in SRAM is mounted as a display of a portable information device driven by a battery, it is possible to contribute to a reduction in power consumption.

Incidentally, the above-described liquid crystal display device with a built-in SRAM includes a counter potential generating circuit for supplying a predetermined counter potential to the counter electrode. FIG. 4 is a circuit configuration diagram of a conventional general counter potential generation circuit.

In FIG. 4, a power supply voltage VDD is a resistor R
1. After being divided by a voltage dividing circuit 6 composed of a variable resistor VR and a resistor R2, the voltage is adjusted by the variable resistor VR to become a set voltage of the opposite potential. The set voltage of the opposite potential is stabilized by the capacitor C, and is further input to the output amplifier circuit 1. The output amplifier circuit 1 creates a counter potential corresponding to the input set voltage from the power supply voltage VDD, and outputs this to the counter electrode 2. A liquid crystal layer 4 is sandwiched between the counter electrode 2 and the pixel electrode 3, and the potential difference between the display data potential applied to the pixel electrode 3 via the TFT 5 and the counter potential applied to the counter electrode 2. , The liquid crystal layer 4 is driven.

The counter potential generating circuit 11 is a power IC
10 and includes a circuit in the power supply IC 10, an external voltage dividing circuit 6 and a capacitor C.

[0007]

In the counter potential generating circuit 11 as described above, current flows from VDD to the voltage dividing circuit 6 and the like even when the SRAM built-in type liquid crystal display device displays a still image. There was no reduction in power consumption in this area. For this reason, the conventional counter potential generating circuit has a problem that constant power is always consumed regardless of the normal display state or the standby display state.

An object of the present invention is to provide a counter potential generating circuit, a flat display device, and a driving method of a flat display device which can reduce power consumption for generating a counter potential in a standby state for displaying a still image. Is to do.

[0009]

In order to achieve the above object, the present invention is directed to a voltage dividing circuit for dividing a power supply voltage to generate a set voltage of an opposite potential, and a power supply for the voltage dividing circuit. A first switch for switching between supply and stop of a current from a voltage, potential holding means for holding a set voltage of a counter potential generated by the voltage dividing circuit, and an opposing voltage generated by the voltage dividing circuit to the potential holding means. A second switch for switching between supply and stop of current from a set voltage of the potential, an output amplifier circuit for outputting a counter potential corresponding to the set voltage, and a switch for controlling on / off of the first and second switches And a control circuit.

In a preferred embodiment, the voltage dividing circuit is configured to generate the set voltage of the common potential by dividing the power supply voltage by resistance.

In a preferred embodiment, the potential holding means is constituted by a capacitor.

According to a second aspect of the present invention, at least a plurality of scanning lines and a plurality of signal lines which are arranged to cross each other, a pixel electrode which is arranged at each intersection of these two lines, and a supply to the scanning lines are provided. On / off control is performed by a scanning signal to be applied, and when the signal line is turned on, the signal line is connected to the pixel electrode to write the display data supplied to the signal line to the pixel electrode. An internal memory capable of holding the supplied display data, a first switch including a second switch unit inserted between the pixel electrode and the internal memory and controlling conduction between the pixel electrode and the internal memory; Electrode substrate, a second electrode substrate including a counter electrode disposed at a predetermined distance from the first electrode substrate, and a second electrode substrate sandwiched between the first electrode substrate and the second electrode substrate. A display layer and the pair As a circuit for supplying a counter potential to the electrodes, a flat display device, characterized in that it comprises a counter potential generation circuit of claim 1.

In a preferred embodiment, the internal memory is
It is composed of a digital memory such as an SRAM.

In a preferred embodiment, the flat display device is an active matrix type liquid crystal display device using thin film transistors.

According to a third aspect of the present invention, there is provided the driving method of the flat panel display device according to the second aspect, wherein the second display is driven during the first display period.
By turning off the continuity between the pixel electrode and the internal memory by the switch unit, and turning on the first switch unit at a predetermined cycle, the display data supplied to the signal line is written to the pixel electrode. Display is performed, and in a second display period, the second switch unit is turned on, display data supplied to the signal line is held in the internal memory, and then the signal line is turned on by the first switch unit. And turning off the conduction between the pixel electrodes and writing the display data held in the internal memory to the pixel electrodes to perform display. In the first display period, the counter potential generation circuit includes The first and second switches are turned on to supply a common potential corresponding to the set voltage generated by the voltage dividing circuit to the common electrode. In the second display period, the common potential of the common potential generating circuit is 1, turns off the second switch, and supplying a counter potential which corresponds to the setting voltage held in the voltage holding means to said counter electrode.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit configuration diagram of a counter potential generation circuit according to the present embodiment. However, the same parts as those in FIG.

The counter potential generating circuit 12 includes an output amplifier circuit 1 for outputting a counter potential, a resistor R1, a variable resistor VR, and a resistor R.
2, a voltage dividing circuit 6 for dividing the power supply voltage VDD to generate a set voltage of the opposite potential, and a potential holding means having a function of stabilizing the set voltage and a function of discharging the accumulated set voltage. A switch SW1 as a first switch for turning on and off the supply of the power supply voltage VDD to the capacitor C and the voltage dividing circuit 6, and a switch as a second switch for turning on and off the output divided voltage from the voltage dividing circuit 6. Switch SW
2. An SW (switch) control circuit 7 for generating a control signal for turning on and off the switches SW1 and SW2. The counter potential generation circuit 12 of the present embodiment is also one of the circuits included in the power supply IC 10,
The power supply IC 10 includes the above circuits, an external voltage dividing circuit 6 and a capacitor C.

Next, a method of driving the counter potential generating circuit 12 configured as described above will be described.

In the normal display state (first display period), the switches SW1 and SW2 are turned on by the switch control circuit 7. Therefore, the power supply voltage VDD is equal to the resistance R
1, a voltage dividing circuit 6 of a variable resistor VR and a resistor R2, and the divided voltage is adjusted by the variable resistor VR.
It becomes the set voltage of the opposing potential. After this set voltage is stabilized by the capacitor C, it is further input to the output amplifier circuit 1. The output amplifying circuit 1 creates a counter potential corresponding to the input set voltage from the power supply voltage VDD,
Output to A liquid crystal layer 4 as a display layer is sandwiched between the counter electrode 2 and the pixel electrode 3, and the potential of the display data applied to the pixel electrode 3 via the TFT 5 and the counter potential applied to the counter electrode 2 The liquid crystal layer 4 is driven according to the potential difference between the liquid crystal layer and the liquid crystal layer.

In the still image display state (second display period),
The switches SW1 and SW2 are controlled to be turned off by the switch control circuit 7. As a result, no current is supplied to the voltage dividing circuit 6 from the power supply voltage VDD, and the set voltage of the opposite potential stored in the capacitor C is supplied to the input of the output amplifier circuit 1.

In the case of the still image display state from the beginning of the power-on, the switch control circuit 7 temporarily switches the switches SW1, S1.
After turning on W2 and accumulating charge in the capacitor C,
By performing control to turn off the switches SW1 and SW2, the set voltage of the opposite potential is supplied from the capacitor C to the input of the output amplifier circuit 1. Here, the switch control circuit 7
Receives the switching signal of the normal display mode / still image display mode from a control IC (not shown) that controls the operation of the entire apparatus, and performs the ON / OFF control of the switches SW1 and SW2 as described above.

Next, an SRAM built-in type liquid crystal display device provided with the counter potential generating circuit 12 shown in FIG. 1 will be described.

FIG. 2 is a circuit diagram showing the configuration of an S
FIG. 2 is a circuit configuration diagram of a liquid crystal display device with a built-in RAM (hereinafter, a liquid crystal display device). FIG. 3 is a schematic sectional view of FIG.
2 and 3, the same parts as those in FIG.

As shown in FIG. 2, the liquid crystal display device 100
Is a display pixel unit 110 in which a plurality of display pixels 13 are formed.
And a scanning line driving circuit 120 and a signal line driving circuit 130 for driving the display pixel section 110.

First, the display pixel section 110 will be described. A plurality of signal lines 8 and a plurality of scanning lines 9 are provided on an array substrate 101 (see FIG. 3) as a first electrode substrate.
The wires are intersected with each other via an insulating film (not shown). Further, a memory control signal line 14 is arranged in parallel with each scanning line 9.

A display pixel 13 is formed at each intersection of the signal line 8 and the scanning line 9. One end of each signal line 8 is connected to a signal line driving circuit 130, and one end of each scanning line 9 and each memory control signal line 14 is connected to a scanning line driving circuit 1.
20.

The display pixel 13 includes a pixel electrode 3, a first switch section (corresponding to the TFT in FIG. 1) 5, a counter electrode 2, a liquid crystal layer 4, a second switch section 15, and an S as an internal memory.
It is constituted by a RAM 16.

The source of the first switch section 5 is a signal line 8
The gate is connected to the scanning line 9 and the drain is connected to the pixel electrode 3. Further, the pixel electrode 3 is connected to the SRAM 16 via the second switch unit 15. The gate of the second switch unit 15 is connected to the memory control signal line 14, the source is connected to the pixel electrode 3, and the drain is connected to the SRAM 16. The first switch unit 5 and the second switch unit 15
Are both composed of MOS transistors.

As shown in FIG. 3, a pixel electrode 3 is formed on an array substrate 101, and a counter electrode 2 facing the pixel electrode 3 is formed on a counter substrate 102 as a second electrode substrate. The counter electrode 2 is supplied with a predetermined counter potential from a counter potential generation circuit (12) included in a power supply IC (not shown). A liquid crystal layer 4 as a display layer is filled between the pixel electrode 3 and the counter electrode 2, and the
The periphery of the counter substrate 102 is sealed with a sealing material 103.

Next, the scanning line driving circuit 120 and the signal line driving circuit 130 will be described. Scan line drive circuit 120
Is composed of a shift register 121 and a buffer circuit (not shown), outputs a scanning signal based on a control signal (vertical clock / start signal) supplied from a control IC (not shown), and changes the potential of the scanning line 9. On level or off level.

Further, the scanning line driving circuit 120 outputs a memory control signal at a predetermined timing, and simultaneously sets the potentials of all the memory control signal lines 14 to the on level or the off level. Specifically, in the normal display state, the potentials of all the memory control signal lines 14 are simultaneously turned off, and in the standby display state, the potentials of all the memory control signal lines 14 are simultaneously turned on. In the standby display state, all the scanning lines 9 are turned off. The memory control signal may be supplied not from the scanning line driving circuit 120 but from a control IC (not shown).

The signal line driving circuit 130 includes a shift register 131, an analog switch 132 and the like. This circuit is supplied with a control signal (horizontal clock / start signal) from a control IC (not shown) and with display data via a video bus 133. The signal line drive circuit 130 supplies the open / close signal of the analog switch 132 from the shift register 131 based on the horizontal clock / start signal, so that the display data supplied to the video bus 133 is transmitted at a predetermined timing to the signal line 8. Sampling.

In the liquid crystal display device 100 of this embodiment, the scanning line driving circuit 120 and the signal line driving circuit 130
Are formed integrally with the signal lines 8, the scanning lines 9, the pixel electrodes 3, and the like on the array substrate 101. However, the scanning line driving circuit 120 and the signal line driving circuit 130 may be arranged on an external circuit board on which a control IC (not shown) is arranged.

Next, the operation of the liquid crystal display device 100 configured as described above in the normal display state and the standby display state will be described.

In the normal display state, the scanning line driving circuit 120
, The on-level scanning signals are sequentially output from each scanning line 9.
Is turned on only for one horizontal scanning period. During this period, display data sampled on the signal line 8 from the signal line driving circuit 130 is written to the pixel electrode 3 through the first switch unit 5. The display data is charged between the pixel electrode 3 and the counter electrode 2 as a signal voltage, and the liquid crystal layer 4 is charged according to the magnitude of the signal voltage.
Responds, the amount of transmitted light from the display pixel 13 is controlled. By repeating such a writing operation for one or several frames, a display image for one screen is completed. During this time, since the potentials of all the memory control signal lines 14 are controlled to the off level, the second switch unit 15 is turned off, and the function of the SRAM 16 is stopped. In the counter potential generation circuit 12 (FIG. 1), a control IC (not shown)
The switch control circuit 7 controls the switches SW1 and SW2 to be turned on. As a result, the set voltage of the common potential divided and adjusted by the voltage dividing circuit 6 is input to the output amplifier circuit 1, where the common potential corresponding to the set voltage is created and supplied to the common electrode 2.

On the other hand, in the still image display state, the supply of control signals and the like to the scanning line drive circuit 120 and the signal line drive circuit 130 is stopped, and these drive circuits are put into a standby state. During this time, the potentials of all the memory control signal lines 14 are controlled to the on level, so that the second switch unit 15 is turned on, the display data held in the SRAM 16 is applied to the pixel electrodes 3, and the Display is performed. In the counter potential generation circuit 12, a switch signal for switching to the still image display mode is given from a control IC (not shown), and the switches SW1 and SW2
Is controlled off. As a result, no current is supplied to the voltage dividing circuit 6 from the power supply voltage VDD, and the set voltage of the common potential stored in the capacitor C is output from the output amplifying circuit 1.
, Where an opposing potential corresponding to the set voltage is created and supplied to the opposing electrode 2.

According to the counter potential generating circuit 12 of the present embodiment, at the time of displaying a still image, the current flowing from the power supply voltage VDD to the GND through the voltage dividing circuit 6 is cut off, and the counter potential is set from the capacitor C. Since the opposite potential is maintained by supplying a voltage to the input of the output amplifier circuit 1, power consumption during still image display can be reduced. Therefore, when the liquid crystal display device 100 in which the counter potential generation circuit 12 is incorporated in a power supply IC is mounted as a display of a portable information device or the like, the battery life can be extended.

[0038]

As described above, according to the present invention,
In a standby state in which a still image is displayed, the current flowing from the power supply voltage VDD to the voltage dividing circuit is cut off, and instead, a counter voltage is supplied from a capacitor to the output amplifier circuit to supply the counter potential. Therefore, power consumption for generating the opposite potential can be reduced during the standby state period for displaying a still image.

Therefore, when the present invention is applied to a display of a portable information device, the power consumed by the entire device can be further reduced.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a counter potential generation circuit according to an embodiment.

FIG. 2 is a circuit configuration diagram of an SRAM built-in type liquid crystal display device provided with a counter potential generation circuit.

FIG. 3 is a schematic sectional view of FIG. 2;

FIG. 4 is a circuit configuration diagram of a conventional general counter potential generation circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Output amplification circuit, 2 ... Counter electrode, 3 ... Pixel electrode, 4 ...
Liquid crystal layer, 5: first switch section (TFT), 6: voltage dividing circuit, 7: SW (switch) control circuit, 10: power supply IC,
11, 12 ... counter potential generating circuit, 13 ... display pixel, 14
... memory control signal line, 15 ... second switch section, 16 ...
SRAM, C: capacitor, R1, R2: resistor, SW
1, SW2: switch, VR: variable resistor

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H093 NC01 NC03 NC09 NC11 NC21 NC22 ND39 5C006 AA16 AC11 AF42 BB16 BC06 FA47 5C080 AA10 BB05 DD26 EE29 FF11 JJ02 JJ03 JJ06

Claims (3)

[Claims] 1. A voltage dividing circuit for dividing a power supply voltage to generate a setting voltage of a counter potential, a first switch for switching supply and stop of a current from the power supply voltage to the voltage dividing circuit, A potential holding means for holding a setting voltage of an opposing potential generated in the voltage dividing circuit; and a second switch for switching supply and stop of a current from the setting voltage of the opposing potential generated in the voltage dividing circuit to the potential holding means. An output amplifying circuit that outputs an opposing potential corresponding to the set voltage; and a switch control circuit that controls on and off of the first and second switches. 2. At least a plurality of scanning lines and a plurality of signal lines arranged intersecting each other, a pixel electrode arranged at each intersection of these two lines, and a scanning signal supplied to the scanning lines to turn on / off. A first switch unit that is turned off and conducts between the signal line and the pixel electrode at the time of on to write display data supplied to the signal line to the pixel electrode, and holds display data supplied to the signal line; A possible internal memory, inserted between the pixel electrode and the internal memory;
A first electrode substrate including a second switch unit that controls conduction between the pixel electrode and the internal memory; and a second electrode including a counter electrode disposed to face the first electrode substrate at a predetermined interval. Electrode substrate, the first electrode substrate and the second
2. A flat display device comprising: a display layer sandwiched between the first electrode substrate and the second electrode substrate; and a counter potential generation circuit according to claim 1 as a circuit for supplying a counter potential to the counter electrode. 3. In the first display period, the conduction between the pixel electrode and the internal memory is turned off by the second switch unit, and the first switch unit is turned on at a predetermined cycle, and The display is performed by writing the display data supplied to the line to the pixel electrode. In a second display period, the second switch unit is turned on,
After the display data supplied to the signal line is held in the internal memory, the conduction between the signal line and the pixel electrode is turned off by the first switch unit, and the display data held in the internal memory is turned off. Is written to the pixel electrode to perform display, and in the first display period, the first and second switches of the common potential generation circuit are turned on, Supplying a counter potential corresponding to a set voltage generated by the voltage dividing circuit to the counter electrode; and, in the second display period, turning off the first and second switches of the counter potential generating circuit, A method for driving a flat display device, comprising: supplying a counter potential corresponding to a set voltage held by a potential holding means to the counter electrode.