JP2002261291A - Thin film wiring structure, thin film transistor and method of manufacturing the same - Google Patents

Abstract

(57) [Problem] To provide a thin film wiring structure capable of reducing the specific resistance after heat treatment in a vacuum to 5 μΩcm or less and constructing a process with good yield. SOLUTION: A first conductive film 2 made of Ta or tantalum nitride sequentially formed on a substrate 1, a second conductive film 3 made of Al metal, and a third conductive film 3 made of Ta or tantalum nitride are formed.
And a fourth conductive film 5 made of Ti or titanium nitride, and the first, third, and fourth conductive films each have a thickness of 10 % Or less.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film wiring structure, various devices using the same, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a known active matrix type liquid crystal display device has a plurality of scanning signal lines and image signal lines crossing each other arranged in a matrix on an insulating substrate made of glass or the like. A thin film transistor (hereinafter, referred to as “TFT”) is arranged and formed at each intersection of the line and the image signal line.
An active matrix panel is constructed by arranging a pixel electrode and a liquid crystal element corresponding to each of the TFTs, and the TFT is switched to drive the corresponding liquid crystal element to perform a required image display on the active matrix panel. In recent years, it is expected to be a flat panel display with high display quality.

As shown in FIG. 9, the active matrix type liquid crystal display device includes a wiring line including a scanning line 102B and a data line 107B, and a pixel is provided near each intersection of the scanning line 102B and the data line 107B. Some include an electrode 110 and a TFT as a switching element. In this case, the gate electrode 102 of the TFT is connected to the scanning line 102B, the source electrode 107 is connected to the data line 107B, and the drain electrode 108 is connected to the pixel electrode 110.

FIG. 10 is a cross-sectional view of a portion around the TFT in FIG. A scanning line 102B including a gate electrode 102 is formed at a predetermined position on the upper surface of the glass substrate 101, and an anodic oxide film 102A is formed on the surface thereof.
A gate insulating film 103 is formed on the entire upper surface. A semiconductor thin film 104 made of amorphous silicon is formed in a portion corresponding to the gate electrode 102 at a predetermined location on the upper surface of the gate insulating film 103. Semiconductor thin film 1
The blocking layer 105 is formed at the center of the upper surface of the substrate 04. Semiconductor thin film 104 and blocking layer 105
Ohmic contact layers 106 made of n ⁺ silicon are formed on both sides of the upper surface of the substrate. On each upper surface of the ohmic contact layer 106, a drain electrode 108 and a source electrode 107 are formed. In addition, these electrodes 10
A data line 107B (not shown) is formed at the same time when the data lines 7 and 108 are formed.

A pixel electrode 110 is formed at a predetermined position on the upper surface of the gate insulating film 103 so as to be connected to the drain electrode 108. Further, a passivation film 109 is formed on the entire upper surface of the pixel electrode 110 except for a predetermined portion.

In recent years, liquid crystal display devices to which TFTs are applied have been increasing in size and definition. Therefore, an increase in wiring resistance has become a problem.

The use of a material having a low specific resistance, for example, Al as a wiring material has been studied, but Al has a problem that hillocks are generated on the surface when heated to several hundred degrees centigrade. For this reason, hillocks are generated on the surface of the gate electrode 102 when the insulating film 103 and the like are formed after the gate electrode 102 is formed, and the gate electrode 102 is affected by the hillocks.
And the source electrode 107 are short-circuited.

As a countermeasure, it is known that an Al alloy containing a refractory metal such as Ti is used as a material of a wiring composed of scanning lines including the gate electrode 102 (for example, Japanese Patent Application Laid-Open No. 4-130776). Gazette). In this case, Al contains a high melting point metal such as Ti because A
This is because the heat resistance of the single substance is not sufficient, and hillocks are prevented from being generated in a subsequent heating step. As described above, it is necessary to consider the hillock resistance, for example, in the process of forming the gate insulating film 103 formed on the scan line including the gate electrode 102, in the process of forming the gate insulating film 103 so that the withstand voltage does not decrease. Is required to be high temperature.

Further, Japanese Patent Application Laid-Open No. Hei 10-284493 describes the Ti content of an Al—Ti alloy thin film, the resistivity depending on the heat treatment temperature, and the hillock resistance. In all the Al—Ti alloy thin films, the resistivity increases as the Ti content increases. Also, the higher the heat treatment temperature, the higher the specific resistance after the heat treatment.

Further, when the heat treatment temperature is, for example, 250 ° C., the generation of hillocks is suppressed when the Ti content is 3 at% or more. Therefore, considering the hillock resistance, when the heat treatment temperature is 250 ° C., the Ti content is 3a.
It is desirable to set it to t% or more. However, when the Ti content is 3 at% or more, the resistivity becomes about 18 μΩcm or more.

In other words, in consideration of the hillock resistance, it is not preferable to set the Ti content to 3 at% or less, and hence the resistivity of the wiring (the scan line 102B including the gate electrode 102) to about 18 μΩcm or less. Can not do.

On the other hand, recently, as the definition of liquid crystal display devices, the aperture ratio, and the size of liquid crystal display devices have been increased, further reduction in the resistance of wiring has been required. There is a demand for a wiring configuration having a resistance of 5 μΩcm or less.

It is disclosed in Japanese Patent Application Laid-Open No. Hei 7-16 that a laminate of Al and Ti (Ti / Al / Ti, Ti / Al), instead of an Al-Ti alloy, is used to reduce the resistance of the wiring and improve the hillock resistance.
9967.

Here, a brief description will be given of the result of the present inventors' investigation on the specific resistance and the hillock resistance of the Ti / Al / Ti laminated structure.

The total film thickness of the Ti / Al / Ti structure is 300 n
m, and the upper and lower Ti film thicknesses are 5, 10, 15, 20, 30
heat treatment in vacuum at 450 ° C for 1 hour,
Specific resistance measurement and surface property observation were performed. Table 1 shows the change in specific resistance due to the heat treatment.

[0016]

[Table 1]

In the Ti / Al / Ti laminated structure, the specific resistance after the heat treatment becomes 5 μΩcm or more when the Ti film thickness is 10 nm or more, and the Ti film thickness is 10 nm or more in order to exhibit the hillock resistance from the result of surface observation. Turned out necessary. Therefore, it is not possible to meet the requirements for both low resistance and hillock resistance.

Japanese Patent No. 2820064 discloses that Ti
A gate electrode configuration of a / Al-Ta alloy / Al configuration has been proposed. Further, in the embodiment of the patent, a pure Al film thickness of 100 to
500 nm, Al-Ta alloy film thickness 50-250 nm, C
The description is made on the assumption that the film thickness of r (corresponding to Ti) is 100 to 200 nm.

In the above electrode configuration, the lamination film thickness is 500
nm or less, the Al-Ta alloy film thickness 50 nm, T
When the i-film thickness is 100 nm (defined so that the low-resistance pure Al film is maximized), the Al film thickness becomes 350 nm. The present inventors perform a heat treatment at 450 ° C. for 1 hour in a vacuum in this configuration to obtain a specific resistance. A measurement was made. As a result, the specific resistance is 5 μΩ
cm or more.

That is, in the structure disclosed in the embodiment of Japanese Patent No. 2820064, the low-resistance pure Al film has a relatively small thickness relative to the thickness of the laminated film. No. In particular, the specific resistance of the Al—Ta alloy itself is several times larger than that of Al, and it is necessary to reduce the film thickness in order to reduce the specific resistance as a laminated film.
In order to prevent the diffusion of i, an Al-Ta alloy film thickness of 50 nm or more is required as proposed in this patent. As described above, in order to realize a low-resistance wiring structure with a laminated film thickness of 500 nm or less, how to prevent Ti from diffusing into Al with a thin film is a major problem.

When Ta (approximately 13 μΩcm) having a lower specific resistance than Ti is used in place of Ti (approximately 43 μΩcm), when the gate insulating film (SiN _x ) 103 is processed in the TFT process, As described later, in the etching step, there is a problem that a selectivity of an etching rate (an etching rate of a gate insulating film / an etching rate of Ta) cannot be made large.
When the Ta film thickness as the Cap material is as thin as 30 nm or less, the selectivity is 20:
About 1 is required.

Usually, the etching in the TFT manufacturing process is R
It is performed by dry etching by IE (reactive ion etching). Usually, a fluorine-based gas and a chlorine-based gas are used for this etching. When a fluorine-based gas is used, oxygen gas O ₂ is generally added for the purpose of increasing F radicals that contribute to the etching (dry process application technology). See Nikkan Kogyo Shimbun, Kobayashi, Okada and Hosokawa).

When CF ₄ + O ₂ or SF ₆ + O ₂ is used as an etching gas, Ti is hardly etched, but the etching rate of Ta is high. This is
This is because the vapor pressure of Ta fluoride is higher than the vapor pressure of Ti fluoride.

Therefore, if a fluorine-based gas is used for Ta, the selectivity ER (SiN _x ): ER (TIN _x ) of the etching rate of Ta and SiN _x used as the gate insulating film
a) is about 2: 1 and does not satisfy the target specification of 20: 1.

In the etching using a chlorine-based gas, the etching rate of SiN _x is slower than the etching rate of Ta, and the selectivity ER (SiN _x ): ER (Ta)
Is about 1: 4. Therefore, there is a problem that the specification of the selectivity of 20: 1 cannot be achieved even when etching with a chlorine-based gas.

[0026]

As described above, Al-
In the case of a wiring made of a Ti alloy thin film, considering the hillock resistance, it is not preferable to set the Ti content to 3 at% or less, and there is a problem that the resistivity cannot be reduced to about 5 μΩcm or less.

On the other hand, Ti / Al having a laminated electrode wiring structure
The / Ti configuration has a problem that the hillock resistance is improved by setting the Ti film thickness to 10 nm or more, but the specific resistance after heat treatment in vacuum cannot be reduced to 5 μΩcm or less.

The Ti / Al-Ta alloy / Al structure cannot have a specific resistance of less than 5 μΩcm after heat treatment in vacuum. That is, Al-T which is a layer for preventing diffusion of Ti into Al
The alloy a has a problem that Ti diffuses into Al greatly and the specific resistance increases.

Further, it has been confirmed that the Ta / Al / Ta and Ta / Al structures achieve a specific resistance of 5 μΩcm or less after heat treatment in a vacuum. However, an insulating film (SiN _x film) is required in the process of forming a TFT. There is a problem that a selective ratio of the etching rate to the etching rate cannot be obtained.

The main object of the present invention is to make it possible to reduce the specific resistance after heat treatment in vacuum to 5 μΩcm or less, to suppress the occurrence of hillocks and pinholes, and to make the insulating film (SiN An object of the present invention is to provide a thin film wiring structure, a thin film transistor, and a method for manufacturing the same, which can increase the selectivity with respect to _X ), obtain a process margin, and build a process with a high yield.

[0031]

The configuration of the present invention which has been achieved to achieve the above object is as follows.

That is, the first aspect of the present invention is a thin film wiring structure formed on a substrate by lamination, wherein a first conductive film, a second conductive film, and a third conductive film are sequentially formed on the substrate. A film and a fourth conductive film, wherein the first conductive film is made of Ta or tantalum nitride, and the second conductive film is
The third conductive film is made of Ta or tantalum nitride, and the fourth conductive film is made of Al.
A thin film made of Ti or titanium nitride, wherein the thickness of each of the first, third and fourth conductive films is 10% or less of the thickness of the second conductive film. In the wiring structure.

Further, the second invention is a thin film wiring structure formed by lamination on a substrate, wherein a first conductive film, a second conductive film, and a third conductive film are sequentially formed on the substrate. A conductive film, wherein the first conductive film is made of Al,
The second conductive film is made of Ta or tantalum nitride, the third conductive film is made of Ti or titanium nitride, and the thickness of each of the second and third conductive films is In the thin film wiring structure, the thickness of the first conductive film is 10% or less.

In the first and second aspects of the present invention, the total thickness of the thin film wiring structure is preferably 500 nm or less.

According to a third aspect of the present invention, there is provided a thin film transistor manufactured through a thermal history of at least 250 ° C. after the formation of the scanning signal line and the gate electrode, wherein the scanning signal line and the gate electrode are formed as described above. A thin film transistor comprising the thin film wiring structure according to the first or second aspect of the present invention.

In a fourth aspect of the present invention, there is provided a method of manufacturing a thin film transistor having a manufacturing step of passing a heat history of at least 250 ° C. after forming a scanning signal line and a gate electrode. Comprises a first conductive film, a second conductive film, and a third conductive film sequentially formed on a substrate, wherein the first conductive film is
The second conductive film is made of Ta or tantalum nitride, the second conductive film is made of Al, and the third conductive film is made of
A thin film wiring structure made of Ta or tantalum nitride, wherein the thickness of each of the first and third conductive films is 10% or less of the thickness of the second conductive film;
A method of manufacturing a thin film transistor, comprising: patterning a gate insulating film formed on the thin film wiring structure using an etching gas obtained by adding 5 to 20% of oxygen gas (O ₂ ) to chlorine gas (Cl ₂ ). It is in.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a thin film transistor having a manufacturing step of passing a heat history of at least 250 ° C. after forming a scanning signal line and a gate electrode. Comprises a first conductive film and a second conductive film sequentially formed on a substrate, wherein the first conductive film is made of Al, and the second conductive film is made of Ta or tantalum nitride. The second conductive film has a thickness of 10% or less of the thickness of the first conductive film, and has a gate insulating film formed on the thin film wiring structure. Oxygen gas (O ₂ ) in chlorine gas (Cl ₂ )
%. A method for manufacturing a thin film transistor, characterized in that patterning is performed using an etching gas added in%.

According to a sixth aspect of the present invention, there is provided a semiconductor device comprising: a plurality of scanning signal lines arranged on an insulating substrate; a plurality of video signal lines arranged so as to intersect the scanning signal lines; A thin film transistor disposed at each intersection of a line and the video signal line; a pixel electrode connected to the thin film transistor; and a liquid crystal display device that drives liquid crystal by an output of the pixel electrode. According to a second aspect of the present invention, there is provided a liquid crystal display device comprising the thin film wiring structure.

In the sixth aspect of the present invention, it is preferable that the scanning signal line having the thin film wiring structure is used as a gate electrode of the thin film transistor.

According to a seventh aspect of the present invention, there is provided a semiconductor device comprising: a plurality of scanning signal lines disposed on an insulating substrate; a plurality of video signal lines disposed so as to intersect the scanning signal lines; A thin film transistor arranged and formed at each intersection of a line and the video signal line; a pixel electrode connected to the thin film transistor; and a method of manufacturing a liquid crystal display device that drives a liquid crystal by an output of the pixel electrode. According to a fourth or fifth aspect of the present invention, there is provided a method for manufacturing a liquid crystal display device, which is manufactured by the manufacturing method according to the present invention.

Further, an eighth aspect of the present invention provides an organic EL device comprising:
In an active matrix drive type organic EL display device having a current control thin film transistor connected thereto, a scanning signal line forming an active matrix circuit is formed by the thin film wiring structure of the first or second invention. The feature is the organic EL display device.

In the eighth aspect of the present invention, it is preferable that a scanning signal line having the thin film wiring structure is used as a gate electrode of the thin film transistor.

A ninth aspect of the present invention provides an organic EL device comprising:
A method of manufacturing an active matrix drive type organic EL display device having a current control thin film transistor connected thereto, wherein the thin film transistor is manufactured by the fourth or fifth manufacturing method of the present invention. A method for manufacturing a display device.

[0044]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to specific examples, but the present invention is not limited to these examples.

[0045]

(Embodiment 1) This embodiment is an example in which a thin film transistor (TFT) substrate applied to a liquid crystal display device is manufactured. FIG. 1 shows a TFT using a thin film wiring structure according to this embodiment.
A cross section around the FT is schematically shown.

In FIG. 1, reference numeral 1 denotes a glass substrate, a gate electrode has a laminated structure of 2 to 5, 2 is a first conductive film made of Ta, 3 is a second conductive film made of Al, and 4 is a film formed of Ta. The third conductive film 5 is a fourth conductive film made of Ti. The gate insulating film 6 is made of SiN _X, 7 is a-S
i: H film, 8 n ⁺ -type a-Si: H film, the source electrode 9, 10 drain electrode, the pixel electrode 11 is made of ITO, 12 is an insulating protective film made of SiN _X.

FIGS. 2 to 4 are cross-sectional views showing the steps of manufacturing the TFT substrate of this embodiment. Hereinafter, the manufacturing process of the TFT substrate of the present embodiment will be described with reference to these drawings.

First, a predetermined thickness of 10 nm made of Ta is formed on a predetermined portion of the glass substrate 1 by magnetron sputtering.
Is formed on the first conductive film 2, and a second 270 nm-thick second conductive film made of Al is formed on the first conductive film 2 by magnetron sputtering.
Is formed thereon, and a third conductive film 4 of Ta is formed thereon by magnetron sputtering in the same manner as above, and a fourth film of Ti is formed thereon by magnetron sputtering. A conductive film 5 having a thickness of 10 nm was formed to form a laminate having the same pattern having a thickness of 300 nm as a whole (FIG. 2A).

In this embodiment, the first conductive film is Ta, and the second conductive film is Ta.
The third conductive film was made of Al, the third conductive film was made of Ta, and the fourth conductive film was made of Ti.
N _X, the third conductive layer is a nitride film of Ta TaN _X, fourth
The conductive film may be TiN _x , which is a Ti nitride film.

In general, TaN _x and TiN _x are formed by reactive sputtering. The specific resistance of the formed thin film can be controlled by changing the partial pressure of N ₂ during sputtering.

Next, patterning was performed by using a photolithography technique, and etching was performed by RIE using a mixed gas of BCl ₃ and Cl ₂ to form a predetermined pattern (FIG. 2B).

In the present embodiment, the laminated film thickness of the thin film wiring structure is 300 nm, but it can be up to about 150 to 500 nm, and most preferably 200 to 350 nm in consideration of the wiring resistance and the coverage of the gate insulating film. Also, T
The thickness of i and Ta is 1 of the main wiring material (second conductive film) Al.
0% or less, and the lower limit film thickness is preferably 5 nm or more.
Preferably, it is 10 to 20 nm.

Next, between one thin film wiring structure and the next one thin film wiring structure, I magnetron sputtering is used.
A transparent pixel electrode 11 made of a TO film was formed, and a predetermined pattern was formed by the above-described photolithography technique and dry etching (FIGS. 2C and 2D).

Next, after the glass substrate 1 is heated to 300 ° C. or higher (preferably to 350 ° C. or higher), plasma CVD is performed.
A gate insulating film 6 made of silicon nitride (SiN _x ) having a thickness of 400 nm, an a-Si: H film 7 having a thickness of 200 nm, and an n ⁺ -type a-Si: H film 8 having a thickness of 50 nm were formed by the method (FIG. 2). (E)).

When the gate insulating film 6 is formed, the glass substrate 1 is heated to 300 ° C. or higher, and plasma CVD is performed.
By forming a SiN _x film, the withstand voltage is 5 × 10 ⁶ V / c.
m or more is easily obtained.

Next, a pattern as shown in FIG. 3F was formed by the photolithography technique and dry etching described above. At this time, the gate insulating film 6, the a-Si: H film 7, and the n ⁺ -type a-Si: H film 8 are simultaneously etched.

Further, a-Si: H film 7, n ⁺ type aS
The i: H film 8 was removed by the above-described photolithography technique and dry etching to form a predetermined pattern (FIG. 3G).

Next, Al was formed by magnetron sputtering.
A conductive layer to be a source electrode 9 and a drain electrode 10 is formed to a thickness of 800 nm (FIG. 3 (h)), and then a predetermined pattern is formed by the photolithography technique and dry etching described above. Was formed (FIG. 3 (i)).

Next, a portion of the n ⁺ -type a-Si: H film 8 that was not covered with the source electrode 9 and the drain electrode 10 was etched to form a channel.

Next, 500 nm is formed by a plasma CVD method.
Insulating protective film 12 made of thick silicon nitride (SiN _x )
Was formed (FIG. 4 (j)).

In the thin film wiring structure according to the present embodiment, the first conductive film 2 made of Ta is formed as the lowermost layer, the fourth conductive film 5 formed of Ti is formed as the uppermost layer, and the second conductive film 5 formed of Al is formed between them. A third conductive film 4 made of a conductive film 3 and Ta is disposed, and the first, third, and fourth conductive films have a thickness of the second conductive film, respectively.
Since the thickness of the conductive film is less than 10%,
The resistance value of this thin film wiring structure is determined by the low resistance characteristic of the second conductive film 3 mainly made of Al.

The thin film wiring structure of the present embodiment is formed by Ti / Ta / A
1 / Ta (fourth conductive layer / third conductive layer / second conductive layer / first
Conductive layer). In the following embodiments, when the thin film wiring structure has a three-layer structure, the third conductive layer / the second conductive layer /
The description is made in the order of the first conductive layer. In the case of a two-layer structure, the description is made in the order of the second conductive layer / the first conductive layer.

In this embodiment, Ti / Ta / Al /
The total thickness of the Ta laminated film is set to 300 nm, the thickness of each of Ta and Ti is set to 5, 10, 15, and 20 nm.
Heat treatment was performed for 1 hour at 0 ° C. and 450 ° C., respectively, and specific resistance measurement and surface property observation were performed. Table 2 shows the results.

[0064]

[Table 2]

As shown in Table 2, at 290 ° C. and 45 ° C.
The specific resistance after heat treatment at 0 ° C. for 1 hour was 5 μΩcm
Below, surface defects such as hillocks were not observed. Thus, by laminating Ta between Ti and Al, the diffusion of Ti into Al was prevented, the rise in specific resistance after heat treatment was sufficiently suppressed, and the effect of the present invention was confirmed.

In this embodiment, the thickness of Ti and Ta is fixed at 10 nm, and the total thickness of the Ti / Ta / Al / Ta laminated film is 150, 200, 300, 400, and 500 n.
m, and heat-treated at 450 ° C. for 1 hour in a vacuum to measure a change in specific resistance. Table 3 shows the results.

[0067]

[Table 3]

As shown in Table 3, although the specific resistance increases as the layer thickness decreases, the specific resistance after heat treatment at 450 ° C. is 4 even when the Ti and Ta film thickness is 10 nm and the Al film thickness is 120 nm. .95 μΩcm. Therefore,
In the thin film wiring structure of the present embodiment, with respect to the demand for lowering the wiring resistance (5 μΩcm or less) due to higher definition, higher aperture ratio, larger size, etc. of the liquid crystal display device, it is sufficient to reduce the film thickness to 150 nm. It is possible to satisfy. still,
There is no particular upper limit to the upper limit of the laminated film thickness as the film thickness increases, since the specific resistance of the laminated film decreases. However, considering the wiring resistance and the coverage of the gate insulating film, there is no upper limit.
It is preferably from 0 to 500 nm, more preferably from 200 to 350 nm.
nm is preferred.

A liquid crystal display device can be constructed using the TFT substrate of this embodiment described above. The configuration and operation of the liquid crystal display device using the TFT substrate of the present embodiment are almost the same as the configuration and operation of a known liquid crystal display device of this type. Since this is not an essential part of the present invention, the description of the panel configuration and operation of the present embodiment will be omitted.

When the thin film wiring structure of this embodiment is used for a scanning signal line of a liquid crystal display device, the width of the thin film wiring structure becomes relatively narrow due to the high definition or large size of the active matrix panel. However, the resistance value does not become too high, and the scanning signal flowing through the scanning signal line is not attenuated or the waveform is not distorted.

Further, by using the thin film wiring structure of the present embodiment, the specific resistance is 5 μΩ when the total laminated film thickness is 300 nm or less.
cm or less, and application to high-definition panels became possible. Furthermore, by using the thin film wiring structure of the present invention, the withstand voltage of the gate insulating film is improved, the production yield is improved, and the gate insulating film can be made thinner.

An anodic oxide film Al ₃ O _{2 is formed} on the gate electrode.
Thus, the process for forming the same can be omitted, and a low-cost process can be constructed.

Further, in the TFT manufacturing process, the margin of the dry etching process of the gate insulating film (SiN _x ) is widened and the manufacturing can be performed with good yield, so that the cost can be greatly reduced and a high quality liquid crystal display device can be obtained. It is obtained.

In addition, since Ta having good adhesion is formed between the substrate 1 and the Al electrode, peeling of the gate electrode during the process was reduced, and the yield was improved. Further, the improvement in the adhesion has increased the subsequent process margin and reduced the cost.

(Embodiment 2) FIG. 5 is a schematic sectional view around a TFT using a thin film wiring structure according to this embodiment.
In FIG. 5, the same components as those shown in FIG. 1 are denoted by the same reference numerals.

In the first embodiment, Ti / Ta is used as the gate electrode material.
Although a four-layer structure of / Al / Ta was used, in this embodiment, Ti is used.
A / Ta / Al three-layer structure was used.

First, a predetermined thickness on a glass substrate 1 was formed on a predetermined portion of the glass substrate 1 by magnetron sputtering.
m first conductive film 3 is formed thereon, and a second 20 nm-thick second conductive film made of Ta is formed on the first conductive film 3 by magnetron sputtering.
And a 20 nm thick third conductive film 5 of Ti is formed thereon by magnetron sputtering to form a 350 nm-thick laminate having the same pattern as a whole. did.

In this embodiment, the first conductive film is made of Al and the second conductive film is made of Al.
The third conductive film was made of TaN _x , which is a Ta nitride film, and the third conductive film was made of TiN _x , which was a Ti nitride film. Is also good.

Next, patterning was performed by using a photolithography technique, and etching was performed by RIE using a CCl ₄ gas to form a predetermined pattern of the laminate.

Next, after heating the glass substrate 1 to 450 ° C., a gate insulating film 6 made of silicon nitride (SiN _x ) having a thickness of 400 nm and an a-Si: H film 7 having a thickness of 200 nm are formed by a plasma CVD method. And n ⁺ type a-Si:
An H film 8 was formed to a thickness of 50 nm.

Next, the gate insulating film 6, the a-Si: H film 7, and the n ⁺ -type a-Si: H film 8 were simultaneously etched by the above-described photolithography technique and dry etching.

Next, Al was formed by magnetron sputtering.
A conductive layer serving as the source electrode 9 and the drain electrode 10 was formed to a thickness of 800 nm, and a predetermined pattern was formed by the above-described photolithography technique and dry etching to form the source electrode 9 and the drain electrode 10.

Next, the IT is performed by magnetron sputtering.
A transparent pixel electrode 11 made of an O film was formed, and a predetermined pattern was formed by the above-described photolithography technique and dry etching.

Next, 500 nm is formed by the plasma CVD method.
Insulating protective film 12 made of thick silicon nitride (SiN _x )
Was formed.

In this embodiment, since Al is directly formed on the substrate (mainly glass), the adhesion is lower than that of the structure of Embodiment 1 in which Ta is laminated between the substrate and Al. Since the film forming process of the electrode is reduced from four steps to three steps, the cost is reduced.

(Embodiment 3) This embodiment is an example in which a TFT substrate applied to an organic EL display device is manufactured. FIG. 6 schematically shows a cross section around a TFT using a thin film wiring structure according to this embodiment. Shown in In FIG. 6, the same components as those shown in FIGS. 1 and 5 are denoted by the same reference numerals.

In the present embodiment, as in the second embodiment, a gate electrode (three-layered laminate), a gate insulating film, a-Si: H
A transparent pixel electrode composed of a film, an n ⁺ -type a-Si: H film, a source electrode, a drain electrode, and an ITO film was patterned by the above-described film forming technique, photolithographic technique, and dry etching. Note that a poly-Si film may be used instead of the a-Si: H film.

Next, the organic EL layer 14 and the upper common electrode 15 of the organic EL element were formed by a vacuum deposition method in a state where a metal mask was provided over the entire pixel region. This upper electrode is made of, for example, a magnesium film containing silver.

Thereafter, if necessary, a protective film 16 of, for example, SiNx is formed to improve the reliability, and an organic EL display is formed.

When an organic EL display is driven by an active matrix circuit, as shown in FIG. 7, each organic EL pixel has a set of thin film transistors for controlling a current supplied to the pixel. Connected.

That is, the organic EL display driven by the active matrix circuit is connected to the X-direction signal line 50.
1, Y direction signal line 502, power supply line 503, thin film transistor 504 for switch, thin film transistor 5 for current control
05, an organic EL element 506, an X-direction peripheral drive circuit, a Y-direction peripheral drive circuit, and the like.

In the above configuration, when the Y direction signal line 502 is selected and the switching thin film transistor 504 is turned on, the voltage of the X direction signal line 501 is supplied to the capacitor (capacity for holding charge) 507 through the switching thin film transistor 504. You.

When the Y direction signal line 502 is in a non-selected state, the switching thin film transistor 504 is turned off,
The voltage of the X-direction signal line 501 is held in a capacitor (capacity for holding charge) 507.

The terminal voltage of the capacitor (capacity for holding charge) 507 is equal to the gate of the current controlling thin film transistor 505,
A thin film transistor 50 for current control applied between the sources.
The current corresponding to the gate voltage and drain current characteristics of No. 5 flows through the power supply line 503 → the organic EL element 506 → the current control thin film transistor 505 → the Y-direction signal line 502, and the organic EL element 506 emits light.

At this time, if the relationship between the luminance of the organic EL element and the voltage applied to the capacitor is known, the organic EL element can emit light at a predetermined luminance.

The gate electrode of this embodiment is made of Ti / Ta / Al
In the TFT manufacturing process,
The margin of the dry etching process of the gate insulating film (SiN _x ) 6 is widened, and the production can be performed with a good yield, the cost can be greatly reduced, and a high quality EL display device can be obtained.

In this embodiment, since Al is directly formed on the substrate (mainly glass), the T
Although the adhesiveness is lower than the configuration in which a is laminated between the substrate and Al, the cost is reduced because the film formation process of the gate electrode is reduced from four steps to three steps.

Embodiment 4 This embodiment is an example in which a thin film transistor (TFT) substrate applied to a liquid crystal display device is manufactured. FIG. 8 schematically shows a cross section of a TFT portion using the thin film wiring structure according to the present embodiment and a contact hole (CH) portion requiring a selectivity of etching of the gate insulating film and Ta. In FIG. 8, the same components as those shown in FIGS. 1 and 5 are denoted by the same reference numerals.

In the first embodiment, the gate electrode material is Ti / Ta
Although a four-layer structure of / Al / Ta was used, in the present embodiment, Ta was used.
A three-layer structure of / Al / Ta was used.

First, a film of Ta having a thickness of 15 nm was formed on a predetermined portion of the glass substrate 1 by magnetron sputtering.
Is formed on the first conductive film 2, and a second conductive film 2 made of Al having a thickness of 250 nm is formed thereon by magnetron sputtering.
Is formed, and a third conductive film 4 made of Ta having a thickness of 15 nm is formed thereon by a magnetron sputtering method to form a laminated body of a predetermined same pattern having a thickness of 280 nm as a whole. did.

In this embodiment, the first conductive film is Ta, and the second conductive film is Ta.
The first conductive film was made of TaN _x , which is a nitride film of Ta, and the third conductive film was made of TaN _x , which was a nitride film of Ta. Is also good.

Next, patterning is performed using a photolithography technique, and RIE is performed using Cl ₂ and BCl ₃ gases.
To form a predetermined pattern of the laminate.

Next, after heating the glass substrate 1 to 450 ° C., a gate insulating film 6 made of silicon nitride (SiN _x ) having a thickness of 350 nm and an a-Si: H film 7 having a thickness of 200 nm are formed by a plasma CVD method. And n ⁺ type a-Si:
An H film 8 was formed to a thickness of 50 nm.

Next, a resist pattern was formed by the photolithography technique described above. Next, etching was performed by dry etching under the following conditions.

The dry etching conditions are as follows: chlorine gas (Cl
₂ ) A gas pressure of about 2.7 Pa (20 mTorr) using a mixed gas of 200 sccm and oxygen gas (O ₂ ) 30 sccm.
r), the RF power was 1 W / cm ² .

Table 4 shows Ta and the etching rate of the gate insulating film (SiN _x ) when the flow rate of the oxygen gas was changed with respect to the chlorine gas. In addition, chlorine gas flow rate 200sc
cm, and the oxygen gas flow rate was 0, 2.5, 5.0,
The etching rates of Ta and SiN were examined by adding 10, 15 and 20%.

[0107]

[Table 4]

As shown in Table 4, the addition of oxygen gas lowers the etching rate of Ta. When Ta is added at 10% or more, Ta is hardly etched.

Selection ratio (ER (SiN _x ): ER (T
a)) is 5: 1 with the addition of 2.5% oxygen, 22: 1 with the addition of 5.0%, Δ with the addition of 10.0%, and Δ with the addition of 15.0%.
Therefore, to obtain an etching rate selectivity of 20: 1, the amount of oxygen gas added to chlorine gas must be 5% or more.

As shown in Table 4, when a large amount of oxygen gas is added, the etching rate of the gate insulating film (SiN _x ) decreases. When 30% of oxygen gas is added, the etching rate decreases to 10 nm / min. Therefore, the practical addition amount of oxygen gas is 5% to 20% with respect to chlorine gas.
% Is appropriate.

In the case of this embodiment, the contact hole T
Since the etching amount of “a” was very small, it was possible to form a contact hole with very little damage.

Next, Al is formed by magnetron sputtering.
A conductive layer serving as the source electrode 9 and the drain electrode 10 was formed to a thickness of 800 nm, and a predetermined pattern was formed by the above-described photolithography technique and dry etching to form the source electrode 9 and the drain electrode 10.

Next, the IT is performed by magnetron sputtering.
A transparent pixel electrode 11 made of an O film was formed, and a predetermined pattern was formed by the above-described photolithography technique and dry etching.

Next, 500 nm is formed by the plasma CVD method.
Insulating protective film 12 made of thick silicon nitride (SiN _x )
Was formed.

In this embodiment, Ti (43 μΩcm) is used.
A change in specific resistance due to heat treatment when Ta (single element 13 μΩcm) having smaller specific resistance was used was measured. Table 5 shows the results.

[0116]

[Table 5]

As shown in Table 5, Ta also has a tendency that the specific resistance increases as the film thickness increases, similarly to Ti.
Low rate of increase in resistivity due to heat treatment, 450 in vacuum
Even after heat treatment at ℃ for 1 hour, the specific resistance is 5μΩ
cm or less. When the Ta film thickness was 10 nm or more, no defects such as hillocks occurred on the surface.

As described above, in this embodiment, the first conductive film is made of Ta or tantalum nitride, the second conductive film is made of Al,
The third conductive film is made of Ta or tantalum nitride, and the film thickness of each of the first and third conductive films is one of the film thickness of the second conductive film.
A thin film wiring structure is formed at 0% or less, and an etching gas obtained by adding 5% to 20% of oxygen gas (O ₂ ) to chlorine gas (Cl ₂ ) is added to a gate insulating film formed on the thin film wiring structure. By using and patterning, it is possible to sufficiently satisfy the demand for the lowering of the wiring (5 μΩcm or less) due to higher definition, higher aperture ratio, larger size, etc. of the liquid crystal display device, and to the TFT manufacturing process. In this case, the selectivity between the gate insulating film and Ta was sufficiently secured, defects such as contact failures in contact holes were reduced, and the yield was improved.

(Embodiment 5) In Embodiment 4, a three-layer structure of Ta / Al / Ta was used for the gate electrode material. However, in this embodiment, a two-layer structure of Ta / Al was used, and Same as Example 4.

In this embodiment, the first conductive film is made of Al and the second conductive film is made of Al.
Although Ta is used as the conductive film, TaN _X which is a Ta nitride film may be used as the second conductive film.

In this embodiment, the first conductive film is made of Al,
The second conductive film is made of Ta or tantalum nitride, and the film thickness of the second conductive film is 10% or less of the film thickness of the first conductive film to form a thin film wiring structure and formed on the thin film wiring structure. The gate insulating film is patterned by using an etching gas obtained by adding oxygen gas (O ₂ ) to chlorine gas (Cl ₂ ) in an amount of 5% to 20% to increase the definition of the liquid crystal display device as in the fourth embodiment. And the demand for lowering the wiring (5 μΩcm or less) due to the increase in aperture ratio and size, etc., and the selection ratio between the gate insulating film and Ta in the TFT manufacturing process is sufficient. Secured
Failures such as contact failures in contact holes were reduced, and the yield was improved.

In this embodiment, since Al is formed directly on the substrate (mainly glass), the adhesion is lower than that of Embodiment 4 in which Ta is laminated between the substrate and Al. In addition, since the film formation process of the gate electrode is reduced from three steps to two steps, the cost is reduced.

(Embodiment 6) In Embodiment 4, a three-layer structure of Ta / Al / Ta was used as a gate electrode material. In this embodiment, a four-layer structure of Ti / Ta / Al / Ta was used.

In this embodiment, the first conductive film is made of Ta, and the second conductive film is made of Ta.
The third conductive film was made of Al, the third conductive film was made of Ta, and the fourth conductive film was made of Ti.
N _X, the third conductive film is a nitride film of Ta TaN _X, fourth
The conductive film may be TiN _x , which is a Ti nitride film.

A thin film wiring was formed in the same manner as in Example 1, and the pattern was formed.
The configuration is the same as that of the fourth embodiment. But dry etchin
The etching conditions are different, and CF is used as the etching gas._Four+ O_Two,
SF ₆+ O_TwoWas used.

SF ₆ (200 sccm), O ₂ (30 sccm)
cm), a gas pressure of about 4 Pa (30 mTorr), and an RF power of 500 W. At this time, SiN
The etching rate of _X was 1000 ° / min, and the etching rate of Ti was 10 ° / min or less.

In the case of this embodiment, since the etching amount of Ti in the channel portion is very small, the damage is very small, and the channel can be formed. Further, the temperature resistance of the TFT substrate forming process is increased, and the process at 300 ° C. or more can be performed by using the thin film wiring structure of the present embodiment.
By forming a SiN film by VD, the withstand voltage is 5 × 1
0 ⁶ V / cm or more insulating films were obtained. Furthermore, in the thin-film wiring structure of the present embodiment, the occurrence of hillocks and the like can be prevented, and the withstand voltage of the insulating film is improved, so that the occurrence of short-circuit defects between the gate electrode and the source and drain electrodes is extremely reduced. As a result, the yield of TFTs was greatly improved.

[0128]

As described above, according to the present invention, the following effects can be obtained.

According to the thin film wiring structure of the first and second aspects of the present invention, with respect to the demand for lowering the resistance of wiring (5 μΩcm or less) due to higher definition, higher aperture ratio, and larger size of the liquid crystal display device, Even if the thickness is reduced to 500 nm or less, it is possible to sufficiently satisfy the requirements.

Further, when the thin film wiring structure of the first and second aspects of the present invention is used for a scanning signal line of a liquid crystal display device, the thin film wiring structure of the active matrix panel is increased based on higher definition or larger size. Even if the width is relatively narrow, the resistance value does not become too high, and a high-quality image can be formed without attenuating the scanning signal flowing through the scanning signal line or distorting the waveform It is. Further, the withstand voltage of the gate insulating film is improved, the production yield is improved, and the thickness of the gate insulating film can be reduced. Further, in the TFT manufacturing process, the gate insulating film (S
Since the margin of the dry etching process of iN _x ) is widened and manufacturing with a good yield is possible, the cost can be greatly reduced and a high quality liquid crystal display device can be obtained.

Further, by using the thin film wiring structure of the present invention, the temperature resistance of the TFT substrate forming process is increased, and
The process at over 00 ° C is possible, and the glass substrate
The insulating film having a withstand voltage of 5 × 10 ⁶ V / cm or more can be obtained by forming an SiN film by plasma CVD by heating to at least 00 ° C. Furthermore, in the thin-film wiring structure of the present invention, the occurrence of hillocks and the like can be prevented, and the withstand voltage of the insulating film has been improved, so that the occurrence of short-circuit defects between the gate electrode and the source / drain electrode is extremely reduced. TF
The yield of T was greatly improved.

According to the fourth and fifth methods of manufacturing a thin film transistor of the present invention, there is a demand for lowering the wiring resistance (5 μΩc) due to higher definition, higher aperture ratio, larger size, etc.
m or less), the selectivity between the gate insulating film and Ta is sufficiently ensured in the TFT manufacturing process, and defects such as contact failures in contact holes are reduced and the yield is improved. .

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing a cross section around a TFT of a TFT substrate applied to a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining a manufacturing process of the TFT according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining a manufacturing process of the TFT according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining a manufacturing process of the TFT according to the first embodiment of the present invention.

FIG. 5 is a diagram schematically showing a cross section around a TFT of a TFT substrate applied to a liquid crystal display device according to a second embodiment of the present invention.

FIG. 6 schematically shows a cross section around a TFT of a TFT substrate applied to an organic EL display device according to a third embodiment of the present invention.

FIG. 7 is an explanatory diagram of an organic EL display device according to a third embodiment of the present invention.

FIG. 8 is a diagram schematically showing a cross section around a TFT of a TFT substrate applied to a liquid crystal display device according to a fourth embodiment of the present invention.

FIG. 9 is an explanatory diagram of a conventional example.

FIG. 10 is a partial sectional view of a conventional thin film transistor.

[Explanation of symbols]

The first conductive and a fourth conductive film 6 SiN _X composed of the third conductive film 5 Ti made of the second conductive film 4 Ta consisting of conductive film 3 Al insulating film 7 a-Si of one glass substrate 2 Ta : H film 8 n ⁺ type a-Si: H film 9 Source electrode 10 Drain electrode 11 Pixel electrode made of ITO film 12 Insulating protective film made of SiN _X 13 Interlayer insulating film 14 Organic EL layer 15 Upper common electrode 16 Protective film 501 X direction signal line 502 Y direction signal line 503 Power supply line 504 Switch thin film transistor 505 Current control thin film transistor 506 Organic EL element 507 Capacitor

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/43 H01L 29/78 617L 5F110 21/336 21/88 R H05B 33/10 N 33/26 29 / 62 G 29/78 612C 617V (72) Inventor Tatsumi Shoji 3-30-2 Shimomaruko, Ota-ku, Tokyo F-term within Canon Inc. (reference) 2H092 GA25 JA26 JA40 JB24 JB57 KB04 MA07 MA18 NA28 NA29 3K007 AB18 BA06 DA02 4M104 AA09 BB17 BB32 CC05 FF13 GG09 HH03 HH16 5C094 AA05 AA14 AA42 AA43 BA03 BA29 BA44 CA19 EA04 EA07 JA01 JA08 5F033 GG04 HH08 HH18 HH21 HH32 HH33 JJ08 KK08 Q08 Q15 Q08 Q15 Q13 Q08 Q15 Q13 Q08 V15 5F110 AA03 AA16 AA26 AA28 BB01 CC07 DD02 EE01 EE03 EE04 EE11 EE15 EE44 FF03 FF30 GG02 GG15 GG24 GG45 HK03 HK09 HK16 HK33 NN04 NN24 NN35 NN72 NN73

Claims (12)

[Claims] 1. A thin film wiring structure laminated on a substrate, comprising: a first conductive film, a second conductive film, a third conductive film, and a fourth conductive film sequentially formed on the substrate. The first conductive film is made of Ta or tantalum nitride, the second conductive film is made of Al, and the third conductive film is made of Ta or tantalum nitride. The fourth conductive film is made of Ti or titanium nitride, and the thickness of each of the first, third, and fourth conductive films is 10% of the thickness of the second conductive film. A thin film wiring structure characterized by the following. 2. A thin film wiring structure laminated on a substrate, comprising: a first conductive film, a second conductive film, and a third conductive film sequentially formed on the substrate. The first conductive film is made of Al, and the second conductive film is
The third conductive film is made of Ta or tantalum nitride, and the third conductive film is made of Ti or titanium nitride.
The film thickness of each of the second and third conductive films is 10% or less of the film thickness of the first conductive film. 3. The total thickness of the thin film wiring structure is 500 nm.
The thin-film wiring structure according to claim 1, wherein: 4. A thin film transistor manufactured through a heat history of at least 250 ° C. after forming a scanning signal line and a gate electrode, wherein the scanning signal line and the gate electrode are formed. A thin film transistor characterized by comprising the thin film wiring structure described in (1). 5. A method for manufacturing a thin film transistor, comprising: a manufacturing process in which a heat history of at least 250 ° C. is formed after a scanning signal line and a gate electrode are formed. The first conductive film, the second conductive film, and the third conductive film, wherein the first conductive film is formed of Ta or tantalum nitride, and the second conductive film is formed of Al. And the third conductive film is made of Ta or tantalum nitride, and the thickness of each of the first and third conductive films is 10 times the thickness of the second conductive film.
% Of the gate insulating film formed on the thin film wiring structure using an etching gas obtained by adding 5 to 20% of oxygen gas (O ₂ ) to chlorine gas (Cl ₂ ). A method for manufacturing a thin film transistor. 6. A method of manufacturing a thin film transistor having a manufacturing process of passing a heat history of at least 250 ° C. after forming a scanning signal line and a gate electrode, wherein the scanning signal line and the gate electrode are sequentially formed on a substrate. The first conductive film is made of Al, the second conductive film is made of Ta or tantalum nitride, and the second conductive film is made of Ta or tantalum nitride. the film thickness of the second conductive film, the first is a thin film interconnect structure film is 10% or less of the thickness of the conductive film, a gate insulating film formed on said thin film wiring structure, chlorine gas (Cl ₂₎ A method for manufacturing a thin film transistor, characterized by patterning using an etching gas in which oxygen gas (O ₂ ) is added in an amount of 5 to 20%. 7. A plurality of scanning signal lines arranged and formed on an insulating substrate, a plurality of video signal lines arranged so as to intersect with the scanning signal lines, and a plurality of scanning signal lines and the video signal lines. The liquid crystal display device which drives a liquid crystal by the thin film transistor arranged and formed at each intersection, the pixel electrode connected to the thin film transistor, and the output of the pixel electrode, The scanning signal line according to any one of claims 1 to 3. A liquid crystal display device characterized by comprising a thin film wiring structure according to (1). 8. The liquid crystal display device according to claim 7, wherein a scanning signal line having the thin film wiring structure is used as a gate electrode of the thin film transistor. 9. A plurality of scanning signal lines arranged and formed on an insulating substrate, a plurality of video signal lines arranged and formed so as to intersect the scanning signal lines, and a plurality of scanning signal lines and the video signal lines. The method according to claim 5, wherein the thin film transistor is disposed at each intersection, a pixel electrode connected to the thin film transistor, and a liquid crystal display device that drives liquid crystal by an output of the pixel electrode. A method for manufacturing a liquid crystal display device, characterized by being manufactured by: 10. An active matrix drive type organic EL display device comprising an organic EL element and a current controlling thin film transistor connected thereto, wherein a scanning signal line constituting an active matrix circuit is provided. An organic EL display device comprising the thin-film wiring structure according to any one of the preceding items. 11. The organic EL display device according to claim 10, wherein a scanning signal line having the thin film wiring structure is used as a gate electrode of the thin film transistor. 12. A method of manufacturing an active matrix drive type organic EL display device comprising an organic EL element and a current controlling thin film transistor connected thereto, wherein the thin film transistor is manufactured by the method according to claim 5 or 6. A method of manufacturing a liquid crystal display device.