JP2002261248A - Semiconductor device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To provide a high-speed SRAM with a conventional technology.
It is difficult to achieve high integration as much as a RAM. An object of the present invention is to provide a device having good compatibility with the current Si process, a small device area and multiple negative resistance characteristics, and a small cell area and high integration using the multiple negative resistance device. It is an object of the present invention to provide a multi-valued SRAM cell which can perform the following. SOLUTION: The present invention provides a method for stacking and connecting two or more structures in which a tunnel barrier film is sandwiched between a degenerated p-type semiconductor layer and an n-type semiconductor layer in series. The semiconductor layer is made of a polycrystalline material.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention generally relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a non-linear element using a tunnel barrier film and a semiconductor device using the non-linear element.

[0002]

2. Description of the Related Art Conventionally, semiconductor integrated circuits have been formed by MOS type devices. The MOS element has a feature that its operation speed, power consumption and integration degree are improved by miniaturization, and has played a very important role in industry. However, ITRS (Internationa
l Technology Roadmap for Se
As shown in the roadmap of M. Semiconductors (1999), the solution has not yet been found for many of the key process technologies for miniaturization from the 0.1 μm generation. On the other hand, for semiconductor integrated circuits that are indispensable for the development of the information industry, there is a demand for higher speed, higher integration, and lower power consumption, particularly for higher performance of portable information terminals.

[0003] Among semiconductor integrated circuits, memories are also required to have high speed, low power consumption and large capacity. 1
A dynamic random access memory (DRAM), which is a volatile memory including one transistor and one capacitor, has been applied as a large-capacity memory because of its small cell area. However, since the storage deteriorates due to the leakage of the charge of the capacitor, a periodic refresh operation is required. On the other hand, a static random access memory (SRAM) which is the same volatile memory
Does not require a refresh operation and is excellent in high speed and low power consumption. However, to construct one cell, MOS
Since six or at least four type transistors are required, it is difficult to increase the capacity as compared with a DRAM.

On the other hand, in addition to the conventional MOS type device,
It is well known that an SRAM cell can be configured with a simpler configuration by using an element exhibiting a negative resistance characteristic. The negative resistance characteristic refers to a current-voltage characteristic in which there is a region where the current value decreases even when a larger voltage is applied to the element, and the current value as shown in FIG. The purpose is to show an N-shaped curve with a valley.

A memory cell using a negative resistance element was originally described in E. In a cell structure proposed by Goto et al., A binary SRAM cell is constituted by three elements of two Esaki diodes exhibiting negative resistance characteristics and one transistor (E. Goto et al., IRETT).
rans. Electron. Comp. , Marc
h, 1960, p. 25). This Esaki diode is replaced by a resonant tunneling diode (RTD), and a three-element cell has also been studied by RCA (RH Bergman et al., RCA).
Rev .. , June, 1962, p. 152). It should be noted here that the current-voltage characteristic of the RTD shows a multiple negative resistance characteristic having a plurality of peaks in the current value, and by using this characteristic, a multi-valued SRAM cell instead of a binary one can be constituted by three elements. That is. This makes it possible to further increase the capacity of the memory.

However, RTDs having good multiple negative resistance characteristics have not yet been developed for Si-based materials, which are currently the center of the semiconductor industry. In addition, in the case of an Esaki diode which is a single negative resistance element, multiple negative resistance characteristics cannot be obtained unless a plurality of Esaki diodes are connected in series.
It is difficult to realize M cells.

[0007]

As described above, it is considered that it is difficult to integrate an SRAM having an excellent high-speed performance as high as a DRAM with the current technology. An object of the present invention is to provide a device having good compatibility with the current Si process, a small device area, and multiple negative resistance characteristics.
It is another object of the present invention to provide a multi-valued SRAM cell having a small cell area and capable of high integration by using the multiple negative resistance elements.

[0008]

In order to achieve the above-mentioned object, the present invention provides a method of stacking two or more structures in which a tunnel barrier film is sandwiched between a degenerated p-type semiconductor layer and an n-type semiconductor layer. In this case, the p-type semiconductor layer and the n-type semiconductor layer are made of a polycrystalline material.

The first semiconductor device according to the present invention comprises a degenerated high-concentration n-type semiconductor layer in which the Fermi level is located in the conduction band, and a degenerated high-concentration p-type semiconductor layer in which the Fermi level is located in the valence band. A high-concentration n-type semiconductor layer and a high-concentration p-type semiconductor layer made of a polycrystalline material, and a high-concentration n-type semiconductor layer and a high-concentration n-type semiconductor layer. It has a structure in which at least two pn connection structures sandwiching a tunnel barrier film between the concentration p-type semiconductor layers are connected in series in the forward direction via the tunnel barrier film.

According to the first semiconductor device, at least two pn connection structures in which a tunnel barrier film is sandwiched between a high-concentration n-type semiconductor layer and a high-concentration p-type semiconductor layer are connected in series via the tunnel barrier film. A multi-negative resistance characteristic having two or more peak current values because the degenerated high-concentration pn connection structure connected in the forward direction and sandwiching the tunnel barrier film is connected in series via the tunnel barrier film Can be obtained. Further, since the high-concentration n-type semiconductor layer and the high-concentration p-type semiconductor layer are made of a polycrystalline body, it is possible to form a stack of degenerate high-concentration pn connection structures sandwiching a tunnel barrier film, The element area can be reduced to 以下 or less as compared with the case of arranging them in a plane.

In the first semiconductor device, the high-concentration n-type semiconductor layer and the high-concentration p-type semiconductor layer are made of silicon, silicon germanium, or silicon germanium carbon, and the tunnel barrier film is a silicon oxide film, a silicon nitride film, or a silicon oxynitride. It is preferable that it is made of a film.

[0012] The second semiconductor device according to the present invention comprises a degenerated high-concentration n-type semiconductor layer in which the Fermi level is located in the conduction band and a degenerated high-concentration p-type semiconductor layer in which the Fermi level is located in the valence band. In a semiconductor device including a semiconductor layer, a tunnel barrier film having a thickness capable of tunneling electrons, and a conductive layer having a lower resistance than the tunnel barrier film, the high-concentration n-type semiconductor layer and the high-concentration p-type semiconductor layer are At least two pn connection structures each made of a polycrystal and having a tunnel barrier film interposed between a high-concentration n-type semiconductor layer and a high-concentration p-type semiconductor layer were connected in series in a forward direction via a conductive layer. It has a structure.

According to the second semiconductor device, at least two pn connection structures in which a tunnel barrier film is interposed between a high-concentration n-type semiconductor layer and a high-concentration p-type semiconductor layer are sequentially connected via a conductive layer. Since the depleted high-concentration pn connection structure sandwiching the tunnel barrier film is connected in series via a conductive layer having a lower resistance than the tunnel barrier film, An element having multiple negative resistance characteristics having two or more peak current values at a lower voltage can be obtained. Further, since the high-concentration n-type semiconductor layer and the high-concentration p-type semiconductor layer are made of a polycrystalline body, it is possible to form a stack of degenerate high-concentration pn connection structures sandwiching a tunnel barrier film, The element area is 1 compared with the case of arranging in the plane.
/ 2 or less.

In the second semiconductor device, the high-concentration n-type semiconductor layer and the high-concentration p-type semiconductor layer are made of silicon, silicon germanium, or silicon germanium carbon, and the tunnel barrier film is a silicon oxide film, a silicon nitride film, or a silicon oxynitride. It is preferable that the conductive layer is made of a metal or a metal silicide.

The third semiconductor device according to the present invention comprises a degenerated high-concentration n-type semiconductor layer in which the Fermi level is located in the conduction band and a degenerated high-concentration p-type semiconductor layer in which the Fermi level is located in the valence band. Device comprising a semiconductor layer having a thickness that allows tunneling of electrons, a tunnel barrier film having a thickness capable of tunneling electrons, and a semiconductor layer having a lower diffusion coefficient than a high-concentration n-type semiconductor layer and a high-concentration p-type semiconductor layer for added impurities. A high-concentration n-type semiconductor layer, a high-concentration p-type semiconductor layer, and a semiconductor layer are made of polycrystalline material, and a pn connection in which a tunnel barrier film is interposed between the high-concentration n-type semiconductor layer and the high-concentration p-type semiconductor layer. The structure has a structure in which at least two are connected in series in the same direction via a semiconductor layer.

According to the third semiconductor device, at least two pn connection structures in which a tunnel barrier film is interposed between the high-concentration n-type semiconductor layer and the high-concentration p-type semiconductor layer are sequentially connected via the semiconductor layer. Since the depleted high-concentration pn connection structure sandwiching the tunnel barrier film is connected in series via a semiconductor layer having a lower resistance than the tunnel barrier film, An element having multiple negative resistance characteristics having two or more peak current values at a lower voltage can be obtained. The semiconductor layer has a high concentration n with respect to the added impurities.
Has a lower diffusion coefficient than the high-concentration semiconductor layer and the high-concentration p-type semiconductor layer. Can be formed steeply. Further, since the semiconductor layer is more thermally stable than a conductive layer such as a metal or a metal silicide, the degree of freedom in temperature in a manufacturing process is increased. Further, a high concentration n-type semiconductor layer and a high concentration p
Since the semiconductor layer and the semiconductor layer are made of a polycrystalline material, it is possible to laminate a degenerate high-concentration pn connection structure with a tunnel barrier film interposed therebetween. Thus, the element area can be reduced to 以下 or less.

In the third semiconductor device, the high-concentration n-type semiconductor layer and the high-concentration p-type semiconductor layer are made of silicon, the tunnel barrier film is made of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. It is preferably made of silicon germanium or silicon germanium carbon.

The fourth semiconductor device according to the present invention has a pn connection structure in which a tunnel barrier film is sandwiched between a high-concentration n-type polycrystalline semiconductor layer and a high-concentration p-type polycrystalline semiconductor layer.
A first stacked structure connected in series in the forward direction, a second stacked structure having the same structure as the first stacked structure, and a transistor, and a high-concentration p-type which is one end of the first stacked structure. The polycrystalline semiconductor layer is connected to a power supply voltage line, the high-concentration n-type polycrystalline semiconductor layer at one end of the second stacked structure is connected to a ground line, and the high-concentration n-type polycrystalline semiconductor at one end of the first stacked structure is connected. The crystalline semiconductor layer and the high-concentration p-type polycrystalline semiconductor layer which is one end of the second stacked structure are connected to form a storage node, the storage node is connected to the drain of the transistor, the gate of the transistor is connected to the word line, and the source is connected to the source. Have a structure in which a bit line and a substrate are connected to a ground line.

According to the fourth semiconductor device, the high-concentration p-type polycrystalline semiconductor layer which is one end of the first laminated structure is connected to the power supply voltage line, and the high-concentration n-type polycrystalline semiconductor layer which is one end of the second laminated structure. The crystal semiconductor layer is connected to the ground line, and the high-concentration n-type polycrystalline semiconductor layer which is one end of the first stacked structure and the high-concentration p-type polycrystalline semiconductor layer which is one end of the second stacked structure are connected and stored. A storage node is connected to the drain of the transistor, the gate of the transistor is connected to the word line, the source is connected to the bit line, and the substrate is connected to the ground line.
And the second stacked structure are connected in series in the forward direction to form a multi-valued stable circuit, and the voltage of the storage node can be controlled by a transistor connected to the storage node, so that a multi-valued memory is formed. can do. Further, since a multilayer structure of a degenerated polycrystalline high-concentration pn connection structure with a tunnel barrier film interposed therebetween is used to form a multi-negative resistance element, the element area is smaller than that in which the elements are arranged in a plane. Can be reduced to １ ／ or less.

In the fourth semiconductor device, when forming the first laminated structure and the second laminated structure, a tunnel barrier film is formed between the high-concentration n-type polycrystalline semiconductor layer and the high-concentration p-type polycrystalline semiconductor layer. When at least two sandwiched pn connection structures are connected in series via a tunnel barrier film in the forward direction, the pn connection structure can be stacked while maintaining a high concentration while suppressing mutual diffusion of impurities, and the peak current value can be increased. , The operation margin of the multi-level memory is increased.

In the fourth semiconductor device, when forming the first stacked structure and the second stacked structure, a tunnel barrier film is formed between the high-concentration n-type polycrystalline semiconductor layer and the high-concentration p-type polycrystalline semiconductor layer. When at least two of the sandwiched pn connection structures are connected in series in the forward direction via a conductive layer having a lower resistance value than the tunnel barrier film, the voltage drop at the connection portion is small, and two or more pn connection structures are formed at a lower voltage. Since a multi-negative resistance characteristic having a peak current value can be obtained, a difference in voltage at each stable point is increased, and a multi-valued memory that operates stably with a large operation margin can be obtained.

In the fourth semiconductor device, when forming the first stacked structure and the second stacked structure, a tunnel barrier film is formed between the high-concentration n-type polycrystalline semiconductor layer and the high-concentration p-type polycrystalline semiconductor layer. A semiconductor made of a polycrystalline body having a high-concentration n-type polycrystalline semiconductor layer and a diffusion coefficient lower than that of a high-concentration p-type polycrystalline semiconductor layer with respect to an impurity added to at least two pn connection structures sandwiched therebetween in the forward direction. By connecting via layers, the pn connection structure can be stacked while maintaining high concentration by suppressing mutual diffusion of impurities as compared with a case where the high concentration n-type semiconductor layer and the high concentration p-type semiconductor layer are directly joined. Since a good multiple negative resistance characteristic having a high peak current value can be obtained, the operation margin of the multilevel memory is increased. In addition, the polycrystalline semiconductor layer has a lower resistance value than the tunnel barrier film, so that the voltage drop at the connection portion is smaller, and a multiple negative resistance having a lower voltage and two or more peak current values. Since the characteristics can be obtained, the difference between the voltages at each stable point increases,
A multi-valued memory having a large operation margin and stable operation can be obtained. Further, since the semiconductor layer is more thermally stable than a conductive layer such as a metal or a metal silicide, the degree of freedom in temperature in a manufacturing process is increased.

In the fourth semiconductor device, when the high-concentration p-type semiconductor layer which is one end of the laminated structure is formed so as to be in contact with the drain of the p-channel transistor of the same conductivity type, the wiring, the contact window, and the element isolation region are formed. Is unnecessary, so that the cell size of the multilevel memory can be reduced.

Similarly, in the fourth semiconductor device, the high-concentration n-type semiconductor layer at one end of the stacked structure has the same conductivity type as n.
When it is formed so as to be in contact with the drain of the channel transistor, a wiring, a contact window, and an element isolation region are not required, so that the cell size of the multi-level memory can be reduced.

In the fourth semiconductor device, the semiconductor substrate is
An SOI substrate is desirable.

In the fourth semiconductor device, the high-concentration n-type polycrystalline semiconductor layer and the high-concentration p-type polycrystalline semiconductor layer are made of silicon, silicon germanium, or silicon germanium carbon, and the tunnel barrier film is a silicon oxide film or a silicon nitride film. Alternatively, the conductive layer is preferably made of a metal or metal silicide, and the semiconductor layer is preferably made of silicon germanium or silicon germanium carbon.

According to the first method of manufacturing a semiconductor device of the present invention, a first conductive type semiconductor substrate is masked on a first conductive type semiconductor substrate and a first conductive type first conductive type is formed in a laminated structure forming region.
Forming a degenerated high-concentration semiconductor layer, forming a first tunnel barrier film over the entire surface of the semiconductor substrate so that a tunnel current flows, and forming a first tunnel barrier film over the entire surface of the first tunnel barrier film. Forming a two-conductivity-type second high-concentration polycrystalline semiconductor layer so as to degenerate;
Forming a second tunnel barrier film over the entire surface of the high-concentration polycrystalline semiconductor layer so that a tunnel current flows; and forming a first tunnel barrier film over the entire surface of the second tunnel barrier film.
Forming a third high-concentration polycrystalline semiconductor layer of conductivity type so as to degenerate, and forming a third tunnel barrier film over the entire surface of the third high-concentration polycrystalline semiconductor layer so that tunnel current flows Forming a second highly doped polycrystalline semiconductor layer of the second conductivity type so as to degenerate over the entire surface of the third tunnel barrier film; and masking the electrode formation region of the stacked structure. 2 high-concentration polycrystalline semiconductor layer, second
By etching the tunnel barrier film, the third high-concentration polycrystalline semiconductor layer, the third tunnel barrier film, and the fourth high-concentration polycrystalline semiconductor layer, an electrode having a multilayer structure is formed on the semiconductor substrate. Forming a first insulating film over the entire surface of the semiconductor substrate, and then etching the first insulating film using the stacked structure forming region as a mask, thereby opening a transistor forming region. After forming a second insulating film over the entire opening of the transistor forming region, a conductive film is formed over the entire surface of the semiconductor substrate, and the gate insulating region of the transistor is masked to form a second insulating film and a conductive film. A step of forming a gate insulating film in the transistor formation region and a gate electrode on the gate insulating film by etching, and a step of forming a second conductive film on the semiconductor substrate by etching. Implantation using a gate electrode as a mask by using impurity ions of a negative electrode, a second source and drain of a transistor is formed on the semiconductor substrate in the gate length direction of the gate electrode.
Forming a conductive type diffusion layer; and depositing a third insulating film over the entire surface of the semiconductor substrate to protect the opened transistor formation region.

According to the first method for manufacturing a semiconductor device, since the transistor is formed after the entire laminated structure is formed, the transistor characteristics are reduced by the high-temperature heat treatment process required for the step of forming the depleted high-concentration semiconductor layer of the laminated structure. Deterioration is eliminated and transistor characteristics as designed are obtained. On the other hand, since the stacked structure can be sufficiently subjected to a high-temperature heat treatment, the number of activated impurities in the high-concentration semiconductor layer increases and the carrier concentration increases, resulting in a good multi-negative resistance characteristic having a high peak current value. Can be obtained. As a result, the operation margin of the multi-level memory is increased, and more stable operation is possible.

In the first method of manufacturing a semiconductor device, the high-concentration n-type polycrystalline semiconductor layer and the high-concentration p-type polycrystalline semiconductor layer are made of silicon, silicon germanium, or silicon germanium carbon, and the tunnel barrier film is a silicon oxide film or It is preferably made of a silicon nitride film or a silicon oxynitride film.

According to a second method of manufacturing a semiconductor device according to the present invention, a transistor formation region is masked on a semiconductor substrate of a first conductivity type, and a first degenerated high conductivity type of a first conductivity type is formed in a stacked structure formation region. Forming a first semiconductor layer, a step of forming a first tunnel barrier film over the entire surface of the semiconductor substrate so that a tunnel current flows, and a step of forming a second conductivity type over the entire surface of the first tunnel barrier film. Forming the second high-concentration polycrystalline semiconductor layer so as to degenerate, and lowering the added impurities from the second high-concentration polycrystalline semiconductor layer over the entire surface on the second high-concentration polycrystalline semiconductor layer Forming a semiconductor layer having a diffusion coefficient, forming a third high-concentration polycrystalline semiconductor layer of the first conductivity type over the entire surface of the semiconductor layer so as to degenerate, and forming a third high-concentration polycrystalline All over the semiconductor layer Forming a second tunnel barrier film so that a tunnel current flows, and forming a second high-concentration fourth high-concentration polycrystalline semiconductor layer of the second conductivity type over the entire surface of the second tunnel barrier film. A second high-concentration polycrystalline semiconductor layer, a semiconductor layer, a third high-concentration polycrystalline semiconductor layer,
Forming a layered electrode on the semiconductor substrate by etching the tunnel barrier film and the fourth high-concentration polycrystalline semiconductor layer, and forming the first insulating film over the entire surface of the semiconductor substrate. After the deposition, a step of opening the transistor formation region was performed by etching the first insulation film using the stacked structure formation region as a mask, and a second insulation film was formed over the entirety of the opened transistor formation region. Thereafter, a conductive film is formed over the entire surface of the semiconductor substrate, and the second insulating film and the conductive film are etched using the gate electrode forming region of the transistor as a mask, so that the gate insulating film and the gate are formed in the transistor forming region. Forming a gate electrode on the insulating film, and using the gate electrode as a mask on the semiconductor substrate using impurity ions of the second conductivity type; By ion implantation, definitive on the semiconductor substrate, the second as the source and the drain of the transistor in the gate length direction of the gate electrode
Forming a conductive type diffusion layer; and depositing a third insulating film over the entire surface of the semiconductor substrate to protect the opened transistor formation region.

According to the second method for manufacturing a semiconductor device, since the transistor is formed after the entire stacked structure is formed, the transistor characteristics are reduced by the high-temperature heat treatment process required for the step of forming the depleted high-concentration semiconductor layer of the stacked structure. Deterioration is eliminated and transistor characteristics as designed are obtained. On the other hand, since the stacked structure can be sufficiently subjected to a high-temperature heat treatment, the number of activated impurities in the high-concentration semiconductor layer increases and the carrier concentration increases, resulting in a good multi-negative resistance characteristic having a high peak current value. Can be obtained. In addition, since the semiconductor layer made of a polycrystalline material has a lower resistance value than the tunnel barrier film, the voltage drop at the connection portion is smaller, and the multi-negative resistance characteristic has a lower voltage and two or more peak current values. , The difference between the voltages at each stable point increases. As a result, a multi-valued memory having a large operation margin and stable operation can be obtained.

In the second method of manufacturing a semiconductor device, the high-concentration n-type polycrystalline semiconductor layer and the high-concentration p-type polycrystalline semiconductor layer are made of silicon, and the tunnel barrier film is a silicon oxide film, a silicon nitride film, or a silicon nitride film. The semiconductor layer made of an oxynitride film and having a low diffusion coefficient is preferably made of silicon germanium or silicon germanium carbon.

[0033]

(First Embodiment) A first embodiment of the present invention.
An embodiment will be described with reference to the drawings.

FIG. 1 is a sectional view showing the structure of a multiple negative resistance element which is a semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, a p-type polysilicon layer 12 as a high-concentration p-type semiconductor layer and a p-type polysilicon layer 12 as a high-concentration n-type semiconductor layer formed on a silicon oxide film 11 formed on a silicon substrate so as to degenerate. An n-type polysilicon layer 13 is provided.
Since each impurity concentration of the p-type polysilicon layer 12 and the n-type polysilicon layer 13 is at least 1 × 10 ¹⁹ cm ⁻³ ,
Since the Fermi level of the p-type polysilicon layer 12 is located in the valence band and the Fermi level of the n-type polysilicon layer 13 is located in the conduction band, the p-type polysilicon layer 12 and n The mold polysilicon layer 13 is in a degenerate state.

At the interface between the p-type polysilicon layer 12 and the n-type polysilicon layer 13, a tunnel barrier film 14 made of silicon oxynitride having a thickness of 1.0 to 2.0 nm is formed. A degenerated pn connection structure 15 made of polysilicon is formed. A stacked structure in which a pn connection structure 16 having the same structure as the pn connection structure 15 is connected in series in the same direction in the forward direction via the same tunnel barrier film 14 on the pn connection structure 15. 17 are formed.

The interlayer insulating film 18 formed over the entire surface of the silicon oxide film 11 includes a p-type polysilicon layer 12 in the pn connection structure 15 and an n-type polysilicon layer 12 in the pn connection structure 16.
Contact holes for exposing the surface of the mold polysilicon layer 13 are respectively formed, contacts 19 filled with tungsten are formed in each contact hole, and each contact 19 is formed of the aluminum wiring 2.
0 are electrically connected to each other. A voltage is applied to the laminated structure 17 via the aluminum wiring 20, and is controlled as a diode having multiple negative resistance characteristics having two peak currents.

Next, the operation principle of the multiple negative resistance element according to this embodiment will be described.

First, FIG. 2 shows the current-voltage characteristics of each pn connection structure. Each pn connection structure exhibits a negative resistance characteristic having one peak current according to the same operation principle as the Esaki diode. However, since the tunnel barrier film 14 is formed between the p-type polysilicon layer 12 and the n-type polysilicon layer 13, the p-type polysilicon layer 12 suppresses the mutual diffusion of impurities and has a steep concentration gradient.
-Maintain the n connection structure. In addition, the energy barrier of the tunnel barrier film made of silicon oxynitride suppresses a thermal diffusion current that tends to flow as the forward bias increases, so that a peak-to-valley ratio (PVR), which is a ratio of a peak current value to a valley current value, is used. : Peak-to-valley
Good negative resistance characteristics with high (Ratio) can be obtained.

When two pn connection structures are connected in series so as to be in the forward direction, a circuit diagram as shown in FIG. 3 is obtained, and the current-voltage characteristic is a negative voltage having two peak currents as shown in FIG. It becomes a resistance characteristic. Similarly, p-
When a plurality of n-connection structures are connected in series so as to be in the forward direction, multiple negative resistance characteristics having a peak current by the number of connected n-connection structures can be obtained.

Here, since each pn connection structure is connected via a tunnel barrier film made of silicon oxynitride, mutual diffusion of impurities at the connection interface is suppressed, and each pn connection structure is connected.
The n-connection structure is stacked while maintaining a high concentration. Also,
A portion where each pn connection structure is connected in series via a tunnel barrier is in a state where a reverse bias is applied to the pn connection structure, and a large electric field is applied to the thin tunnel barrier film. , A tunnel current larger than that in the state where the voltage is applied flows, and has a lower resistance value than each pn connection structure. Therefore, the voltage drop due to the portion connecting each pn connection structure in series via the tunnel barrier is small,
Sufficient voltage is applied to the -n connection structure.

FIGS. 5A to 5I briefly show the reason why multiple negative resistance characteristics can be obtained using a circuit in which two pn connection structures shown in FIG. 3 are connected in series. FIG. 6 shows a negative resistance characteristic having two peak currents obtained from the circuit of FIG. The intersection of the current-voltage characteristic 51 of the pn connection structure 31 in FIG. 3 and the load characteristic 52 of the pn connection structure 32 in FIG.
Operating points 53a to 53i. 5A to 5I, two intersections 54 between the load characteristic 52 and the horizontal axis of the graph representing the voltage indicate the voltage applied to the series circuit 33, and two current values at the operating points 53a to 53i. The current value of the series circuit 33 is shown. On the other hand, the voltages at the operating points 53a to 53i are p
The voltage applied to the pn connection structure 32 indicates the voltage applied to the pn connection structure 32.
It is a value obtained by subtracting the voltage value of ~ 53i. In FIG. 5A, the voltage is equally distributed to each pn connection structure. Next, after the state of FIG. 5B in which the current value peaks, as shown in FIG. 5C, when the load characteristic 52 has a smaller peak current, the operating point has a smaller voltage. , More voltage is distributed to the pn connection structure 32, which is a load, than the pn connection structure 31. Then, after the state of FIG. 5D in which the current value becomes the minimum value, the voltage applied to the pn connection structure 32 of the load does not change so much, and the voltage applied to the pn connection structure 31 increases. Then, the state shown in FIG. 5F is reached in which the current value peaks again through the state shown in FIG. After FIG. 5 (g), the current value again takes the minimum value, and after FIG. 5 (h), the same voltage is applied again, and as shown in FIG. 5 (i), the current monotonously increases as the voltage increases. It will only be done. As a result, the locus of the operating points 53a to 53i has a negative resistance characteristic having two peaks as shown in FIG. If the peak current of the load characteristic 52 is larger than that of the current-voltage characteristic 51, the operating point moves to the higher voltage, and the load p-
Since the voltage distribution is opposite to that of the previous example in which more voltage is distributed to the pn connection structure 31 than to the n connection structure 32, the order in which the two peaks appear changes, but the negative resistance characteristic having two peak currents Is still obtained.

As described above, p-
When a plurality of n-connection structures are connected in series so as to be in the forward direction, multiple negative resistance characteristics having a plurality of peak currents can be obtained. However, if the degenerated high-concentration p-type semiconductor layer in the pn connection structure is formed in a substrate made of single-crystal silicon as in the conventional example shown in FIG. Since a plurality of pn connection structures 71 must be arranged, the area of the multiple negative resistance characteristic element increases.

Accordingly, in the present embodiment, the degenerated high-concentration p-type semiconductor layer and high-concentration n-type semiconductor layer are formed of polycrystalline polysilicon, so that the underlying substrate can be made of silicon oxide, It is also possible to form a pn connection structure by stacking on silicon oxynitride or the same polycrystalline polysilicon. Therefore, using the method of the present invention, the pn connection structure 15 and the pn connection structure shown in FIG.
It is possible to easily form a laminated structure in which the connection structure 16 is connected in series so as to be in the forward direction via the tunnel barrier film 14 made of silicon oxynitride. As a result, as shown in FIG. 8, in the device using the laminated structure 81 of the present embodiment, the area of the device in the conventional example manufactured side by side in the plane is one unit.
/ 2. In the present embodiment, a multiple negative resistance element having two peak currents is used. However, a multiple negative resistance element having more peak currents may be formed by stacking a larger number of pn connection structures. Accordingly, the effect of reducing the element area can be further enhanced as compared with the present embodiment.

In the present embodiment, a p-type polysilicon layer 12 as a high-concentration p-type semiconductor layer is formed on a silicon oxide film 11 formed on a silicon substrate, and then a tunnel barrier film 14 is interposed therebetween. N as a concentration n-type semiconductor layer
Although the type polysilicon layer 13 is formed, a multi-negative resistance element that operates by reversing the polarity of all the p-type and n-type to form a laminated structure and reversing the polarity of the applied voltage can be configured. Needless to say.

When a laminated structure is formed directly on a single-crystal silicon substrate, even if a high-concentration semiconductor layer corresponding to the lowermost portion of the laminated structure is formed on a silicon substrate made of single-crystal silicon, a multiple negative resistance element is formed. Can be formed.

As shown in FIG. 9, as a first modification of the first embodiment, instead of connecting each pn connection structure via a tunnel oxide film, a resistance value lower than that of the tunnel oxide film is used. They are connected via a titanium silicide film 91 as a conductive layer. Here, the same members as those shown in FIG.

According to this modification, the effect of the multiple negative resistance element of the first embodiment can be obtained, and in addition, each pn connection structure can be formed through the titanium silicide 91 having a lower resistance than the tunnel oxide film. Since the connection is made, the voltage drop at the part where each pn connection structure is connected in series via the titanium silicide 91 is smaller than when connected via the tunnel oxide film, so that each pn connection structure is more reliable. As a result, as shown in FIG. 10, an element having a multi-negative resistance characteristic having two or more peak current values at a lower voltage in the current-voltage characteristic can be applied. Obtainable. The operation as a multiple negative resistance element is the same as that of the multiple negative resistance element according to the first embodiment.

In this embodiment, silicon is mainly used as a material. However, a multi-negative resistance element can be manufactured by using silicon germanium or silicon germanium carbon. In particular, when the high-concentration p-type semiconductor layer is formed of silicon germanium or silicon-germanium carbon, a p-type semiconductor layer having a higher concentration can be formed as compared with a case where the high-concentration p-type semiconductor layer is formed of silicon. An n-connection structure can be formed, and a multiple negative resistance element having a high peak current can be obtained.

As shown in FIG. 11, as a second modification of the first embodiment, instead of connecting each pn connection structure via a tunnel oxide film, a polysilicon layer The connection is made via a silicon germanium layer 92 as a polycrystalline semiconductor layer having a lower diffusion coefficient. The composition is expressed as, for example, Si (1-x) Gex, where x = 0.1.
A mixed crystal is formed at a ratio of about 0.6. The film thickness is 2 to 20 nm. Here, the same members as those shown in FIG.

According to this modification, the effect of the multiple negative resistance element in the first embodiment can be obtained, and the polycrystalline silicon germanium layer 92 having a diffusion coefficient lower than that of the polysilicon layer for added impurities can be obtained. Since the respective pn connection structures are connected to each other, the pn connection structures can be stacked while suppressing the mutual diffusion of impurities and maintaining a high concentration, and a good multiple negative resistance characteristic having a high peak current value can be obtained. be able to. In addition, since the polycrystalline silicon germanium layer 92 has a lower resistance than the tunnel barrier film, the voltage drop at the portion where each pn connection structure is connected in series via the polycrystalline silicon germanium layer 92 is reduced by tunnel oxidation. Since it is smaller than the case where connection is made via a film, a sufficient voltage can be applied to each pn connection structure with certainty. As a result, as shown in FIG. It is considered that an element having multiple negative resistance characteristics having two or more peak current values at a low voltage can be obtained. The operation as a multiple negative resistance element is the same as that of the multiple negative resistance element according to the first embodiment.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 12 is a sectional view showing the configuration of a multi-valued memory (SRAM) which is a semiconductor device according to the second embodiment of the present invention. In the multi-valued SRAM shown in FIG.
Reference numeral 12 denotes a multiple negative resistance element having two peak currents having a structure similar to that of the semiconductor device according to the first embodiment, and 111 and 112 are connected in series by metal wiring so as to be in a forward direction. , The storage node 113 is formed. Reference numeral 114 denotes a transfer transistor that permits or inhibits access to the storage node 113.

As shown in FIG. 12, an SOI substrate 115 (Silicon on Insul) made of p-type silicon is used.
, a first device isolation film 116A, a second device isolation film 116B, a third device isolation film 116C, and a fourth device isolation film 116D made of silicon oxide, which are spaced apart from each other by a predetermined distance. Is formed.

In the multiple negative resistance element 111, the SOI
First and second element isolation films 116A, 116A, 1B on substrate 115
16B, the impurity concentration is 1 × 10 19 cm −3 or more,
Degenerate high concentration p as first conductivity type high concentration semiconductor layer
Type diffusion layer 117A is formed, and the film thickness is
A first layer made of silicon oxynitride having a thickness of 1.0 nm to 2.0 nm;
200 nm in thickness, with the tunnel barrier film 118A interposed
Impurity concentration is 1 × 10¹⁹cm^-3As described above, the second conductivity type
Degenerate high-concentration n-type as high-concentration polycrystalline semiconductor layer of 1
A polysilicon layer 119A is formed, and a first pn connection is formed.
A structure 120A has been formed. On top of that, a membrane
200 nm thick, impurity concentration 1 × 10¹⁹cm^-3More than,
Degenerate high as a high-concentration polycrystalline semiconductor layer of the first conductivity type
A p-type polysilicon layer 121A having a thickness of 200
nm, impurity concentration is 1 × 10¹⁹cm ^-3Above, the second conductive
High concentration as a second high concentration polycrystalline semiconductor layer of the type
Between the n-type polysilicon layer 123A and the n-type polysilicon layer 123A.
Second tunnel made of silicon oxynitride of m to 2.0 nm
P-n connection structure formed with the barrier film 122A interposed therebetween.
Structure 124A is formed. Second pn connection structure 1
24A and the first pn connection structure 120A have a thickness of 1.0.
Third ton made of silicon oxynitride having a thickness of 2.0 nm to 2.0 nm
In series via the tunnel barrier film 125A so as to be in the forward direction.
To form a first stacked structure 126A.

In the multiple negative resistance element 112, the multilayer structure 126B is the multilayer structure 126 of the multiple negative resistance element 111.
It has the same structure as A and is formed between the second and third element isolation films 116B and 116C on the SOI substrate 115.

In the transfer transistor 114, the region between the third and fourth element isolation films 116 C and 116 D on the SOI substrate 115 is formed through a gate insulating film 127 made of silicon oxynitride and having a thickness of 5 nm.
Type polysilicon, impurity concentration 1 × 10 ¹⁹ cm
The thickness at ^-3 is formed a gate electrode 128 of 200 nm, the gate electrode 12 on the SOI substrate 115
Side wall 129 made of silicon oxide on the side surface of No. 8
Is formed, and the gate electrode 1 on the SOI substrate 115 is formed.
An extension region 130 made of a high concentration p-type diffusion layer, a source electrode 131A, and a drain electrode 131B are formed on both sides of the gate electrode 28 in the gate length direction.

On the entire surface of the SOI substrate 115, an interlayer insulating film 132 is deposited. The interlayer insulating film 132 has a high concentration p-type diffusion layer 117A, a high concentration n-type polysilicon layer 123A, a high concentration p-type diffusion layer. On the layer 117B, on the high-concentration n-type polysilicon layer 123B, and on the gate electrode 12
8, source electrode 131A and drain electrode 131B
133 each made of tungsten
Are formed so as to be electrically connected.

Each contact 1 in the interlayer insulating film 132
An aluminum wiring 134A is formed on the high-concentration p-type diffusion layer 117A on the high-concentration n-type polysilicon layer 12A.
An aluminum wiring 134B is formed on the high concentration p-type diffusion layer 117B, an aluminum wiring 134D is formed on the high concentration n-type polysilicon layer 123B, and an aluminum wiring 134E is formed on the gate electrode 128. , Source electrode 131A and drain electrode 13
Aluminum wirings 134G and 134F are formed on 1B so as to be electrically connected to each other. Although not shown, the aluminum wiring 134B,
134C and 134F are electrically connected to each other on the interlayer insulating film 132.

Hereinafter, the circuit configuration of the multi-valued SRAM according to the present embodiment will be described with reference to FIG.

In FIG. 13, bit line 201 is
Bit line 2 corresponding to the aluminum wiring 134G shown in FIG.
The transistor connected to 01 corresponds to the transfer transistor 114 in FIG. 12, and the word line 202 corresponds to the aluminum wiring 134E on the gate electrode 128.

The storage node 113 for holding the charge serving as the data to be recorded is connected to the multiple negative resistance element 11 shown in FIG.
2 corresponds to the high-concentration p-type diffusion layer 117B in FIG. 2 and is electrically connected to the high-concentration n-type polysilicon layer 123A in the multiple negative resistance element 111 and the drain electrode 131B of the transfer transistor 114 by aluminum wiring as described above. ing.

As described above, the multiple negative resistance element 111 has the laminated structure 126A, and the power supply voltage line 203 is formed of the aluminum wiring 134 on the high concentration p-type diffusion layer 117A.
Corresponds to A. On the other hand, multiple negative resistance element 112 has a laminated structure 126B, and ground line 204 corresponds to aluminum wiring 134D on high-concentration n-type polysilicon layer 123B.

Although not shown in FIG. 12, the potential of the substrate 135 of the transfer transistor 114 is set to the aluminum wiring 134A, that is, the power supply voltage line 203.
Is set to the same potential as.

Hereinafter, the operation of the semiconductor device according to the present embodiment configured as shown in FIG. 12 as a multi-valued SRAM will be described with reference to FIG. In FIG. 14, the horizontal axis represents the voltage applied to the high-concentration p-type diffusion layer 117A or 117B, and the vertical axis represents the current flowing through the high-concentration p-type diffusion layer 117B. That is, the horizontal axis and the vertical axis indicate the multiple negative resistance elements 11.
1 and 112 respectively show the voltage and current applied in the forward direction.

First, the characteristic curve 301 of the multiple negative resistance element 112 shows a multiple negative resistance characteristic having two peaks as described in the first embodiment. On the other hand, the characteristic curve 302 of the multiple negative resistance element 111 used as a load similarly shows a multiple negative resistance characteristic having two peaks. At this time, the voltage applied in the forward direction to the series connection circuit of the multiple negative resistance elements 111 and 112, that is, the voltage of the aluminum wiring 134A that is the power supply voltage line 203 is selected within an appropriate range, so that the multiple negative resistance is selected. Characteristic curve 301 of element 112
Can be controlled so as to have more intersections with the characteristic curve 302 of the multiple negative resistance element 111 used as a load. In the present embodiment in which multiple negative resistance elements having two peak current values are connected in series, the power supply voltage is set to 0.7 to 1.0.
By setting between V, a maximum of five intersections is obtained.

The characteristic curve 301 of the multiple negative resistance element 112
Of the intersections between the load and the characteristic curve 302 of the load multiple negative resistance element 111, at each intersection, only the intersection where the sign of each of the characteristic curves 301 and 302 is positive is a stable point. Here, of the five intersections 303 to 307, three intersections 303, 305, and 307 are stable points. On the other hand, since the intersections 304 and 306 are in the negative resistance region of each characteristic curve, the slopes of the curves representing the resistances are both negative, and are unstable points.

Among the stable points, the stable point 303 having the lowest voltage value is defined as low data VL, the stable point 305 having an intermediate voltage value is defined as middle data VM, and the stable point 307 having the highest voltage value is defined as high data VL. I will call it VH. The potential of the storage node 113 is stabilized only at one of the low data VL, the middle data VM, and the high data VH. Therefore, this circuit operates stably as a ternary memory of low data VL, middle data VM, and high data VH.

Data writing is performed by preparing predetermined data on the bit line 201 and grounding the word line 202. On the other hand, data read is performed on bit line 2
01 is floating and the word line 202 is grounded.

FIGS. 15A and 15B show examples of the multilevel memory according to the present embodiment and a conventional cell layout, respectively. As shown in FIGS. 15A and 15B, a memory cell using a multiple negative resistance element 403 having two current peaks and having a multilayer structure according to the present embodiment has a single pn connection structure. Compared with a conventional memory cell in which the negative resistance elements 401 are arranged in a plane, the number of elements constituting the memory cell can be reduced and the memory cell area can be reduced. Further, in the present embodiment, the memory cell is configured by using a multiple negative resistance element having two peak currents.
By configuring a memory cell using multiple negative resistance elements having more peak currents, the effects of reducing the number of memory cell components and the cell area can be further increased as compared with the present embodiment. As a result, a multilevel memory suitable for high integration can be formed.

As shown in FIG. 16, as a first modification of the multi-valued memory (SRAM) which is the semiconductor device according to the second embodiment, in the multiple negative resistance element 111 of FIG. The pn connection structure 124A and the first pn connection structure 120A are directed in the forward direction via a third tunnel barrier film 125A made of silicon oxynitride having a thickness of 1.0 to 2.0 nm. Instead of forming the first stacked structure 126A in series with the second pn connection structure 1
24A and the first pn connection structure 120A are connected via a titanium silicide film 501A as an example of a conductive layer having a lower resistance value than the tunnel oxide film to form a first stacked structure 502A, Multiple negative resistance element 1
12, a laminated structure 502B having the same structure and connected via a titanium silicide film 501B is used. Here, the same members as those shown in FIG. 12 are denoted by the same reference numerals, and description thereof will be omitted.

According to the present modification, in addition to the effect of the multiple negative resistance element of the second embodiment, each pn connection structure is connected via titanium silicide having a lower resistance than the tunnel oxide film. Therefore, as described in the modification of the first embodiment, the voltage drop in the portion where each pn connection structure is connected in series via titanium silicide is smaller than that in the case where connection is made via a tunnel oxide film. Because it becomes smaller,
A sufficient voltage can be reliably applied to each pn connection structure, and as a result, an element having a multiple negative resistance characteristic having two peak current values at a lower voltage can be obtained. . Therefore, as shown in FIG.
It is considered that the voltage difference at each stable point becomes large and a multi-valued memory having a large operation margin can be obtained.

As shown in FIG. 18, as a second modification of the multi-valued memory (SRAM) which is the semiconductor device according to the second embodiment, in the multiple negative resistance element 111 of FIG. The pn connection structure 124A and the first pn connection structure 120A are directed in the forward direction via a third tunnel barrier film 125A made of silicon oxynitride having a thickness of 1.0 to 2.0 nm. Instead of forming the first stacked structure 126A in series with the second pn connection structure 1
24A and the first pn connection structure 120A are connected to each other via a silicon germanium layer 701A as an example of a polycrystalline semiconductor layer having a diffusion coefficient lower than that of the polysilicon layer with respect to an additional impurity, thereby forming a first stacked structure. In addition to forming the structure 702A, a multilayer structure 702B having the same structure connected to the multiple negative resistance element 112 via the silicon germanium layer 701B is used. The composition is, for example, Si (1-
x) When expressed as Gex, Si = Ge at a ratio of x = 0.1 to 0.6.
To form a mixed crystal of The film thickness is, for example, 2 to 20 nm. Here, the same members as those shown in FIG. 12 are denoted by the same reference numerals, and description thereof will be omitted.

According to the present modification, the effect of the multiple negative resistance element of the second embodiment can be obtained, and the poly-silicon germanium layer having a lower diffusion coefficient than the polysilicon layer with respect to the additional impurities can be obtained. Since the laminated structure is formed, as described in the modification of the first embodiment, the p-n connection structure can be laminated while suppressing the interdiffusion of impurities and maintaining a high concentration, and the peak current value is high. Good multiple negative resistance characteristics can be obtained. Further, since each pn connection structure is connected via a polycrystalline silicon germanium layer having a lower resistance value than the tunnel oxide film, as described in the modification of the first embodiment, each pn Since the voltage drop at the part where the connection structure is connected in series via the polycrystalline silicon germanium layer is smaller than that when the connection structure is connected via the tunnel oxide film, it is necessary to ensure that a sufficient voltage is applied to each pn connection structure As a result, an element having multiple negative resistance characteristics having two peak current values at a lower voltage can be obtained. Therefore, as also shown in FIG. 17, it is considered that the voltage difference at each stable point becomes large and a multi-valued memory having a large operation margin can be obtained.

As shown in FIG. 18, in the third modification of the multi-valued memory (SRAM) which is the semiconductor device according to the second embodiment, the third element isolation film 1 shown in FIG.
16C, the high-concentration p-type diffusion layer 117B, which is a storage node, and the drain electrode 131B of the transfer transistor 114 are connected so as to be in contact with each other.

According to the present modification, the effect of the multiple negative resistance element in the second embodiment can be obtained, and the high concentration formed by the same conductivity type without forming the third element isolation film 116C. Since the p-type diffusion layer 117B and the drain electrode 131B are formed so as to be in contact with each other, the wiring 134F, the contact, and the element isolation film 116C on the drain electrode 131B in FIG. It can be further reduced. As a result, it is possible to obtain a multi-level memory with a higher degree of integration.

Similarly, the two laminated structures 1 in FIG.
26A, 126B high concentration p-type diffusion layers 117A, 117
B is the drain electrode of the transfer transistor 1
If the storage node is formed in contact with the storage node 31B, the element isolation film 116B in FIG. 19 is not required, so that the cell area of the multilevel memory can be further reduced. As a result, it is possible to obtain a multi-level memory with a higher degree of integration. However, in this case, the laminated structure 126A, 1
It is necessary to further form a high-concentration p-type polysilicon layer on either one of the layers 26B through a tunnel barrier film.

In this embodiment, a p-type transistor is used for the first conductivity type and a p-channel transistor is used for the transfer transistor. It goes without saying that a multi-valued memory can be constructed in which an element is manufactured, an n-channel transistor is manufactured as a transfer transistor, and the polarity of the applied voltage is inverted to operate.

In this embodiment, silicon is mainly used as a material. However, a multi-valued memory can be manufactured by using silicon germanium or silicon germanium carbon. As described above, when the high-concentration p-type semiconductor layer is formed of silicon germanium or silicon germanium carbon, a high-concentration p-type semiconductor layer can be formed as compared with the case where the high-concentration p-type semiconductor layer is formed of silicon. Pn connection structure can be formed, and a multiple negative resistance element having a high peak current can be obtained. As a result, a multi-value memory having a large operation margin can be obtained.

(Third Embodiment) Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

FIGS. 20 (a) to (d) and FIGS. 21 (e) to
(H), FIGS. 22 (i) and (j) are cross-sectional views in the order of steps showing a method for manufacturing a multi-level memory (SRAM) which is a semiconductor device according to the third embodiment of the present invention. First, FIG.
As shown in the figure, after performing element isolation using a selective oxidation method or the like on a semiconductor substrate having p-type Si with a thickness of 300 nm or less as an SOI layer, using thermal oxidation or the like over the entire surface of the semiconductor substrate, A sacrificial oxide film made of silicon oxide with a thickness of about 10 nm
Form 801. Next, a resist pattern 802 having an opening in the laminated structure forming region is formed by using ordinary photolithography. Thereafter, using the resist pattern as a mask, ion implantation is performed using boron ions (B) at an implantation energy of 20 to 40 keV and at a dose of ² to 8 × 10 ¹⁵ cm ⁻² through the sacrificial oxide film 801 in a nitrogen atmosphere. Medium heat treatment at 900 ° C. is applied for 30 minutes to form degenerate high-concentration p-type diffusion layers 117A and 117B having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ or more only on the semiconductor substrates in the stacked structure forming regions 111 and 112, respectively. .

Next, after removing the resist pattern 802 using oxygen plasma or the like, the semiconductor substrate is treated with hydrogen fluoride.
After dipping in a solution containing (HF) and etching the sacrificial oxide film 801 and the natural oxide film to expose the high-concentration p-type diffusion layers 117A and 117B in the stacked structure forming regions 111 and 112, FIG.
As shown in (b), it is made of silicon oxynitride and has a film thickness of about
A furnace temperature of 700 ° C. is applied to the first tunnel barrier film 803 of 1.0 to 2.0 nm,
LPCV using ammonia and dichlorosilane as reactive gas species
Formed by the D method or the like. Subsequently, the polysilicon film (D) is doped over the entire surface of the first tunnel barrier film 803 by vapor phase diffusion of phosphorus (P) using a phosphine gas.
(PS) is deposited by 50 to 200 nm by LPCVD. Thereafter, a heat treatment at 950 ° C. in a nitrogen atmosphere is applied for 30 minutes, so that the impurity concentration is 1 × 10
A degenerated first high-concentration n-type polysilicon layer 804 having a size of ¹⁹ cm ⁻³ or more is formed over the entire surface of the semiconductor substrate.

Next, hydrogen fluoride (H
F), a natural oxide film or the like is etched over the entire surface of the semiconductor substrate to expose the first high-concentration n-type polysilicon layer 804. Then, as shown in FIG.
A second tunnel barrier film 805 made of silicon oxynitride and having a thickness of about 1.0 to 2.0 nm is formed by an LPCVD method using a furnace temperature of 700 ° C. and ammonia and dichlorosilane as reactive gas species.
Subsequently, after polysilicon having a thickness of 50 to 200 nm is deposited over the entire second tunnel barrier film 805, ion implantation using B ions is performed over the entire surface of the polysilicon, and a heat treatment at 900 ° C. in a nitrogen atmosphere is performed. For 30 minutes to form a degenerated high-concentration p-type polysilicon layer 806 having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ or more over the entire surface of the semiconductor substrate.

Next, hydrogen fluoride (H
F), a natural oxide film is etched over the entire surface of the semiconductor substrate, and a high-concentration p-type polysilicon layer is formed.
After exposing 806, as shown in FIG. 20 (d), a third tunnel barrier film 807 made of silicon oxynitride and having a thickness of about 1.0 to 2.0 nm is formed at a furnace temperature of 700 ° C. and a reactant gas species of ammonia. And an LPCVD method using dichlorosilane. Subsequently, the polysilicon film (DPS) is subjected to LPCVD by 50 to 200 n by doping by vapor phase diffusion of phosphorus (P) using a phosphine gas over the entire third tunnel barrier film 807.
m is deposited. After that, a heat treatment at 950 ° C. is performed in a nitrogen atmosphere for 30 minutes to form a degenerated second high-concentration n-type polysilicon layer 808 having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ or more over the entire surface of the semiconductor substrate. Thereafter, a resist pattern 809 is formed on the second high-concentration n-type polysilicon layer 808 using normal photolithography to mask only the electrode region of the stacked structure.

Next, using the resist pattern 809 as a mask, a second high-concentration n-type polysilicon layer, a third tunnel barrier film, a high-concentration p-type polysilicon layer, a second tunnel barrier film, Dry etching is performed on the concentration n-type polysilicon layer. At this time, by using emission spectroscopy or the like utilizing the difference in the constituent elements of the tunnel barrier film and the polysilicon film to be etched, it is detected that the etching of the polysilicon film is completely completed, and the tunnel barrier film is etched. When the etching is performed, the stacked film can be efficiently etched by changing the type of the etching gas to, for example, a fluorine-based gas such as CF ₄ . Note that the etching gas of the polysilicon can suppress the side etching so deposited on the side wall due to the relatively low vapor pressure of the reaction product The use of chlorine or bromine-based gas, for example, Cl ₂ and HBr, etc., good Etching shape can be obtained. In addition, by using the tunnel barrier film as an etching marker and by completing the etching at the time when the polysilicon has been etched by the number of times of stacking the tunnel barrier film (three times in the present embodiment), the etching can be surely performed. The stacked structure can be etched. As a result, as shown in FIG. 21E, the p-n
Laminated structures 126A and 126B in which connection structures are connected in series via a tunnel barrier film are formed before forming a transistor. Since the formed laminated structure has been subjected to sufficient high-temperature heat treatment, it is possible to realize recovery from damage such as crystal defects due to ion implantation and to improve the crystallinity of polysilicon, and additionally, it has been activated in the high-concentration semiconductor layer. Since the number of impurities increases and the carrier concentration increases, a multiple negative resistance element having a high peak current value and good multiple negative resistance characteristics can be formed.

Next, a film thickness of 200 to 800 is formed on the entire surface of the semiconductor substrate so as to completely cover the laminated structures 126A and 126B.
After depositing a silicon oxide film 810 nm, a resist pattern (not shown) having an opening in a transistor formation region
Then, dry etching is performed on the silicon oxide film 810 to expose the semiconductor substrate 135 in the transistor formation region 114 as shown in FIG.

Next, as shown in FIG. 21 (g), a silicon oxide or silicon oxynitride film having a thickness of 1.3 to 5.0 nm is formed on the semiconductor substrate 135 in the open transistor formation region by thermal oxidation or the like. The gate insulating film 811 is formed.
Subsequently, the polysilicon film (DPS) was subjected to LPC while doping by vapor phase diffusion of phosphorus (P) using phosphine gas.
After depositing 50 to 200 nm of polysilicon by VD method or depositing polysilicon of 50 to 200 nm in thickness, ion implantation using P ions or As ions is performed over the entire surface of the polysilicon to perform high concentration n-type polysilicon. Form a layer. afterwards,
900 ° C ~ 1000 in nitrogen atmosphere to activate impurities
A rapid heat treatment at a temperature of ° C. for 15 seconds or less is applied to form a degenerated high-concentration n-type polysilicon layer 812 having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ or more over the entire surface of the semiconductor substrate. After that, a resist pattern 813 is formed on the high-concentration n-type polysilicon layer 812 so as to serve as a mask in the gate electrode region.

Next, dry etching is performed on the high-concentration n-type polysilicon layer 812 using the resist pattern 813 as a mask, as shown in FIG.
A gate electrode 128 made of n-type polysilicon is formed on 135 via a gate insulating film 127. Then, the gate electrode 1
The source / drain extension regions 130 of the transistor having an impurity concentration of 10 ¹⁸ cm ⁻³ or more are formed by ion implantation using P ions or the like with 28 as a mask.

Next, as shown in FIG. 22 (i), a silicon oxide film (not shown) is
A side wall 129 made of silicon oxide is formed on the side surface of the gate electrode by depositing a film having a thickness of about 400 nm and etching back the silicon oxide film. Thereafter, ion implantation using As ions or the like is performed using the gate
The source electrode 131A and the drain electrode 131B made of a degenerated high-concentration n-type diffusion layer having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ or more by a rapid heat treatment at a temperature of 0 ° C. to 1000 ° C. for 15 seconds or less.
To form

Next, as shown in FIG. 22J, a silicon oxide film having a thickness of 200 to 800 nm is deposited so as to cover the transistor formed over the entire surface of the semiconductor substrate.
Form 132. Then, using normal lithography, the high concentration p-type diffusion layer 117 on the interlayer insulating film 132
A, 117B, above the n-type polysilicon layer 123A, 123B, above the gate electrode 128, and above the source electrode 131A and the drain electrode 131B to form a resist pattern (not shown) having an opening, respectively, Next, using the resist pattern as a mask, dry etching is performed on the interlayer insulating film 132 to form a high-concentration p-type diffusion layer 117 on the interlayer insulating film 132.
A and 117B, the upper surfaces of the n-type polysilicon layers 123A and 123B, the upper surface of the gate electrode 128, and the contact holes exposing the upper surfaces of the source electrode 131A and the drain electrode 131B, respectively. W) is filled to form contacts 133, respectively.
After that, each contact 133 on the upper surface of the interlayer insulating film 132
High concentration p-type diffusion layers 117A, 117B, or n-type polysilicon layers 123A, 123B, or a gate electrode 128, or a source electrode 1
Aluminum wirings 134A to 134G electrically connected to 31A and drain electrode 131B are formed, respectively. In addition,
Although not shown, the substrate (body) of the transistor 135
Is connected to the aluminum wiring through another contact, and the transfer transistor is completed. According to the present embodiment, since the transfer transistor is formed after forming the multilayer structure of the multiple negative resistance elements, a heat treatment process at a high temperature for a long time to obtain good multiple negative resistance characteristics when forming the multilayer structure is performed. I will not receive it,
Deterioration of transistor characteristics caused by impurity diffusion in a heat treatment process at a high temperature for a long time does not occur, so that a transfer transistor having designed transistor characteristics can be formed. Note that the transistor may be formed using any generation rule as long as the steps for forming the transistor are comparable to or higher than the high-temperature heat treatment process for forming the stacked structure.

Thereafter, although not shown, when performing multilayer wiring, another interlayer insulating film is formed again on the interlayer insulating film and wiring is performed. When performing flattening,
It may be performed using a mechanical polishing (CMP) process or the like. Thereafter, annealing is performed at 400 ° C. to 500 ° C. in a nitrogen atmosphere of 5 to 10% of hydrogen to reduce the contact resistance and reduce the level of the interface between the tunnel barrier film of the stacked structure and the gate insulating film of the transistor. Finally, a protective insulating film is formed on the surface of the interlayer insulating film, and an opening for a bonding pad is provided to complete a multilevel memory.

According to the present embodiment, the multiple negative resistance elements and the transistor can be formed on the same semiconductor substrate without deteriorating the characteristics of each other. As a result, a stacked structure having a high peak current value and good multi-negative resistance characteristics can be formed, so that a multi-value memory having a large operation margin and operating stably can be obtained. On the other hand, since the transfer transistor also has the designed transistor characteristics, it is possible to obtain a multi-valued memory capable of performing data input / output control exactly as designed, particularly at the operation speed.

As a first modification of the third embodiment, as shown in FIG.
Instead of forming the stacked structures 126A and 126B by connecting the -n connection structures in series via a tunnel barrier film, as shown in FIG. As an example of the semiconductor layer, for example, a silicon germanium layer 814 is deposited by using an LPCVD method or the like, and a degenerated high-concentration p-type polysilicon layer 806 is formed on the silicon germanium layer 814 in the same manner as in FIG. Formed over the entire surface. Subsequent steps are the same as those in the third embodiment, but in the dry etching of the laminated structure, the tunnel barrier film is used as an etching marker and the number of times the tunnel barrier film is laminated (the first modification of this embodiment) By ending the etching only when the etching of the polysilicon layer or the polysilicon layer including the silicon germanium layer is completed (only twice in the example), the stacked structure can be surely etched.
As a result, the pn connection structure via the tunnel barrier film is changed to the stacked structures 702A, 702B via the silicon germanium layer 814.
To form When the composition of the silicon germanium layer 814 is expressed as, for example, Si (1-x) Gex, a mixed crystal of Si and Ge is formed at a ratio of x = 0.1 to 0.6 so as to have a film thickness of 2 to 20 nm. . Here, the same members as those shown in FIG. 20 are denoted by the same reference numerals, and description thereof will be omitted.

According to this modification, the effect of the multi-level memory of the third embodiment can be obtained, and the laminated structure is provided via a polycrystalline silicon germanium layer having a diffusion coefficient lower than that of the polysilicon layer for added impurities. Is formed, as described in the modification of the first embodiment, the pn connection structure can be stacked while suppressing the interdiffusion of impurities and maintaining a high concentration, and a favorable peak current value is high. Multiple negative resistance characteristics can be obtained. Further, since each pn connection structure is connected via a polycrystalline silicon germanium layer having a lower resistance value than the tunnel oxide film, as described in the modification of the first embodiment, each pn Since the voltage drop at the part where the connection structure is connected in series via the polycrystalline silicon germanium layer is smaller than that when the connection structure is connected via the tunnel oxide film, it is necessary to ensure that a sufficient voltage is applied to each pn connection structure As a result, an element having multiple negative resistance characteristics having two peak current values at a lower voltage can be obtained. Therefore, it is considered that the voltage difference at each stable point becomes large and a multi-valued memory having a large operation margin can be obtained.

In the present embodiment, a ternary memory composed of two stacked structures in which two pn connection structures are connected in series via a tunnel barrier film on a semiconductor substrate via a tunnel barrier film is used. Although an example of the manufacturing method has been described, a similar process is added to increase the number of times of stacking the pn connection structure via the tunnel barrier film via the tunnel barrier film.
Further, it is easy to form a memory that can handle multiple values. In that case, it is conceivable that dry etching becomes difficult due to an increase in the height of the stacked structure. Therefore, it is preferable to reduce the thickness of each of the p-type polysilicon layer and the n-type polysilicon layer forming the stacked structure. .

Further, in this embodiment, the high-concentration p-type diffusion layer is formed on the semiconductor substrate and the n-type polysilicon layer is formed with the tunnel barrier film interposed therebetween. It goes without saying that a multi-valued memory that operates by reversing the type and the n-type and reversing the polarity of the applied voltage can be configured.

[0096]

According to the first semiconductor device of the present invention, since at least two degenerate high-concentration pn connection structures sandwiching the tunnel barrier film are connected in series via the tunnel barrier film, An element having multiple negative resistance characteristics having two or more peak current values can be obtained. Also,
Since the high-concentration n-type semiconductor layer and the high-concentration p-type semiconductor layer are made of polycrystalline material, the depleted high-concentration p
It can be manufactured by stacking -n connection structures. This makes it possible to form a multiple negative resistance element suitable for high integration by reducing the element area to 以下 or less as compared with the case where the elements are arranged in a plane.

Further, in the first semiconductor device, since silicon, silicon germanium, or silicon germanium carbon is used for the high-concentration semiconductor layer, a degenerate high-concentration pn connection structure can be surely formed, and a tunnel is formed. Since the barrier film is made of silicon oxide, silicon nitride, or silicon oxynitride, a tunnel barrier film through which a tunnel current flows between the degenerated high-concentration pn connection structures can be reliably formed. In particular, high concentration p
When the type semiconductor layer is formed of silicon germanium or silicon germanium carbon, a p-type semiconductor layer having a higher concentration can be formed as compared with the case of silicon, so that a pn connection structure having a steep concentration gradient is more reliably formed. As a result, a multiple negative resistance element having a high peak current can be obtained.

According to the second semiconductor device of the present invention,
Since the degenerate high-concentration pn connection structure sandwiching the tunnel barrier film is connected in series via a conductive layer having a lower resistance value than the tunnel barrier film, two or more peak current values can be obtained at a lower voltage. An element having multiple negative resistance characteristics can be obtained. In addition, since the high-concentration n-type semiconductor layer and the high-concentration p-type semiconductor layer are made of polycrystal, it is possible to form a stacked structure of a degenerated high-concentration pn connection structure with a tunnel barrier film interposed therebetween. This makes it possible to form a multiple negative resistance element suitable for high integration by reducing the element area to 以下 or less as compared with the case where the elements are arranged in a plane.

Further, since the second semiconductor device uses silicon, silicon germanium, or silicon germanium carbon for the high-concentration semiconductor layer similarly to the first semiconductor device, it has a degenerated high-concentration pn connection structure. Since the tunnel barrier film can be formed reliably and the tunnel barrier film is made of silicon oxide, silicon nitride, or silicon oxynitride, a tunnel barrier film through which a tunnel current flows between the degenerated high-concentration pn connection structures is reliably formed. Can be. In particular, when the high-concentration p-type semiconductor layer is formed of silicon germanium or silicon-germanium carbon, a p-type semiconductor layer having a higher concentration can be formed as compared with the case where silicon is formed of silicon.
The n-connection structure can be formed more reliably, and as a result, a multiple negative resistance element having a high peak current can be obtained.

According to the third semiconductor device of the present invention, the degenerated high-concentration pn connection structure sandwiching the tunnel barrier film is connected in series via the semiconductor layer having a lower resistance than the tunnel barrier film. Therefore, an element having a multiple negative resistance characteristic having two or more peak current values at a lower voltage can be obtained. In addition, since the semiconductor layer has a lower diffusion coefficient with respect to the added impurity than the high-concentration n-type semiconductor layer and the high-concentration p-type semiconductor layer, it is difficult to directly join the high-concentration n-type semiconductor layer and the high-concentration p-type semiconductor layer. In comparison, mutual diffusion of impurities can be suppressed, and a junction in which the concentration gradient changes steeply can be formed. Further, since the semiconductor layer is more thermally stable than a conductive layer such as a metal or a metal silicide, the degree of freedom in temperature in a manufacturing process is increased. Further, since the high-concentration n-type semiconductor layer, the high-concentration p-type semiconductor layer, and the semiconductor layer are made of polycrystalline material, it is possible to laminate the degenerate high-concentration pn connection structure sandwiching the tunnel barrier film. In this case, the element area can be reduced to 以下 or less as compared with the case of arranging them in a plane.

According to the fourth semiconductor device of the present invention,
Two multi-negative resistance elements having the same structure are connected in series in the same direction to form a multi-valued ballast circuit, and the voltage of the storage node can be controlled by a transistor connected to the storage node. Can be formed.
In addition, since a multi-negative resistance element is formed using a stacked structure of a degenerated polycrystalline high-concentration pn connection structure with a tunnel barrier film interposed therebetween, a memory cell is required to be formed side by side in a plane. The number of constituent elements can be reduced, and the area of the memory cell can be reduced to half or less. As a result, a multilevel memory suitable for high integration can be formed.

In the fourth semiconductor device, when forming a laminated structure forming two multiple negative resistance elements in a memory cell, at least two high-concentration pn connection structures sandwiching a tunnel barrier film are formed. When connected in series in a forward direction via a tunnel barrier film, the pn connection structure can be stacked while suppressing the interdiffusion of impurities and maintaining a high concentration, and a good multiple negative resistance characteristic having a high peak current value can be obtained. be able to. Thereby, the operation margin of the multi-valued memory is increased, and a multi-valued memory that operates stably can be obtained.

Further, in the fourth semiconductor device, each pn is connected via a conductive layer having a lower resistance than the tunnel oxide film.
Since the connection structure is connected, the voltage drop at the part connected in series via the conductive layer is smaller than that when the connection is made via the tunnel oxide film, so that each pn connection structure ensures a sufficient voltage. As a result, an element having a multiple negative resistance characteristic having two peak current values at a lower voltage can be obtained. Thus, it is considered that the voltage difference between the stable points becomes large, and a multi-valued memory having a large operation margin can be obtained.

In the fourth semiconductor device, when forming the first stacked structure and the second stacked structure, a tunnel barrier is formed between the high-concentration n-type polycrystalline semiconductor layer and the high-concentration p-type polycrystalline semiconductor layer. At least two pn connection structures sandwiching the film are connected in series in the forward direction to a high concentration n-type polycrystalline semiconductor layer and a polycrystalline material having a lower diffusion coefficient than the high concentration p-type polycrystalline semiconductor layer. Connected via a semiconductor layer
Compared to a case where a high-concentration n-type semiconductor layer and a high-concentration p-type semiconductor layer are directly joined, a p-n connection structure can be stacked while maintaining a high concentration by suppressing mutual diffusion of impurities, and the peak current value is high. Since multi-negative resistance characteristics can be obtained, the operation margin of the multi-level memory is increased. In addition, the polycrystalline semiconductor layer has a lower resistance value than the tunnel barrier film, so that the voltage drop at the connection portion is smaller, and the multi-negative resistance has a lower voltage and two or more peak current values. Since the characteristics can be obtained, the difference between the voltages at the respective stable points increases, and a multi-valued memory that operates stably with a large operation margin can be obtained. Further, since the semiconductor layer is more thermally stable than a conductive layer such as a metal or a metal silicide, the degree of freedom in temperature in a manufacturing process is increased.

In the fourth semiconductor device, a drain electrode and an element isolation film of a p-channel transistor, which is a transfer transistor in which a high-concentration p-type diffusion layer at one end of the stacked structure is formed of the same conductivity type, are formed. Since they are formed so as to be in contact with each other, a wiring, a contact, and an element isolation region for connecting the high-concentration p-type diffusion layer and the drain electrode of the p-channel transistor are not required, so that the cell area of the multilevel memory is further reduced. be able to. as a result,
Further, a multi-level memory with a high degree of integration can be obtained.

Similarly, in the fourth semiconductor device, the high-concentration n-type semiconductor layer, which is one end of the laminated structure, has the same conductivity type as n.
Since the wiring is formed so as to be in contact with the drain electrode of the channel transistor, a wiring, a contact, and an element isolation region are not required, so that the cell size of the multilevel memory can be reduced. As a result, it is possible to obtain a multi-level memory with a higher degree of integration.

Further, in the fourth semiconductor device, since the SOI substrate having the buried oxide film provided in parallel with the main surface inside the semiconductor substrate is used, the buried oxide film allows the SOI substrate to be perpendicular to the main surface of the substrate. Element isolation is reliably formed in any direction.

Further, the fourth semiconductor device comprises the first and second semiconductor devices.
As in the case of the semiconductor device described above, since silicon, silicon germanium, or silicon germanium carbon is used for the high-concentration semiconductor layer, a degenerated high-concentration pn connection structure can be reliably formed, and the tunnel barrier film is formed of silicon oxide. Alternatively, since it is made of silicon nitride or silicon oxynitride, a tunnel barrier film in which a tunnel current flows between the degenerated high-concentration pn connection structures can be surely formed. In particular, when the high-concentration p-type semiconductor layer is formed of silicon germanium or silicon-germanium carbon, a p-type semiconductor layer having a higher concentration can be formed as compared with a case where the high-concentration p-type semiconductor layer is formed of silicon. An n-connection structure can be formed, and a multiple negative resistance element having a high peak current can be obtained. As a result, a multi-value memory having a large operation margin can be obtained.

According to the first method of manufacturing a semiconductor device according to the present invention, since the transistor is formed after the entire laminated structure is formed, the high-temperature heat treatment process required for the step of forming the degenerate high-concentration semiconductor layer of the laminated structure is performed. As a result, the transistor characteristics are not deteriorated, and the transistor characteristics as designed can be obtained. On the other hand, since the stacked structure can be sufficiently subjected to a high-temperature heat treatment, the number of activated impurities in the high-concentration semiconductor layer increases and the carrier concentration increases, resulting in a good multi-negative resistance characteristic having a high peak current value. Can be obtained. As a result, the operation margin of the multi-level memory is increased, and more stable operation is possible.

According to the second method of manufacturing a semiconductor device according to the present invention, since the transistor is formed after the entire laminated structure is formed, the high-temperature heat treatment process required for the step of forming the depleted high-concentration semiconductor layer of the laminated structure is performed. As a result, the transistor characteristics are not deteriorated, and the transistor characteristics as designed can be obtained. On the other hand, since the stacked structure can be sufficiently subjected to a high-temperature heat treatment, the number of activated impurities in the high-concentration semiconductor layer increases and the carrier concentration increases, resulting in a good multi-negative resistance characteristic having a high peak current value. Can be obtained. In addition, since the semiconductor layer made of a polycrystalline material has a lower resistance value than the tunnel barrier film, the voltage drop at the connection portion is smaller, and the multi-negative resistance characteristic has a lower voltage and two or more peak current values. , The difference between the voltages at each stable point increases. As a result of these,
A multi-valued memory having a large operation margin and stable operation can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration sectional view showing a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a voltage-current characteristic diagram of one pn connection structure according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram of the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a voltage-current characteristic diagram of the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a voltage-current characteristic diagram for explaining the operation of the semiconductor device according to the first embodiment of the present invention;

FIG. 6 is a voltage-current characteristic diagram of the semiconductor device according to the first embodiment of the present invention;

FIG. 7 is a plan view showing a layout example of a conventional semiconductor device.

FIG. 8 is a plan view showing a layout example of the semiconductor device according to the first embodiment of the present invention;

FIG. 9 is a configuration sectional view showing a semiconductor device according to a first modification of the first embodiment of the present invention;

FIG. 10 is a comparison diagram of the voltage-current characteristics of the semiconductor device according to the first modification of the first embodiment of the present invention and the voltage-current characteristics of the semiconductor device according to the first embodiment of the present invention;

FIG. 11 is a sectional view showing a configuration of a semiconductor device according to a second modification of the first embodiment of the present invention;

FIG. 12 is a configuration sectional view showing a semiconductor device according to a second embodiment of the present invention;

FIG. 13 is a circuit diagram of a semiconductor device according to a second embodiment of the present invention.

FIG. 14 is a voltage-current characteristic diagram illustrating the operation of the semiconductor device according to the second embodiment of the present invention.

15A is a plan view showing a layout example of a conventional semiconductor device, and FIG. 15B is a plan view showing a layout example of a semiconductor device according to a second embodiment of the present invention.

FIG. 16 is a sectional view showing a configuration of a semiconductor device according to a first modification of the second embodiment of the present invention;

FIG. 17 is a voltage-current characteristic diagram comparing operations of the semiconductor device according to the first modification of the second embodiment of the present invention and the semiconductor device according to the second embodiment;

FIG. 18 is a sectional view showing a configuration of a semiconductor device according to a second modification of the second embodiment of the present invention;

FIG. 19 is a sectional view showing a configuration of a semiconductor device according to a third modification of the second embodiment of the present invention;

20A is a sectional view illustrating a method of manufacturing a semiconductor device according to a third embodiment of the present invention, and FIG. 20B is a sectional view illustrating the method of manufacturing a semiconductor device according to the third embodiment of the present invention. (C) Step-by-step cross-sectional view showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention (d) Step-by-step cross-sectional view showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention

FIG. 21E is a step-by-step cross-sectional view showing a method of manufacturing a semiconductor device according to the third embodiment of the present invention. (F) Step order showing a method of manufacturing a semiconductor device according to the third embodiment of the present invention. (G) Step-by-step cross-sectional view showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention (h) Step-by-step cross-sectional view showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention

FIG. 22 (i) is a process order sectional view showing a method for manufacturing a semiconductor device according to a third embodiment of the present invention, and (j) is a process order showing a method for manufacturing a semiconductor device according to the third embodiment of the present invention. Sectional view

FIG. 23 is a process sectional view illustrating the method of manufacturing the semiconductor device according to the first modified example of the third embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 11 silicon oxide film 12 p-type polysilicon layer (high-concentration p-type semiconductor layer) 13 n-type polysilicon layer (high-concentration n-type semiconductor layer) 14 tunnel barrier film 15 pn connection structure 16 pn connection structure (p 17 (on n-connection structure 15) 17 Stacked structure 18 Interlayer insulating film 19 Contact 20 Aluminum wiring

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Ryo Morimoto 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F-term (reference) 5F083 AD70 GA05 GA09 HA02 JA35 JA36 JA39 NA08 PR33 PR36 ZA21

Claims (19)

[Claims] 1. A degenerate high-concentration n-type semiconductor layer in which a Fermi level is located in a conduction band, a degenerate high-concentration p-type semiconductor layer in which a Fermi level is located in a valence band, and electrons can tunnel. In a semiconductor device having a tunnel barrier film having a thickness, the high concentration n-type semiconductor layer and the high concentration p
Having a pn connection structure with the tunnel barrier film interposed between the high-concentration n-type semiconductor layers and the high-concentration p-type semiconductor layer.
A semiconductor device, wherein the type semiconductor layer is made of a polycrystalline body. 2. The pn layer having the tunnel barrier film interposed between the high-concentration n-type semiconductor layer and the high-concentration p-type semiconductor layer.
2. The semiconductor device according to claim 1, wherein the connection structure has a structure in which at least two connection structures are connected in series in the same direction via the tunnel barrier film. 3. The high-concentration n-type semiconductor layer and the high-concentration p-type semiconductor layer are made of silicon, silicon germanium, or silicon germanium carbon, and the tunnel barrier film is made of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The semiconductor device according to claim 1, wherein: 4. A degenerated high-concentration n-type semiconductor layer in which a Fermi level is located in a conduction band, a degenerated high-concentration p-type semiconductor layer in which a Fermi level is located in a valence band, and electrons can tunnel. In a semiconductor device including a tunnel barrier film having a thickness and a conductive layer having a lower resistance than the tunnel barrier film, the high-concentration n-type semiconductor layer and the high-concentration p-type semiconductor layer are made of a polycrystalline material, A pn connection structure sandwiching the tunnel barrier film between the high-concentration n-type semiconductor layer and the high-concentration p-type semiconductor layer has at least two layers via the conductive layer.
A semiconductor device having a structure connected in series in the same direction. 5. The high-concentration n-type semiconductor layer and the high-concentration p-type semiconductor layer are made of silicon, silicon germanium, or silicon germanium carbon, and the tunnel barrier film is made of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. 5. The semiconductor device according to claim 4, wherein said conductive layer is made of metal or metal silicide. 6. A degenerated high-concentration n-type semiconductor layer in which a Fermi level is located in a conduction band, a degenerated high-concentration p-type semiconductor layer in which a Fermi level is located in a valence band, and electrons can tunnel. A semiconductor device comprising: a tunnel barrier film having a thickness; and a semiconductor layer having a diffusion coefficient lower than that of the high-concentration n-type semiconductor layer and the high-concentration p-type semiconductor layer with respect to additional impurities. Layer and said high concentration p
The semiconductor layer and the semiconductor layer are made of a polycrystalline body, and a pn connection structure in which the tunnel barrier film is interposed between the high-concentration n-type semiconductor layer and the high-concentration p-type semiconductor layer has the semiconductor layer interposed therebetween. A semiconductor device having a structure in which at least two are connected in series in the same direction. 7. The high-concentration n-type semiconductor layer and the high-concentration p-type semiconductor layer are made of silicon, the tunnel barrier film is made of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, and the semiconductor layer is made of silicon. 7. The semiconductor device according to claim 6, comprising germanium or silicon germanium carbon. 8. A semiconductor substrate, a first-conductivity-type high-concentration semiconductor layer and a first second-conductivity-type high-concentration polycrystalline semiconductor layer formed on the semiconductor substrate with a first tunnel barrier film interposed therebetween. A second tunnel barrier film is formed between the first conductive type high-concentration polycrystalline semiconductor layer and the second second conductive type high-concentration polycrystalline semiconductor layer on the formed first pn connection structure. The second formed by sandwiching
A first stacked structure in which at least one pn connection structure is connected in series in the same direction, a second stacked structure having the same structure as the first stacked structure, and a transistor, The high-concentration semiconductor layer of the first conductivity type, which is one end of the stacked structure, is connected to a power supply voltage line, and the second high-concentration polycrystalline semiconductor layer of the second conductivity type, which is one end of the second stacked structure, A second conductive type high-concentration polycrystalline semiconductor layer that is connected to a ground line and is one end of the first stacked structure; and a first conductive type high-concentration polycrystalline semiconductor layer that is one end of the second stacked structure. The semiconductor layer is connected to form a storage node, the storage node is connected to a drain of a transistor, the gate of the transistor is connected to a word line, the source is connected to a bit line, and the substrate is connected to a ground line. Characteristic semiconductor device. 9. The first laminated structure and the second laminated structure, wherein the second pn connection structure is formed on the first pn connection structure at least via a third tunnel barrier film. 9. The semiconductor device according to claim 8, wherein the semiconductor device has a structure in which one device is connected in series in the same direction. 10. The first laminated structure and the second laminated structure, wherein at least one second pn connection structure is connected in series with the first pn connection structure via the conductive layer. 9. The semiconductor device according to claim 8, wherein the semiconductor device has a structure connected in the same direction. 11. The first stacked structure and the second stacked structure are formed on the first pn connection structure via the semiconductor layer in which the second pn connection structure is made of polycrystal. 9. The semiconductor device according to claim 8, wherein the semiconductor device has at least one structure connected in series in the same direction. 12. The high-concentration p-type transistor, wherein the first conductivity type high-concentration semiconductor layer at one end of the first stacked structure is a high-concentration p-type semiconductor layer. The semiconductor device according to claim 8, wherein the semiconductor layer is formed so as to be in contact with a drain of the transistor. 13. The high-concentration n-type transistor, wherein the transistor is an n-channel transistor, the first conductivity type high-concentration semiconductor layer at one end of the first stacked structure is a high-concentration n-type semiconductor layer, The semiconductor device according to claim 8, wherein the semiconductor layer is formed so as to be in contact with a drain of the transistor. 14. The semiconductor device according to claim 8, wherein said semiconductor substrate is an SOI substrate. 15. The high-concentration n-type polycrystalline semiconductor layer and the high-concentration p-type polycrystalline semiconductor layer are made of silicon, silicon germanium, or silicon germanium carbon, and the tunnel barrier film is a silicon oxide film, a silicon nitride film, or a silicon nitride film. 15. The semiconductor device according to claim 8, wherein the semiconductor device is made of an oxynitride film, the conductive layer is made of metal or metal silicide, and the semiconductor layer is made of silicon germanium or silicon germanium carbon. 16. A step of forming a first degenerate high-concentration semiconductor layer of a first conductivity type in a stacked structure formation region by masking a transistor formation region on a first conductivity type semiconductor substrate;
Forming a first tunnel barrier film over the entire surface of the semiconductor substrate so that a tunnel current flows; and forming a second high-concentration polycrystalline second conductivity type over the entire surface of the first tunnel barrier film. Forming a semiconductor layer so as to degenerate; forming a second tunnel barrier film over the entire surface of the second high-concentration polycrystalline semiconductor layer such that a tunnel current flows therethrough; Forming a third high-concentration polycrystalline semiconductor layer of the first conductivity type so as to degenerate over the entire surface of the barrier film; and forming a third tunnel over the entire surface of the third high-concentration polycrystalline semiconductor layer. Forming a barrier film so that a tunnel current flows; and forming a second film over the entire surface of the third tunnel barrier film.
Forming a conductive type fourth high-concentration polycrystalline semiconductor layer so as to degenerate; and masking the electrode formation region of the laminated structure, forming the second high-concentration polycrystalline semiconductor layer and a second tunnel barrier film. Forming an electrode having a laminated structure on the semiconductor substrate by etching the third high-concentration polycrystalline semiconductor layer, the third tunnel barrier film, and the fourth high-concentration polycrystalline semiconductor layer. After depositing a first insulating film over the entire surface of the semiconductor substrate, etching the first insulating film using the stacked structure forming region as a mask, thereby opening the transistor forming region. Forming a second insulating film over the entire surface of the opened transistor formation region, forming a conductor film over the entire semiconductor substrate, and masking the gate electrode formation region of the transistor. Forming a gate insulating film in the transistor formation region and a gate electrode on the gate insulating film by etching the insulating film and the conductive film, respectively; and forming a second conductive type on the semiconductor substrate. By performing ion implantation using the gate electrode as a mask by using the impurity ions, a second conductive type diffusion layer as a source and a drain of a transistor is formed on the semiconductor substrate on the gate length direction side of the gate electrode. Forming a third insulating film over the entire surface of the semiconductor substrate and forming the third insulating film so as to protect the opened transistor formation region. Method. 17. The high-concentration polycrystalline semiconductor layer of the first conductivity type and the high-concentration polycrystalline semiconductor layer of the second conductivity type are made of silicon, silicon germanium, or silicon germanium carbon, and the tunnel barrier film is made of silicon. 17. The method for manufacturing a semiconductor device according to claim 16, comprising an oxide film, a silicon nitride film, or a silicon oxynitride film. 18. A step of forming a first degenerate high-concentration semiconductor layer of a first conductivity type in a stacked structure formation region by masking a transistor formation region on a first conductivity type semiconductor substrate;
Forming a first tunnel barrier film over the entire surface of the semiconductor substrate so that a tunnel current flows; and forming a second high-concentration polycrystalline second conductivity type over the entire surface of the first tunnel barrier film. Forming a semiconductor layer so as to degenerate, and a semiconductor having a lower diffusion coefficient for added impurities than the second high-concentration polycrystalline semiconductor layer over the entire surface of the second high-concentration polycrystalline semiconductor layer. Forming a layer, and forming a first high-concentration third high-concentration polycrystalline semiconductor layer over the entire surface of the semiconductor layer so as to degenerate; Forming a second tunnel barrier film over the entire surface so that a tunnel current flows, and degenerating a fourth high-concentration polycrystalline semiconductor layer of the second conductivity type over the entire surface of the second tunnel barrier film. To form The second high-concentration polycrystalline semiconductor layer, the semiconductor layer, the third high-concentration polycrystalline semiconductor layer, the second tunnel barrier film, and the fourth high-concentration polycrystalline semiconductor layer by masking the electrode formation region of the stacked structure. Forming a stacked structure electrode on the semiconductor substrate by etching the concentration polycrystalline semiconductor layer; and depositing a first insulating film over the entire surface of the semiconductor substrate, and then forming the stacked structure Opening the transistor formation region by etching the first insulation film while masking the region, and forming a second insulation film over the entire opening of the transistor formation region; By forming a conductive film over the entire surface of the substrate and etching the second insulating film and the conductive film while masking a gate electrode formation region of the transistor, the transistor is formed. Forming a gate insulating film on the gate insulating film and a gate electrode on the gate insulating film, and performing ion implantation on the semiconductor substrate using impurity ions of a second conductivity type using the gate electrode as a mask. Forming a second conductive type diffusion layer as a source and a drain of a transistor on the semiconductor substrate on the gate length direction side of the gate electrode, and forming a third insulating layer over the entire surface of the semiconductor substrate. Depositing a film and forming the film to protect the opened transistor formation region. 19. The high-concentration n-type polycrystalline semiconductor layer and the high-concentration p-type polycrystalline semiconductor layer are made of silicon, and the tunnel barrier film is made of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. 19. The method according to claim 18, wherein the semiconductor layer having a low diffusion coefficient is made of silicon germanium or silicon germanium carbon.