JP2002261192A - Wafer level CSP - Google Patents

Abstract

(57) [Summary] (with correction) [PROBLEMS] To provide a thin CSP that can be assembled at a wafer level. SOLUTION: By using the side surface of a through hole formed at a specific location on a scribe line of a wafer, electrical connection between the front and back of the wafer is made, and an electrode for mounting a substrate is arranged on the back surface of the wafer. The through hole is formed by half-etching the scribe line of the wafer to form a recess and then polishing the back surface of the wafer until the bottom of the recess disappears.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a small package for housing a semiconductor device.

[0002]

2. Description of the Related Art There is a great need for smaller and lighter electronic portable devices such as mobile phones and digital cameras, and smaller, thinner and lighter electronic components are required for electronic devices. At present, small packages such as BGA and CSP are applied to small portable electronic devices, and it is expected that a chip-scale ultra-small package that can be mounted on a bare chip or assembled at a wafer level will be introduced in the future. In particular, CSP chip size packages formed at the wafer level or chip scale packages are BGA, CSP
It has the same level of reliability and is easier to handle than bare chips, so it is attracting attention as a next-generation package.

FIG. 5 shows a cross-sectional structure of a typical wafer level CSP. The manufacturing method is manufactured by the following process. After the wafer process is completed, the semiconductor substrate 15 is ground to about 500 μm by back grinding, a protective film 17 such as polyimide is formed on the semiconductor substrate 15, and the electrode pads 16 and other necessary parts are opened. Next, a copper redistribution layer 18 is formed by plating, and the electrodes are rearranged in an array. Copper posts 19 are formed by plating to form electrodes for external connection, and then the mold resin 20 is sealed. Finally, a bump electrode 21 for mounting the substrate is formed by a ball mounter or screen printing. Conventionally, wafer-level CSP has been manufactured by the above method.

[0004]

However, in the wafer level CSP, it is necessary to form a copper post in order to form an electrode for external connection. Copper post
It is necessary to completely expose the copper on the post surface in order to connect to the bump electrode or the mounting board.However, the copper post is plated and formed, causing variations in the post. There is a problem that the joining reliability is reduced. In addition, in order to absorb the variation of the posts, it is necessary to make the transfer pressure of the molding device highly accurate and to use a special film, which causes a problem that the manufacturing cost of the package increases. In addition, the copper post causes the flow resistance of the mold resin, and the resin does not spread evenly on the wafer surface, causing unfilled resin, which causes a problem of lowering the assembly yield.

[0005] Further, since the bump electrode for bonding the substrate is formed on the copper post on the mold resin sealing side, the bump electrode cannot be formed by electrolytic plating, but is formed by ball mounting or screen printing. Therefore, it is difficult to form a narrow pitch bump electrode of 100 μm or less.

[0006] The wafer level CSP of the present invention has a structure in which electrodes for substrate bonding are formed on the back surface of the wafer and no copper posts are used. In addition, since there is no substrate mounting electrode on the mold sealing surface, all of the above problems can be solved.

[0007]

SUMMARY OF THE INVENTION Wafer level C of the present invention
SP has a substrate mounting electrode on the back side of the wafer, and its structure is realized by making electrical connection between the front and back of the wafer using the side of the through hole formed at a specific location on the scribe line . The through-hole is formed by polishing the back surface of the concave portion obtained by half-etching the scribe line on the silicon substrate using back grinding.

[0008]

According to the above-mentioned means, since there is no electrode for connecting the substrate on the side of the semiconductor circuit to be resin-sealed, there is no need to form a copper post, and there is no need to use a special film. The flow resistance of the resin due to the post is also eliminated, and the unfilling failure at the time of molding is eliminated. In addition, since there is no electrode for connecting the substrate on the mold sealing surface, the bump can be formed by an electroplating method in addition to a solder ball mount and a screen printing method, and a bump corresponding to a narrow pitch of 100 μm or less can be formed.

[0009]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a top view showing a first embodiment of the present invention, and FIGS. 2 to 4 are sectional views. The structure of the wafer level CSP of the first embodiment will be described with reference to the drawings.

As shown in FIG. 2A, the wafer after the formation of the semiconductor circuit used for the package assembly has an electrode pad 2 formed on a semiconductor substrate 1 and a protective film such as silicon nitride on the electrode pad 2. 3 is formed in a portion except on the electrode pad 2 and the scribe line 4.

In the first step, as shown in FIG. 2B, a half-etched portion 5 is selectively wet-etched at a specific portion of the scribe line area to form a concave portion having a depth of about 50 to 100 μm.

Next, as shown in FIG. 2C, an insulating film 6 of polyimide or the like is formed on the entire surface of the wafer, and as shown in FIG. 2D, the electrode pads 2 and the half-etched portions 5 on the scribe lines are selected. And make it open.

Next, after a copper film having a thickness of 2000 to 5000 mm is formed by sputtering, a resist 7 is patterned into a desired shape as shown in FIG. A metal wiring layer 8 of about 50 μm of copper, aluminum or the like is formed by plating, and an insulating layer 9 of polyimide or the like is formed over the entire surface as necessary.

Next, as shown in FIG. 3C, a mold resin 10 having a thickness of about 30 μm to 100 μm is transferred to the semiconductor circuit by transfer molding or potting for the purpose of protecting the semiconductor circuit, handling the package, and improving heat dissipation. Seal the entire side.

Next, as shown in FIG. 3D, the silicon substrate 1 is back ground to a thickness of 20 μm to 200 μm according to the mounting application.

Next, as shown in FIG.
After forming an insulating film 11 such as polyimide on the ground surface of
FIG. 4B illustrates patterning into a desired shape. Next, after a metal film such as copper is formed on the entire back surface of the wafer by a method such as sputtering, resist patterning is performed, and an electrode pad 12 having a thickness of about 10 to 50 μm is formed on the semiconductor substrate 1 as shown in FIG. Is formed on the back surface by plating or the like.

Finally, as shown in FIG. 5, the center of the scribe line is diced with a margin of about 50% of the scribe width to make a package. With the above-described method, a wafer-level package having the mounting electrode pads 12 on the back surface of the semiconductor substrate 1 can be provided.

Next, a second embodiment of the present invention will be described. FIG. 6 is a sectional view showing a second embodiment of the present invention. An electrode pad 2 is formed on a part of the surface of the semiconductor substrate 1, a protective film 3 is formed around the electrode pad 2, an insulating film 6 is formed on the protective film 3, and an insulating film 9 is formed on the uppermost layer. I have. An insulating film 11 and an electrode pad are formed on a part of the back surface of the semiconductor substrate 1. As shown in FIG.
In the embodiment of the present invention, the structure does not perform molding resin sealing.
The thickness of the package can be reduced to 100um or less, and it can be used for applications such as IC cards.

Next, a third embodiment of the present invention will be described. FIG. 7 is a sectional view showing a third embodiment of the present invention. As shown in FIG. 7, in the third embodiment, the bump electrodes 13 can be formed on the mounting electrode pads on the back surface of the wafer by a ball mounting method, a screen printing method, or an electrolytic plating method. Enable. At this time, if the insulating film formed on the back surface of the wafer is used as a buffer material 14 such as an elastomer, the stress between the mounting substrate and the bumps is absorbed, and the reliability at the time of mounting is improved.

[0020]

According to the wafer level CSP of the present invention, there is no need to form a copper post for forming an electrode for external connection, and an improved molding device for absorbing the variation of the post and the use of a special film are used. There is no need to
The manufacturing cost of the package can be reduced. Since there is no copper post, the mold resin spreads evenly on the wafer surface without receiving flow resistance, so that no resin is filled, and the assembly yield is improved. In addition, since there is no bump for substrate bonding on the mold resin sealing surface side, bumps can be formed by electrolytic plating.
It is possible to form a narrow pitch bump electrode of 100 μm or less.

[Brief description of the drawings]

FIG. 1 is a top view of a semiconductor device according to a first embodiment.

FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment.

FIG. 3 is a cross-sectional view of the semiconductor device according to the first embodiment.

FIG. 4 is a sectional view of the semiconductor device according to the first embodiment;

FIG. 5 is a sectional view of the semiconductor device according to the first embodiment;

FIG. 6 is a sectional view of a semiconductor device according to a second embodiment.

FIG. 7 is a sectional view of a semiconductor device according to a third embodiment.

FIG. 8 is a sectional view of a conventional wafer level CSP.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Electrode pad 3 ... Protective film 4 ... Scribe area 5 ... Half-etched location 6 ... .... Insulating film 7 ... Resist 8 ... Metal wiring layer 9 ... Insulating layer 10 ... Mold resin 11 ... Insulating film 12 ... Electrode pad 13 ... Bump electrode 14 ... Buffer material 15 ... Semiconductor substrate 16 ... Electrode pad 17 ... Protective film 18 ... Rewiring Layer 19: Copper post 20: Mold resin 21: Bump electrode

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Claims (8)

[Claims] 1. A wafer level CSP having an electrode for bonding a substrate on a back surface of a semiconductor substrate. 2. The wafer level CSP according to claim 1, wherein the electrode is electrically connected to an electrode of a semiconductor circuit through a side surface of the through hole. 3. The wafer level C according to claim 2, wherein the through hole is in a scribe line.
SP. 4. The wafer-level CSP according to claim 2, wherein the through-hole is formed by back-grinding a concave portion formed by a method such as etching by back grinding. 5. The wafer level CSP according to claim 2, wherein a film formed on a side surface of the through hole has a two-layer structure of an insulating film and a metal film. 6. The wafer level CSP according to claim 2, wherein the through hole is in an active region of the semiconductor substrate. 7. The wafer-level CSP according to claim 2, wherein the through-hole is formed by back-grinding a concave portion formed by a method such as etching by back grinding. 8. The wafer level CSP according to claim 2, wherein a film formed on a side surface of the through hole has a two-layer structure of an insulating film and a metal film.