JP2002260991A - Fine resist pattern, method of forming fine pattern, and semiconductor device - Google Patents

Abstract

(57) Abstract: A fine resist pattern, a method for forming a fine pattern, and a semiconductor device capable of forming a finer pattern on the surface of a semiconductor device are provided. A step of forming a resist layer (9) on a substrate (6), which is in contact with a specific gas containing a specific element and bonds with the specific element to enhance resistance to a predetermined etching gas, Performing a first exposure 10 on the layer 9 to form a first exposure area 9b and a first non-exposure area 9a; and performing a second exposure 11 on the first exposure area 9b, Second exposure area 9c and third exposure area 9d
A step of exposing the resist layer 9 to a specific gas to bond only the third exposed region 9d to a specific element; and forming the second exposed region 9c and the first non-exposed region 9a Removing by etching to form a resist pattern composed of the third exposed region 9e.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fine resist pattern, a method for forming a fine pattern, and a semiconductor device, and more particularly, to a fine resist pattern and a fine pattern for forming a fine memory holding pattern in the manufacture of a semiconductor device. The present invention relates to a method and a semiconductor device.

[0002]

2. Description of the Related Art A conventional method for forming a fine pattern, that is, a method for forming a cylindrical pattern when manufacturing a semiconductor device will be described with reference to FIG. 5A to 5D are schematic cross-sectional views showing a semiconductor device in each step in a conventional method for forming a resist pattern. It should be noted that, in the figure, illustration of an activation region connected to the cylindrical pattern 5 is omitted for simplicity.

First, as shown in FIG. 1A, an exposure, development and etching process is performed. That is, first, the resist 2 is applied on the substrate 1. After that, exposure, development,
Etching is performed to form a concave portion in the resist 2.
Thus, the exposure, development, and etching steps of the semiconductor device are completed.

Next, as shown in FIG. 1B, a polysilicon film forming step is performed. That is, in the semiconductor device after the exposure, development, and etching steps, the polysilicon film 3 is formed on the surface of the resist 2 having the concave portion. Thus, the step of forming the polysilicon film of the semiconductor device is completed.

Next, as shown in FIG. 1C, an oxide film forming step is performed. That is, in the semiconductor device after the polysilicon film forming step, an oxide film 4 is further formed on the resist 2 on which the polysilicon film 3 is formed. Thus, the oxide film forming step of the semiconductor device is completed.

Finally, as shown in FIG. 1D, an etch back step is performed. That is, in the semiconductor device after the oxide film forming step, the entire surface of the resist 2 on which the polysilicon film 3 and the oxide film 4 are formed is etched back,
The polysilicon film 3 and the oxide film 4 in the region other than the concave portion are removed. Then, a desired cylindrical pattern 5 of the polysilicon film 3a is formed. As a result, all the steps for forming the fine pattern of the semiconductor device are completed.

[0007]

In recent years, demands for higher integration of semiconductor devices have been increasing more and more with advances in technology. There is a similar demand for a semiconductor device related to memory retention, and a semiconductor device capable of securing a large memory retention capacity in a small volume has been actively developed. That is, the memory holding pattern formed on the semiconductor device needs to be an extremely fine pattern.

However, in the above-mentioned conventional technology,
It was difficult to form an extremely fine pattern. That is, if the resolution is improved by changing the light beam wavelength or the lens numerical aperture of the exposed portion, a finer concave portion can be formed in the exposure, development, and etching steps. However, there is a technically difficult problem in forming a polysilicon film or an oxide film at a constant quality in the fine concave portion in the film forming process. And, the finer the concave portion, the greater the problem to overcome.

The present invention has been made in order to solve the above-mentioned problems, and a fine resist pattern capable of forming a finer pattern on the surface of a semiconductor device without going through a complicated film forming process. It is an object to provide a method for forming a fine pattern and a semiconductor device.

[0010]

Means for Solving the Problems The inventor of the present invention has conducted studies for solving the above problems, and as a result, has come to know the following matters. That is, as a resist applied on the substrate,
A resist having a copolymer in which a hydroxyl group of polyvinyl phenol is protected by a t-butoxycarbonyl group (t-BOC group) and an acetal group is used as a main polymer. This resist has the following three chemical modes depending on the amount of exposure to the resist surface.

First, a first mode is a case where a high exposure amount is exposed on the surface of the above-described resist. In this case, the resist is not cross-linked (silylated) even if the resist is cross-linked by exposure to a gas containing silicon (Si) as a specific element.

Next, the second mode is a case where the surface of the resist is exposed with a medium exposure amount. In this case, when the resist is deprotected without being cross-linked by exposure, and then comes into contact with a gas containing silicon, the resist is silylated.

[0013] The third embodiment is a case where the surface of the resist is exposed with a low exposure amount (including the case where no exposure is performed at all). In this case, the resist is not deprotected by exposure, does not crosslink, and does not silylate even when subsequently contacted with a silicon-containing gas.

The present invention has been made in order to solve the above-mentioned problems based on the above research results. That is, the method for forming a fine resist pattern according to the first aspect of the present invention comprises: A step of forming a resist layer having a property of contacting with a specific gas containing a specific element and bonding with the specific element and enhancing resistance to a predetermined etching gas; and forming a resist pattern on the resist layer in a first pattern. Performing one exposure, a step of forming a first exposure area that has received the first exposure and a first non-exposure area that does not receive the first exposure, from the outer edge of the first exposure area A second exposure is performed on the first exposure region with a second pattern reduced at a predetermined interval, and a second exposure region that has undergone the second exposure in the first exposure region and A third exposure area that does not receive a second exposure Forming, exposing the resist layer to a specific gas containing the specific element, and bonding only the third exposed region to the specific element, and forming the second exposed region and the first Removing the non-exposed area by etching to form a resist pattern comprising the third exposed area.

According to a second aspect of the present invention, in the method for forming a fine resist pattern according to the first aspect, the resist layer is protected by an acetal group and a t-butoxycarbonyl group. It was formed from a polymer.

According to a third aspect of the present invention, there is provided a method of forming a fine resist pattern according to the first or second aspect of the present invention, wherein the specific element is silicon.

Further, the method of forming a fine resist pattern according to the invention of claim 4 is the above-mentioned claim 1 to claim 3.
In the invention described in any one of the above, the predetermined etching gas is oxygen gas.

Further, the method of forming a fine resist pattern according to the invention of claim 5 provides the method of forming a fine resist pattern according to claims 1 to 4 above.
In the invention according to any one of the above, the resist pattern comprising the third exposure region is formed in a circular shape, a rectangular shape, a line-and-space shape, or a cross shape.

A semiconductor device according to a sixth aspect of the present invention is manufactured by the method for forming a fine resist pattern according to any one of the first to fifth aspects.

Further, in the method for forming a fine pattern according to the present invention, a step of forming a layer to be processed on a substrate and a step of forming a first resist layer on the layer to be processed are provided. Step, a second resist layer having a property of being in contact with a specific gas containing a specific element and bonding with the specific element to enhance resistance to a predetermined etching gas on the first resist layer And forming a first exposure on the second resist layer in a first pattern,
Forming a first exposure area that has received the first exposure and a first non-exposure area that does not receive the first exposure; and a step of reducing at a predetermined interval from an outer edge of the first exposure area. Perform a second exposure on the first exposure area in a second pattern,
Forming a second exposure area of the first exposure area that has undergone the second exposure and a third exposure area that does not receive the second exposure, and the second resist layer Exposing the third exposed region only to the specific element by exposing to the specific gas containing the specific element, and exposing the first resist layer by removing the first non-exposed region by etching Forming a region and removing the exposed region of the first resist layer by etching to form a first exposed region of the processed layer, and etching a second exposed region of the second resist layer Forming an exposed region of the first resist layer by removing the first exposed region of the layer to be processed by a constant thickness etching, etching the exposed region of the first resist layer Before removal by Forming a second exposed region of the layer to be processed, and using the third exposed region of the second resist layer as a mask, removing the first exposed region of the layer to be processed by etching; Forming a pattern of the layer to be processed by etching while leaving a second exposed region of the layer with a predetermined thickness.

In the method for forming a fine pattern according to the present invention, the second resist layer is protected by an acetal group and a t-butoxycarbonyl group. It was formed from the polymer obtained.

According to a ninth aspect of the present invention, in the method of forming a fine pattern, the specific element is silicon in the seventh or eighth aspect of the invention.

According to a tenth aspect of the present invention, there is provided a method for forming a fine pattern according to any one of the seventh to ninth aspects, wherein the predetermined etching gas is oxygen gas. is there.

In the method for forming a fine pattern according to the present invention, the pattern of the layer to be processed may be circular or rectangular. , A line and space shape or a cross shape.

A semiconductor device according to a twelfth aspect of the present invention is manufactured by the method for forming a fine pattern according to any one of the seventh to eleventh aspects.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, Embodiment 1 of the present invention will be described in detail with reference to the drawings. Figure 1
FIGS. 3A to 3J are schematic cross-sectional views illustrating a semiconductor device in each step in a method for forming a fine pattern according to the first embodiment of the present invention. It should be noted that in the figure, illustration of an activation region connected to the fine pattern 7b is omitted for simplicity.

First, as shown in FIG. 1A, a laminating step is performed. That is, first, the processed layer 7 is formed on the substrate 6. Here, for example, the substrate 6 is made of SiO ₂ and functions as an interlayer film of the semiconductor device. On the other hand, the processing target layer 7 is made of polysilicon and functions as a processing target substrate of the semiconductor device. Then, on the substrate 6, the layer to be processed 7 is
It is preferable to form a film with a thickness of about 0.5 μm.

Next, after a lower resist 8 as a first resist layer is applied on the layer 7 to be processed, this is thermally crosslinked. Here, as the lower layer resist 8, for example, a novolak resist (for example, an i-line resist PFI-38 manufactured by Sumitomo Chemical Co., Ltd.) can be used as a material. Further, the thickness of the lower resist 2 at this time is preferably about 0.4 μm by so-called spin coating, in which case thermal crosslinking can be achieved at a temperature of 200 to 300 ° C. .

Next, an upper resist 9 as a second resist layer is applied on the lower resist 8. Here, as described above, the upper layer resist 9 is a silylated resist that bonds to silicon in a silicon-containing gas under a certain condition. This silylated resist is obtained, for example, by adding a phenolic hydroxyl group of a polyvinylphenol-based polymer to t-BO.
A polymer protected by a C group and an acetal group is used as a main polymer. The polymer is further dissolved in a solvent such as PGMEA to form an acid generator (eg, Triphenylsulfonium t
riflate). Then, it is preferable to form this silylated resist on the lower resist 8 as a thin film of 0.03 to 0.07 μm by spin coating.

Thus, the lamination process of the semiconductor device is completed. The lower resist 8 is heat-treated at a high temperature after the application step, as described above. Therefore, the upper-layer resist 9 applied thereafter is preferably applied without being mixed with the lower-layer resist 8.

Next, as shown in FIG. 1B, a first exposure step is performed. That is, in the semiconductor device after the laminating step, the first exposure 10 is performed in the first pattern on the surface of the upper resist 9 of the semiconductor device. And the first exposure 10
Then, an upper resist first region 9b as a first exposure region receiving the first exposure and an upper resist non-first region 9a as a first non-exposure region not receiving the first exposure 10 are formed.

Here, for the first exposure 10, a light source capable of irradiating high energy such as ultraviolet rays, X-rays, and electron beams can be used. For example, an argon fluoride excimer laser (ArF excimer laser) is used as a light source. In this case, the irradiation amount of the first exposure 10 is preferably set to 3 to 8 mJ / cm ² . It should be noted that a first mask having a predetermined opening corresponding to the first pattern is provided in an unillustrated exposure portion for performing the first exposure 10. In the first embodiment, a mask having a rectangular opening is used as the first mask, and the shape of the opening can be, for example, 0.9 μm in length × 1.9 μm in width.

In this manner, the upper resist first region 9b which has received the first exposure 10 is decomposed (deprotected) by the medium exposure amount. That is, in the upper resist 9, the chemical properties of the upper resist first region 9 b in the decomposed state by the first exposure 10 and the upper resist non-first region 9 a in the decomposed state without receiving the first exposure 10 are different. Two different regions occur. Thus, the first exposure process of the semiconductor device ends.

Next, as shown in FIG. 1C, a second exposure step is performed. That is, in the semiconductor device after the first exposure step, the second exposure 11 is performed in the second pattern on the upper resist first region 9b, and the heat treatment is performed at 110 to 130 ° C. for about 1 minute. In the upper resist first region 9b, the upper resist second region 9c as a second exposure region receiving the second exposure 11, and the upper resist as a third exposure region not receiving the second exposure 11 A third region 9d is formed.

Here, in the second exposure step, when the above-mentioned ArF excimer laser is used as a light source, the irradiation amount is preferably set to 100 to 300 mJ / cm ² . That is, the exposure amount of the second exposure 11 in the second exposure step is larger than the exposure amount of the first exposure 10 in the above-described first exposure step. The second exposure 11
A second mask having a predetermined opening corresponding to the second pattern is set in the exposure unit performing the above. In the first embodiment, a mask having a rectangular opening is used as the second mask, and the shape of the opening can be, for example, 0.7 μm × 1.7 μm. That is, the upper resist second region 9c is reduced at a predetermined interval from the outer edge of the upper resist first region 9a.

In this way, the upper resist second region 9c which has received the second exposure 11 is crosslinked by the large exposure. That is, the second exposure 11
The upper resist second region 9c cross-linked by the above, the upper resist third region 9d decomposed by receiving only the first exposure 10 and not receiving the second exposure 11, the first exposure 10 and the second exposure 11
Therefore, three regions having different chemical properties from the upper resist non-first region 9a which is not crosslinked or decomposed without any of the above are generated. Thereby, the second exposure process of the semiconductor device ends.

Next, as shown in FIG. 1 (D), a silylation step is performed. That is, the semiconductor device after the second exposure step is exposed to a silicon-containing gas as a specific gas. Here, as the silicon-containing gas, for example,
Dimethylsilyldimethylamine (DMSDMA) can be used. Note that the symbol Si in FIG. 1D indicates a silicon-containing gas, in which the exposed surface of the semiconductor device is in contact with the silicon-containing gas.

Then, by contact with the silicon-containing gas, only the upper resist third region 9d is silylated, thereby forming the upper resist pattern 9e.
That is, medium exposure 1 without large exposure 11
Upper resist third region 9 which is in a decomposed state by receiving only 0
Only d will take in silicon in that region due to the chemical reaction between the phenolic hydroxyl groups and DMSDMA. The upper resist non-first region 9a that has not been exposed at all and the crosslinked upper resist second region 9c do not take in silicon. In this way,
The silylation process of the semiconductor device ends.

Next, as shown in FIG. 1E, a third exposure step is performed. That is, in the semiconductor device after the silylation process, the entire region of the upper resist 9, that is,
Upper resist non-first area 9a and upper resist second area 9
c and the upper resist pattern 9e, the third exposure 1
Do 2 Then, by performing the heat treatment, the upper resist non-first region 9a is decomposed. Here, the third exposure 12
For example, when the above-described ArF excimer laser is used as a light source, the irradiation amount is preferably set to 3 to 8 mJ / cm ² . Thus, the third exposure step of the semiconductor device is completed.

Next, as shown in FIG. 1F, a first removal step is performed. That is, in the semiconductor device after the third exposure step, the upper resist non-first region 9a decomposed in the third exposure step is removed by etching. And
An exposed region of the lower resist 8 is formed.

Here, as the etching removing method in the first removing step, for example, a wet developing method using an alkali developing solution can be used. Thus, the upper resist non-first region 9a is dissolved and removed. On the contrary,
Since the upper resist second region 9c is cross-linked, it does not dissolve in the alkaline developer. Also, the upper resist pattern 9e is not dissolved in the alkali developing solution because it is silylated. Thus, the first removing step of the semiconductor device is completed.

Next, as shown in FIG. 1G, a second removal step is performed. That is, in the semiconductor device after the first removing step, the upper resist second region 9c and the exposed region in the lower resist 8 are removed by etching. Thus, only the upper resist pattern 9e remains in the upper resist 9. Then, as for the lower resist 8, the lower resist third region 8a and the lower resist second region 8b as an exposed region remain. And about the to-be-processed layer 7, a 1st exposure area | region is formed in a non-first area | region.

Here, as a removing method in the second removing step, for example, an etching (dry development) method using oxygen plasma can be used. In this case, since the upper resist pattern 9e is silylated and has enhanced resistance to oxygen gas as a predetermined etching gas, the upper resist pattern 9e is not etched away even when subjected to oxygen plasma processing. On the other hand, the lower resist of the non-first region is etched away by the oxygen plasma treatment, and the non-silylated upper resist second region 9c is also removed by the oxygen plasma treatment. The etching processing conditions include, for example, an etching apparatus TCP-9400 manufactured by Lam Research.
When using, a processing time of about 15 seconds is required under the conditions of a maximum output of 200 W and a minimum output of 5 W. Thus, the second removing step of the semiconductor device is completed.

Next, as shown in FIG. 1H, a third removing step is performed. That is, in the semiconductor device after the second removing step, the processed layer 7 in the non-first region, which is the exposed region, is formed by the desired film thickness L1 using the lower resist second region 8b and the upper resist pattern 9e as an etching mask. By etching and removing, the remaining layer 7a to be processed is formed. Here, for example, the processed layer 7 formed of polysilicon
Is 0.5 μm, it is preferable that the thickness L1 of the layer 7 to be removed be about 0.05 μm. Thus, the third removing step of the semiconductor device is completed.

Next, as shown in FIG. 1I, a fourth removing step is performed. That is, in the semiconductor device after the third removing step, only the lower resist second region 8b is removed by etching. Then, a second exposed region of the processed layer remaining portion 7a is formed. Here, as the removing method in the fourth removing step, for example, the above-described etching method using oxygen plasma can be used. Thus, the fourth removing step of the semiconductor device is completed.

Next, as shown in FIG. 1J, a fifth removing step is performed. That is, in the semiconductor device after the fourth removing step, the processed layer 7
Is removed by etching. That is, using the upper resist pattern 9e as a mask, the entire processed layer 7 in the non-first region as the first exposed region is etched away. Then, with respect to the processed layer 7 in the second region as the second exposed region, the remaining portion is etched away except the desired film thickness L2. Here, the thickness L2 of the processed layer 7 in the remaining second region is substantially equal to the thickness L1 of the processed layer 7 removed in the above-described third removal step. Thus, the fifth removal step of the semiconductor device is completed, and the desired fine pattern 7b of the layer to be processed is formed.

As described above, in the method for forming a fine pattern and the semiconductor device configured as in the first embodiment, the step of forming the polysilicon film is not performed after the formation of the fine pattern 7b. After laminating a polysilicon film as a layer to be processed 7 on a substrate 6 in advance, a resist layer of a lower resist 8 and an upper resist 9 is laminated.
Then, the upper resist 9 has a high exposure amount of the second exposure 11.
Is performed, a crosslinked upper resist second region 9c is formed, and the region finally functions as a positive resist without silylation. On the other hand, the first exposure 10
Is performed, a deprotected upper resist first region 9b is formed, and then the region is silylated to function as a negative resist. Further, a first exposure 10 and a second exposure 11
In the upper resist non-first region 9a where the above-mentioned process is not performed, the region functions as a positive resist without being silylated thereafter. By performing a plurality of exposure steps and a plurality of removal steps using the chemical properties of the upper resist 9, an extremely fine pattern can be formed on the surface of the semiconductor device.

In the first embodiment, the substrate 6
In the semiconductor device having the processed layer 7, the lower resist 8, and the upper resist 9 formed thereon, a fine pattern of the processed layer 7 was formed. Separately from this, in a semiconductor device in which only the upper resist 9 as a resist layer is formed on the substrate 6, after performing the same steps as FIGS. 1A to 1D in the first embodiment, the upper resist is removed. By performing the step of etching and removing the first region 9a and the upper resist second region 9c, a fine resist pattern of the resist layer can be formed.

Embodiment 2 Hereinafter, a second embodiment of the present invention will be described in detail with reference to the drawings. FIG.
(C) is a schematic diagram showing a method for forming a fine pattern according to the second embodiment of the present invention; In the present second embodiment, the first mask 20 and the second mask 2
The shape 1 and the shape of the fine pattern 25 formed on the semiconductor device are different from those of the first embodiment. That is, while the opening shape of the first mask and the like in the first embodiment is rectangular, the opening shape of the first mask and the like in the second embodiment is circular. In the second embodiment, as in the first embodiment, a fine pattern 25 of a layer to be processed is formed on a semiconductor device through a plurality of exposure steps, removal steps, and the like.

Hereinafter, the relationship between the first mask 20, the second mask 21, and the fine pattern 25 will be described in detail with reference to FIGS. First, FIG. 1A is a schematic diagram showing a first mask 20 used in a first exposure step. The first mask 20 is provided with a first mask opening 20a having a circular opening having a diameter D1. Then, light corresponding to the first exposure is emitted from the light source toward the first mask 20. This light source light passes through only the first mask opening 20a and irradiates the upper resist surface of the semiconductor device via the projection lens. Thus, the diameter d is formed on the upper resist in accordance with the magnification of the projection lens.
A first upper resist first region is formed.

FIG. 5B is a schematic view showing a second mask 21 used in the second exposure step. The second mask 21 has a second mask opening 21a having a circular opening having a diameter D2. Here, the diameter D2 of the second mask opening 21a is formed smaller than the diameter D1 of the first mask opening 20a. Then, light corresponding to the second exposure is emitted from the light source toward the second mask 21. This light source light passes through only the second mask opening 21a and irradiates the upper resist surface of the semiconductor device. Thus, an upper resist second region having a diameter d2 is formed on the upper resist.

Finally, FIG. 3C is a schematic diagram showing a fine pattern 25 formed on the semiconductor device. After the first exposure step using the first mask 20 and the second exposure step using the second mask 21, the third exposure step and a plurality of removal steps are performed as in the first embodiment. As a result, the semiconductor device finally has an outer diameter d indicated by oblique lines in FIG.
1. A fine pattern 25 having a convex portion with an inner diameter d2 is formed.

As described above, in the method for forming a fine pattern configured as in the second embodiment, an extremely fine pattern having a relatively free shape can be formed on a semiconductor device.

Embodiment 3 FIG. Hereinafter, a third embodiment of the present invention will be described in detail with reference to the drawings. FIG.
(C) is a schematic view showing a method for forming a fine pattern according to the third embodiment of the present invention. In the third embodiment, the shapes of the first mask 30 and the second mask 31 and the shape of the fine pattern 35 are different from those of the second embodiment. That is, while the shape of the fine pattern in the second embodiment is circular, the shape of the fine pattern in the third embodiment is a cross. In the third embodiment, as in the second embodiment,
After a plurality of exposure steps, removal steps, and the like, a fine pattern 35 of a layer to be processed is formed on the semiconductor device.

Hereinafter, the relationship between the first mask 30, the second mask 31, and the fine pattern 35 will be described in detail with reference to FIGS. First, FIG. 1A is a schematic view showing a first mask 30 used in a first exposure step. The first mask 30 is provided with a first mask opening 30a having a rectangular opening of M2 × M1. Then, light corresponding to the first exposure is emitted from the light source toward the first mask 30. This light source light passes through only the first mask opening 30a and irradiates the upper resist surface of the semiconductor device via the projection lens. In this way, corresponding to the magnification of the projection lens,
A rectangular upper resist first region having a length of m2 and a width of m1 is formed.

FIG. 7B is a schematic view showing a second mask 31 used in the second exposure step. The second mask 31 has four rectangular second mask openings 31a, 31b, 31c, and 31d in a range of M4 × M3.
It is formed so as to provide a cross-shaped portion at the center thereof. Here, the second mask openings 31a, 31b, 31
The range of length M4 × width M3 of c and 31d is formed smaller than length M2 × width M1 of the first mask opening 30a.
Then, light corresponding to the second exposure is emitted from the light source toward the second mask 31. This light source light passes through the second mask openings 31a, 31b, 31c, 31d,
The upper resist surface of the semiconductor device is irradiated. Thus,
Four rectangular upper resist second regions are formed on the upper resist in a range of m4 × m3.

Finally, FIG. 3C is a schematic diagram showing a fine pattern 35 formed on the semiconductor device. After the first exposure step using the first mask 30 and the second exposure step using the second mask 31, the third exposure step and a plurality of removal steps are performed in the same manner as in the second embodiment. As a result, a fine pattern 35 having a cross-shaped protruding portion therein is finally formed on the semiconductor device as shown by hatching in FIG.

As described above, in the method for forming a fine pattern configured as in the third embodiment, an extremely fine pattern having a relatively free shape can be formed on a semiconductor device.

Embodiment 4 FIG. Hereinafter, a fourth embodiment of the present invention will be described in detail with reference to the drawings. FIG. 4 (A)-
(C) is a schematic view showing a method for forming a fine pattern according to the fourth embodiment of the present invention. In the fourth embodiment, the shapes of the first mask 40 and the second mask 41 and the shape of the fine pattern 45 are different from those of the second embodiment. That is, while the shape of the fine pattern in the second embodiment is circular, the shape of the fine pattern in the fourth embodiment is a line-and-space shape. In the fourth embodiment, as in the second embodiment, a fine pattern 45 of a layer to be processed is formed on a semiconductor device through a plurality of exposure steps, removal steps, and the like.

Hereinafter, the mutual relationship between the first mask 40, the second mask 41, and the fine pattern 45 will be described in detail with reference to FIGS. First, FIG. 1A is a schematic view showing a first mask 40 used in a first exposure step. The first mask 40 is provided with a first mask opening 40a having a rectangular opening of N2 × N1. Then, light corresponding to the first exposure is emitted from the light source toward the first mask 40. This light source light passes through only the first mask opening 40a and irradiates the upper resist surface of the semiconductor device via the projection lens. In this way, corresponding to the magnification of the projection lens,
A rectangular upper layer first region of n2 × n1 is formed.

FIG. 7B is a schematic view showing a second mask 41 used in the second exposure step. The second mask 41 has five rectangular second mask openings 41a, 41b, 41c, 41d, 4d within a range of N2 × N1.
1e are provided at equal intervals. Here, the vertical length of the second mask openings 41a, 41b, 41c, 41d, 41e is N2, and the first mask openings 30a
Is formed equal to the vertical length N2. On the other hand, the second mask openings 41a, 41b, 41c, 41d, 41
Each of the horizontal widths e is formed to be 1/11 of the horizontal length N1 of the first mask opening 30a. Then, light corresponding to the second exposure is emitted from the light source toward the second mask 41. This light source light passes through the second mask openings 41a, 41b, 41c, 41d, and 41e and irradiates the upper resist surface of the semiconductor device. In this way, 5 × 5 in the range of n2 × n1 on the upper resist
Two rectangular upper resist second regions are formed.

Finally, FIG. 3C is a schematic diagram showing a fine pattern 45 formed on the semiconductor device. After the first exposure step using the first mask 40 and the second exposure step using the second mask 41, a third exposure step and a plurality of removal steps are performed as in the second embodiment. As a result, a fine pattern 45 as a line and space having six convex portions is finally formed on the semiconductor device as shown by oblique lines in FIG.

As described above, in the method of forming a fine resist pattern configured as in the fourth embodiment, an extremely fine pattern having a relatively free shape can be formed on a semiconductor device.

In each of the above embodiments, a fine pattern of a semiconductor device is formed by using polysilicon as the layer 7 to be processed. Instead, an organic material as a low dielectric constant material is used as the layer 7 to be processed. (For example, silk made of DuPont). For example, if the first mask is provided with a line-and-space opening and the second mask is provided with a circular opening, a circular recess is provided at the center of the line-and-space protrusion. And a fine pattern made of a low dielectric constant material can be formed.

Further, it is apparent that the present invention is not limited to the above embodiments, and that the embodiments can be appropriately modified within the scope of the technical idea of the present invention. In addition, the number, position, shape, and the like of the constituent members, the procedure of each step, the number of times, and the like are not limited to the above-described embodiments. The procedure of the process, the number of times, etc. can be used.

[0066]

Since the present invention is constructed as described above, it is not necessary to perform the step of forming a polysilicon film or the like after the formation of a fine pattern. It is possible to provide a fine resist pattern capable of forming a simple pattern, a method for forming a fine pattern, and a semiconductor device.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a semiconductor device in each step in a method for forming a fine pattern according to a first embodiment of the present invention.

FIGS. 2A and 2B are schematic views showing (A) a first mask used in a first exposure step and (B) a second mask used in a second exposure step in the method for forming a fine pattern according to the second embodiment of the present invention; 3A and 3B are a schematic diagram showing two masks and a schematic diagram showing a fine pattern formed in a semiconductor device.

FIG. 3 is a schematic diagram showing (A) a first mask used in a first exposure step and (B) a second mask used in a second exposure step in the method for forming a fine pattern according to the third embodiment of the present invention; 3A and 3B are a schematic diagram showing two masks and a schematic diagram showing a fine pattern formed in a semiconductor device.

FIG. 4 is a schematic diagram illustrating (A) a first mask used in a first exposure step and (B) a second mask used in a second exposure step in the method for forming a fine pattern according to the fourth embodiment of the present invention. 3A and 3B are a schematic diagram showing two masks and a schematic diagram showing a fine pattern formed in a semiconductor device.

FIG. 5 is a schematic cross-sectional view showing a semiconductor device in each step in a conventional method for forming a fine pattern.

[Explanation of symbols]

6 substrate, 7 processed layer, 7a remaining portion of processed layer,
7b fine pattern, 8 lower resist, 8a lower resist third region, 8b lower resist second region,
9 upper layer resist, 9a upper layer resist non-first region,
9b upper resist first region, 9c upper resist second region, 9d upper resist third region, 9e upper resist pattern, 10 first exposure, 11 second exposure,
12 Third exposure, 20, 30, 40 First mask, 2
0a, 30a, 40a First mask opening, 21, 3
1, 41 Second mask, 21a, 31a to 31d, 41
a to 41e Second mask opening, 25, 35, 45 Fine pattern.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G03F 7/40 521 H01L 21/28 D H01L 21/28 21/30 568 502C F-term (Reference) 2H025 AA02 AB16 AD03 BE00 BE10 BG00 CB41 DA11 FA06 FA39 FA41 2H096 AA25 BA11 EA14 HA23 HA30 KA03 4M104 BB01 DD62 DD65 HH14 5F046 AA13 JA22 LA14 LA18 LA19

Claims (12)

[Claims] A step of contacting a specific gas containing a specific element on the substrate to form a resist layer having a property of bonding with the specific element and enhancing resistance to a predetermined etching gas; Performing a first exposure on the resist layer in a first pattern, a step of forming a first exposure area that has received the first exposure and a first non-exposure area that does not receive the first exposure, Perform a second exposure on the first exposure area in a second pattern reduced at a predetermined interval from the outer edge of the first exposure area, the second exposure in the first exposure area Forming a second exposed region received and a third exposed region not subjected to the second exposure, and exposing the resist layer to a specific gas containing the specific element to form the third exposed region Only bonding with the specific element, and the second exposure region Removing the first non-exposed area by etching to form a resist pattern comprising the third exposed area. 2. The method according to claim 1, wherein the resist layer comprises an acetal group and t-
2. The method for forming a fine resist pattern according to claim 1, wherein the method is formed of a polymer protected by a butoxycarbonyl group. 3. The method according to claim 1, wherein the specific element is silicon. 4. The method according to claim 1, wherein the predetermined etching gas is an oxygen gas. 5. The resist pattern according to claim 1, wherein the resist pattern comprising the third exposure region has a circular shape, a rectangular shape, a line-and-space shape, or a cross shape. The method for forming a fine resist pattern according to the above. 6. A semiconductor device manufactured by the method for forming a fine resist pattern according to any one of claims 1 to 5. 7. A step of forming a layer to be processed on a substrate; and a step of forming a first resist layer on the layer to be processed.
On the first resist layer, a second resist layer having a property of contacting with a specific gas containing a specific element and bonding with the specific element to enhance resistance to a predetermined etching gas is formed. Performing a first exposure on the second resist layer with a first pattern, a first exposure area that has received the first exposure, and a first non-exposure area that does not receive the first exposure. And forming, the second exposure to the first exposure region in a second pattern reduced at a predetermined interval from the outer edge of the first exposure region, the second exposure of the first exposure region Forming a second exposure area that has received the second exposure and a third exposure area that does not receive the second exposure,
Exposing the second resist layer to a specific gas containing the specific element to combine only the third exposed region with the specific element, and removing the first non-exposed region by etching; Forming an exposed region of the first resist layer, and removing the exposed region of the first resist layer by etching to form a first exposed region of the processed layer; Removing the second exposed region by etching to form an exposed region of the first resist layer; and removing the first exposed region of the processed layer by etching with a constant thickness; and Removing the exposed region of the resist layer by etching to form a second exposed region of the processed layer, and using the third exposed region of the second resist layer as a mask, the first of the processed layer Dew Forming a pattern of the processed layer by removing the region by etching and etching the second exposed region of the processed layer while leaving a predetermined thickness. Forming method. 8. The method according to claim 7, wherein the second resist layer is formed of a polymer protected by an acetal group and a t-butoxycarbonyl group. 9. The method for forming a fine pattern according to claim 7, wherein the specific element is silicon. 10. The method for forming a fine pattern according to claim 7, wherein the predetermined etching gas is an oxygen gas. 11. The pattern of the layer to be processed is circular,
The method for forming a fine pattern according to any one of claims 7 to 10, wherein the method has a rectangular shape, a line-and-space shape, or a cross shape. 12. A semiconductor device manufactured by the method for forming a fine pattern according to any one of claims 7 to 11.