JP2002246861A - Variable gain amplifier and optical receiver using the same - Google Patents

Abstract

(57) [PROBLEMS] To provide a low-power and wide-band variable gain amplifier in which the band is not reduced even when the gain is changed. A variable gain amplifier includes transistors Q1 and Q2 having emitters connected to each other via a resistor and connected to a current source, and transistors Q3 and Q5 having collectors connected to one input of a load circuit LD. , Load circuit L
A transistor Q having a collector connected to the other input of D
4, Q6, resistors Rc1 and Rc2 having one ends connected to the emitters of transistors Q3 and Q4, respectively,
5, a resistor Rc having one end connected to the emitter of Q6.
3 and Rc4 and the other ends of the resistors Rc1 and Rc2 are connected to a transistor Q1.
The other ends of the resistors Rc3 and Rc4 are connected to the transistor Q
2 and the gain control signal Vcont is applied to the bases of the transistors Q3 to Q6.
The input signal is applied to the base of Q2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable gain amplifier and, more particularly, to a wideband variable gain amplifier whose bandwidth is not reduced even when the gain is changed, and an optical receiver using the variable gain amplifier.

[0002]

2. Description of the Related Art FIG. 2 shows an example of a conventional circuit frequently used as a variable gain amplifier. This conventional circuit includes a Gilbert-type multiplier including transistors Q1 to Q6 and a load circuit. The Gilbert multiplier is a transistor Q
1 and Q2 and two pairs of transistors Q3 to Q6 are connected in series, and two input signals V
current and the current signal Iou, which is proportional to the product of in and the gain control signal Vcont.
t0 and Iout1 are output. The output signals Vout are obtained by converting the current signals Iout0 and Iout1 into voltage signals in the load circuit LD.

Therefore, the gain (Vout / Vi) of this conventional circuit is
n) is proportional to the gain control signal Vcont,
By changing t, the gain can be changed.

Regarding such a conventional circuit, see, for example, Reference 1: IEE Journal of Solid-State Circuits, July 1994, pp. 815-822 (IEEE Journal of Solid-States Circuits, vol. 29,
no. 7, pp. 815-822, July 1994) and Reference 2: IEE Journal of Solid State Circuits, September 1999, pp. 1290-1297 (IEEE Journal of Solid State Circuits)
Solid-States Circuits, vol. 34, no.9, pp. 1290-12
97, Sept. 1999).

[0005]

However, the conventional circuit described above has the following problems. FIG.
3 shows an equivalent circuit of a gain control section including transistors Q3 and Q4 of the variable gain amplifier. The following equation (1) holds from this equivalent circuit.

[0006]

(Equation 1) Here, r _b is the base resistance, rπi the input resistance, Cπi
Is the sum of the depletion layer capacitance and the diffusion capacitance between the base and the emitter, g
_mi is the transconductance, zπi is the input resistance and capacitance Cπ
i parallel impedance (zπi = rπi // Cπi: i
= 3,4). When approximating r _b << rπ,
Current gain G _i of the gain control unit is represented by the following formula (2).

[0007]

(Equation 2) Here, assuming that the base traveling time is τ _Fi , Cπi ≒ g _mi ·
By approximating τ _Fi , the following equation (3) is obtained.

[0008]

(Equation 3) Here, G _i0 is a current gain. 3dB bandwidth of the G _i ω
_BWGi is given by the following equation (4).

[0009]

(Equation 4) The collector current I _C3 of the transistor Q3 (hereinafter, the collector current of the transistor Qi is represented as I _Ci ) and the current gain G _i0
FIG. 4 shows the relationship between the band and the band ω _BWGi . Here, I _C3
The calculation results in the case of + I _C4 = 3 mA and r _b = 44Ω are shown. The collector current I _C3 is normalized by I _C3 + I _C4 , and the band is normalized by the base transit time τ _F.

[0010] Collector current I_C3Increases from 0,
Flow gain G_i0Decreases to I_C3= I_C4And becomes 0,
G_iBand ω_BWGiTakes the minimum value. This is given by equation (3)
α is I _C3= I_C4(G_m3= G_m4= G_mM) At maximum (α
_max= G_mM・ R_b). Therefore, the gain
If it is reduced, the gain will be affected
The bandwidth of the entire amplifier is also reduced.

In order to solve this problem, the latter document 2 mentioned above proposes a variable gain amplifier as shown in FIG. This circuit comprises two variable gain amplifiers A1 and A2.
Are connected via an emitter follower EF.
The variable gain amplifier A1 is the same as the variable gain amplifier shown in FIG. 2, and the variable gain amplifier A2 includes a Gilbert multiplier and a load circuit LD2. Variable gain amplifier A2
The output signal of the variable gain amplifier A1 is input to the upper differential pair constituted by the transistors Q9 to Q12 through the emitter follower EF. The gain control signal Vcont2 is input to the lower differential pair formed by the transistors Q7 and Q8. Further, the transistor Q on one side of the upper differential pair
A peaking capacitor Cp is connected between the emitters of Q11 and Q12.

The bandwidth of the variable gain amplifier A2 increases when the gain is reduced, contrary to the variable gain amplifier A1. The reason will be described below. The collector currents I _C7 and I _C8 of the transistors Q7 and Q8 are I _C7 >> I _C8 when the gain is high, and the signal is mainly amplified by the differential amplifier including the transistors Q9 and Q10. However, when the gain is reduced (I _C7 > I _C8 ), the signals are output from the transistors Q9 and Q1.
0 and transistors Q11 and Q1
The signal is amplified by two differential amplifiers AR composed of two.

Further, a peaking capacitor Cp is connected to the differential amplifier AR, and the band of the differential amplifier AR is made wider than the band of the differential amplifier AL by zero generated by the resistors RE3 and RE4 and the peaking capacitor Cp. be able to. Thus, the band of the variable gain amplifier A2 can be increased when the gain is reduced. Therefore, by appropriately designing the peaking capacitance Cp, the variable gain amplifier A1
And the dependence of the band on the gain of A2 can be canceled each other, and the band can be prevented from decreasing even if the gain is reduced.

However, in this prior art, the required gain is relatively small, and even if it can be constituted by a single-stage amplifier, it must be constituted by a two-stage amplifier.
There is a problem that power consumption and chip size increase.
Further, since the signal input of the variable gain amplifier A2 is at the upper stage of the Gilbert type multiplier, it is necessary to increase the potential by about 1 V as compared with the signal input of the variable gain amplifier A1. For this reason, for example, when two stages of emitter follower circuits are connected as buffers between the variable gain amplifier A1 and the preceding circuit (not shown), the variable gain amplifiers A1 and A2
In between, only one stage of the emitter follower circuit EF can be connected. For this reason, the load seen from the variable gain amplifier A1 becomes heavy, and the band is reduced.

An object of the present invention is to provide a low-power and wide-band variable gain amplifier in which the band is not reduced even when the gain is changed.

[0016]

In order to achieve the above object, a variable gain amplifier according to the present invention has a structure in which respective emitters are connected to each other directly or via a resistor, and further connected to a current source. A first and a second transistor to which an input signal is applied, a third, a fourth, a fifth and a sixth transistor to which a gain control signal is applied to a base, and one end to an emitter of the third transistor. A first resistor connecting the other end to the collector of the first transistor; and a second resistor connecting one end to the emitter of the fourth transistor and the other end to the collector of the first transistor. A third resistor having one end connected to the emitter of the fifth transistor and the other end connected to the collector of the second transistor; A fourth resistor connected to the emitter of the transistor and the other end connected to the collector of the second transistor; one input connected to the collectors of the third and fifth transistors and the other input connected to the other input; And a load circuit for extracting an output to which the collectors of the fourth and sixth transistors are connected.

Further, in the variable gain amplifier described above, a transimpedance circuit, for example, a transimpedance circuit having a configuration shown in FIGS. 7 and 8 described later can be used as the load circuit.

Further, an output obtained by amplifying an input signal by the first variable gain amplifier is input to a second variable gain amplifier via an emitter follower circuit, and a two-stage connection for extracting an output signal from the second variable gain amplifier is provided. In the variable gain amplifier described above, it is preferable that the first and second variable gain amplifiers are each configured using the above-described variable gain amplifier according to the present invention. Thus, the output of the emitter follower circuit can be input to the bases of the first and second transistors in the lower stage constituting the second variable gain amplifier. Therefore, the number of stages of the emitter follower can be increased as compared with the prior art. , It is possible to reduce the load as viewed from the variable gain amplifier, and to realize a wider band. For example, in the prior art described in the above-mentioned document 1, the power supply voltage −6.
The emitter follower between the first and second variable gain amplifiers at 5V has a two-stage configuration. According to the present invention, it becomes possible to configure the emitter follower in three stages with the same power supply voltage as that of the prior art.

Still further, a photoelectric conversion element for converting an optical signal from an optical fiber into a current signal, a preamplifier for converting a current signal to a voltage signal, and an automatic gain for amplifying an output of the preamplifier to a certain amplitude. The control amplifier and the output of the automatic gain control amplifier are compared with a predetermined threshold voltage to determine "1" /
An automatic gain control amplifier, wherein the automatic gain control amplifier is capable of changing a gain, a control circuit for outputting a gain control signal for controlling the gain of the variable gain amplifier, An output amplitude detection circuit that detects the amplitude of the output signal of the variable gain amplifier and adjusts a gain control signal of the control circuit based on the detection result so that the output amplitude of the variable gain amplifier becomes constant. In the receiver, if any one of the variable gain amplifiers according to the present invention described above is used as the variable gain amplifier, a low power and wide band optical receiver can be realized, which is preferable.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Figure 1
FIG. 1 shows an embodiment of a variable gain amplifier according to the present invention. In FIG. 1, the same components as those of the conventional example shown in FIG. 2 are denoted by the same reference numerals. This embodiment is different from the conventional example shown in FIG. 2 in that the resistors Rc1 to Rc4 are connected to the emitters of the transistors Q3 to Q6 of the gain control unit, respectively. How the band of the gain control unit changes with the resistance will be described below. The resistor inserted between the emitters of the transistors Q1 and Q2 is provided to expand the linear input range, and the linear range required only by the emitter parasitic resistance associated with the transistors Q1 and Q2 can be secured. In that case, it may be deleted.

FIG. 6 shows a transistor Q of the present embodiment.
3 is an equivalent circuit of a gain control unit including Q4 and resistors Rc1 and Rc2. Here, the resistance values of the resistors Rc1 and Rc2 are both rc. From this equivalent circuit, the current gain G _i of the gain control unit is represented by the following formula (5).

[0022]

(Equation 5) Here, G _i0c is a current gain. Further, 3 dB bandwidth of the current gain G _i of the gain control unit is represented by the following equation (6).

[0023]

(Equation 6) The band of the conventional example shown in FIG. 2 represented by the formula (4) and the band of the present invention represented by the formula (6) have the same shape. Is wider. Comparing under the condition of g _m3 = g _m4 = g _mM where α and β are maximum, the following equation (7) is obtained.

[0024]

(Equation 7) If the following equation (8) is satisfied, α _max > β _max , and the band of the present invention is wider. _{r b · g mM> 1 ...} (8) whether the condition of the equation (8) is satisfied depends on the base resistance r _b of the transistor. That is, a transistor having an extremely low base resistance does not satisfy this condition, and the circuit configuration of the present invention may not be effective. However, in the transistor currently being developed, the above conditions are satisfied, and the present invention is effective. Hereinafter, it will be verified whether or not the above-mentioned conditions are satisfied, taking as an example a transistor having top-class performance among currently developed transistors.

The main use of the variable gain amplifier according to the present invention is considered to be an optical transmission system. The base resistance of a bipolar transistor used in this field is, for example, as follows.
Reference 3: IEE Journal of Solid State Circuits, January 1999, pages 18-24 (IEEE
Journal of Solid-States Circuits, vol. 34, no.
pp. 18-24, Jan. 1999), the silicon (Si) bipolar transistor has an emitter area of 0.3 × 2.8.
μm ² and the base resistance is 230Ω. Reference 4: ISSC Digest of Technical Papers, 2000, pp. 210-211 (ISSCC Dig
est of Technical Papers, pp. 210-211, 2000), the emitter area of the silicon-germanium (SiGe) heterojunction bipolar transistor is 0.2 × 2.0.
μm ² and the base resistance is 90Ω.

Since the current that can flow through these transistors is about 2 mA, g _mM is about 80 mS. Therefore, when calculating r _b · g _mM in the formula (8), 18.
4 and 7.2, which indicate that the present invention satisfies the condition that is effective. Thus, the condition of equation (8) holds for most high-speed bipolar transistors, and it can be said that the applicable range of the present invention is very wide.

[0027] FIG. 11 is the equivalent circuit of the variable gain amplifier according to the present invention shown in FIG. 6, the resistor Rc3, both the resistance values of Rc4 and rc = 30 [Omega, the collector current I _C3 of the transistor Q3 and current gain It shows the relationship between G _i0 and the band ω _BWGi . Again, as in FIG.
The calculation results in the case of I _C3 + I _C4 = 3 mA and r _b = 44Ω are shown. The collector current I _C3 is normalized by I _C3 + I _C4 , and the band is normalized by the base transit time τ _F. For comparison, the conventional configuration shown in FIG. 2 corresponding to the case where the resistors Rc1 to Rc4 are not provided in the configuration of the variable gain amplifier of the present invention, that is, the result of the resistance value rc = 0 (the same as FIG. 4)
Also shown. From FIG. 11, even if the current gain G _i0 is changed by changing the collector current, the band ω _BWGi is wider than the conventional example,
Also, it can be seen that the fluctuation is small.

As a case where the condition of the expression (8) is not satisfied, it is conceivable to connect a large number of transistors in parallel to lower the base resistance. In this case, however, the band is not improved because the parasitic capacitance increases. .

As described above, according to the present invention, there is provided a variable gain amplifier in which the band does not decrease even when the gain is changed.
Since it can be realized in stages, it is possible to contribute to low power consumption. Further, since the signal can be input to the lower stage of the Gilbert multiplier, an emitter follower circuit can be connected in multiple stages as a buffer between the circuits in the preceding stage. For example, when two stages of the variable gain amplifier of the present invention are used, the circuit EF can be configured as a two-stage emitter follower configuration as shown in FIG. 10 as a buffer between the stages. This makes it possible to reduce the load seen from the preceding circuit, and to realize a wideband variable gain amplifier.

FIG. 7 shows an example of the configuration of a load circuit LD suitable for combination with the variable gain amplifier according to the present invention. This load circuit comprises a differential pair of transistors QL1, QL2,
The transimpedance circuit is composed of resistors RL1 to RL4 and a current source, and its conversion gain (transimpedance gain) is substantially equal to the feedback resistors RL3 and RL4.
Is equal to the value of That is, a voltage output of RL (I _in1 −I _in0 ) is obtained. The frequency characteristic of the conversion gain of this load circuit is 2
The peaking effect can be obtained by approximating the transfer function with the next delay and setting the open loop gain large. This makes it possible to expand the band of the entire variable gain amplifier.

FIG. 8 shows another example of a load circuit LD suitable for combination with the variable gain amplifier of the present invention. This load circuit is constituted by a transimpedance circuit as in FIG. However, the difference is that the feedback resistors RL3 and RL4 are connected via the emitter follower transistors QL3 and QL4. Through the emitter follower,
The load seen from the collectors of the transistors QL1 and QL2 can be reduced, and a wider band can be achieved than in the circuit of FIG.

FIG. 9 shows the configuration of an optical receiver configured using the variable gain amplifier of the present invention. The optical receiver includes a photodiode PD that receives an optical signal from an optical fiber and converts it into a current signal, a preamplifier PRE that converts a current signal into a voltage signal, and an automatic gain control amplifier AGC that amplifies the output to a certain amplitude. And an identification circuit DEC that compares the output with a threshold voltage VTH to determine “1” / “0” and a clock CL based on the output of the automatic gain control amplifier.
It comprises a clock extraction circuit CEXT for extracting K.

The automatic gain control amplifier AGC comprises a variable gain amplifier VGA, an amplitude detection circuit AD, and a control circuit GC. The amplitude detection circuit AD is a variable gain amplifier VGA
Is detected, and if it is smaller than a predetermined amplitude, the control circuit GC adjusts the control signal so as to increase the gain of the variable gain amplifier. Conversely, if the detected amplitude is larger than the predetermined value, the control signal is adjusted so as to decrease the gain of the variable gain amplifier. Accordingly, the output amplitude of the automatic gain control amplifier AGC is always kept at a constant value regardless of the transmission distance of the optical fiber and the variation in the conversion efficiency of the photodiode PD, and a stable receiving operation can be realized. In this optical receiver, a low power and wide band optical receiver can be realized by configuring the variable gain amplifier VGA in the automatic gain control amplifier AGC with the variable gain amplifier of the present invention described above.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various design changes may be made without departing from the spirit of the present invention. It goes without saying that

[0035]

As is clear from the above-described embodiment, according to the present invention, a variable gain amplifier in which the band is not reduced even when the gain is changed can be realized in one stage. For this reason, it is possible to contribute to lower power consumption.

Since signals can be input to the lower stage of the Gilbert multiplier, multiple stages of emitter followers can be connected as buffers between the preceding stages. This makes it possible to reduce the load seen from the preceding circuit, and to realize a wideband variable gain amplifier.

Further, if the variable gain amplifier of the present invention is applied to an optical receiver, a low power and wide band optical receiver can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a basic configuration of a variable gain amplifier according to the present invention.

FIG. 2 is a circuit diagram showing a conventional variable gain amplifier.

FIG. 3 is an equivalent circuit diagram of the conventional gain amplifying unit shown in FIG.

4 is a diagram showing a relationship between an operating current and a band in the equivalent circuit shown in FIG.

FIG. 5 is a circuit diagram showing another example of a conventional variable gain amplifier.

FIG. 6 is an equivalent circuit diagram of a gain amplifier of the variable gain amplifier of the present invention shown in FIG.

FIG. 7 is a diagram showing an example of a load circuit used in the variable gain amplifier of the present invention.

FIG. 8 is a diagram showing another example of the load circuit used in the variable gain amplifier of the present invention.

FIG. 9 is a block circuit diagram showing a configuration example of an optical receiver to which the variable gain amplifier of the present invention is applied.

FIG. 10 is a circuit diagram showing a configuration example when two stages of variable gain amplifiers of the present invention are used.

11 is a diagram showing a relationship between an operating current and a band in the equivalent circuit shown in FIG.

[Explanation of symbols]

Q1 to Q12: bipolar transistors, QL1 to QL
6. Bipolar transistor, RE1, RE2, Rc1 ~
Rc4, RL1 to RL4: resistor, LD: load circuit, PRE
... preamplifier, AGC ... automatic gain control amplifier, DEC ...
Identification circuit, CEXT: clock extraction circuit, VGA: variable gain amplifier, AD: amplitude detection circuit, GC: control circuit.

Continued on the front page. (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H04B 10/04 10/28 10/26 (72) Inventor Katsuyoshi Washio 1-280, Higashi-Koigabo, Kokubunji, Tokyo Inside the Central Research Laboratory of the Works (72) Inventor Tohru Masuda 1-280 Higashi Koigabo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory of Hitachi, Ltd. F term (reference) 5J092 AA03 AA21 CA62 FA15 HA01 HA25 HA44 TA01 TA02 UL01 5J100 AA17 AA26 BB07 BB17 CA01 CA05 DA06 QA01 QA09 5K002 AA03 CA10 FA01

Claims (4)

[Claims] 1. Each emitter is connected to each other directly or via a resistor and further connected to a current source,
First and second input signals applied to respective bases
And a third, fourth, fifth, and sixth transistor having a base to which a gain control signal is applied; one end connected to the emitter of the third transistor, and the other end connected to the collector of the first transistor. Connect to the first
A second resistor having one end connected to the emitter of the fourth transistor and the other end connected to the collector of the first transistor; and one end connected to the emitter of the fifth transistor and the other end. A third resistor connected to the collector of the second transistor; a fourth resistor having one end connected to the emitter of the sixth transistor and the other end connected to the collector of the second transistor; A load circuit for taking out an output having an input connected to the collectors of the third and fifth transistors and the other input connected to the collectors of the fourth and sixth transistors. Variable gain amplifier. 2. The variable gain amplifier according to claim 1, wherein said load circuit comprises a transimpedance circuit. 3. A two-stage connection in which an output obtained by amplifying an input signal by a first variable gain amplifier is input to a second variable gain amplifier via an emitter follower circuit, and an output signal is extracted from the second variable gain amplifier. 3. The variable gain amplifier according to claim 1, wherein the variable gain amplifier according to claim 1 is used as each of the first and second variable gain amplifiers. 4. 4. A photoelectric conversion element for converting an optical signal from an optical fiber into a current signal, a preamplifier for converting a current signal to a voltage signal, and an automatic gain control for amplifying an output of the preamplifier to a constant amplitude. An amplifier and an identification circuit for comparing the output of the automatic gain control amplifier with a predetermined threshold voltage to determine whether the gain is "1" / "0", wherein the automatic gain control amplifier has a variable gain. A variable amplifier, a control circuit that outputs a gain control signal for controlling the gain of the variable gain amplifier, and an output amplitude of the variable gain amplifier based on a detection result of detecting the amplitude of the output signal of the variable gain amplifier. An optical receiver comprising: an output amplitude detection circuit that adjusts a gain control signal of the control circuit so as to be constant. The variable gain amplifier according to any one of claims 1 to 3, wherein the variable gain amplifier is provided. Optical receiver which comprises using the vessel.