JP2002246758A - Printed wiring board - Google Patents

Abstract

(57) [Problem] To provide a multilayer printed wiring board that can be directly electrically connected to an IC chip without using a lead component. SOLUTION: The multilayer printed wiring board has an IC chip (CPU) 20A and an IC chip (cache memory) 20B built in a core substrate 30 in advance, and the IC chip 20 is provided.
A and 20B are provided with a transition layer 38 on the die pad 24.
Is arranged. Therefore, the electrical connection between the IC chip and the multilayer printed wiring board can be established without using a lead component or a sealing resin. Further, by providing the transition layer 38 on the aluminum die pad 24, the die pad 24 is formed.
The remaining resin can be prevented, and the connectivity and reliability between the die pad 24 and the via hole 60 are improved. Also,
By incorporating a plurality of IC chips, high integration can be achieved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board incorporating a semiconductor element such as an IC chip.

[0002]

2. Description of the Related Art At present, flip-chip mounting uses a build-up printed wiring board. The build-up multilayer printed wiring board is manufactured by a method disclosed in, for example, Japanese Patent Application Laid-Open No. 9-130050. That is,
A roughened layer is formed by electroless plating or etching on the surface of the conductor circuit on the substrate, a resin layer is formed, a via hole opening for interlayer conduction is formed, and an interlayer resin insulating layer is formed. . Furthermore, a catalyst such as palladium is applied to the roughened surface of the interlayer insulating layer that has been roughened with an acid or an oxidizing agent to form an electroless plating film, and a pattern is formed on the plating film with a resist. Then, after thickening by electrolytic plating, the resist is peeled off and removed with a developer and etched to form a conductor circuit. By repeating this, a build-up multilayer printed wiring board is obtained. Solder bumps are formed on the surface layer, and are connected to the semiconductor element by flip-chip mounting.

There is a demand for a printed wiring board having higher density and higher functionality. To cope with this, it was necessary to propose a structure of a printed wiring board.

In the conventional mounting method, a lead component (wire, wire) for connection is provided between an IC chip and a printed wiring board.
Electrical connection is made via leads and bumps).
Since those lead parts are easily cut and corroded, IC
In some cases, the connection with the chip was interrupted or malfunctioned. In addition, in each mounting method, epoxy resin or the like is used to protect the IC chip, but if air bubbles etc. are included at that time, lead components are destroyed, IC pads are corroded, and reliability is reduced. Will be invited. In order to avoid them, it is necessary to propose a structure of a printed wiring board which can be directly electrically connected to an IC chip without using a lead component.

As a structure corresponding to the above problem, a semiconductor element is embedded in a substrate, and a wiring layer is formed on the element.
It is proposed to take a connection between the semiconductor element and the outside.

As a prior art for housing, housing, built-in or embedding a semiconductor element in a substrate, see Japanese Patent Application Laid-Open No. 9-32140.
No. 8 (US Pat. No. 5,875,100), JP-A-10-2564
29 and JP-A-11-126978. In each case, a semiconductor element is embedded in the substrate,
An electrical connection is obtained by forming a build-up layer.

Japanese Patent Application Laid-Open No. 9-321408 (USP 587)
No. 5100), a semiconductor element having a stud bump formed on a die pad is embedded in a printed wiring board, and a wiring is formed on the stud bump to make an electrical connection. However, since the stud bump has an onion shape and a large variation in height, when an interlayer insulating layer is formed, the smoothness is reduced, and even if a via hole is formed, the stud bump is easily disconnected. Further, the stud bumps are planted one by one by bonding, so that they cannot be arranged collectively, and there is a problem in terms of productivity.

Japanese Patent Application Laid-Open No. 10-256429 discloses a structure in which a semiconductor element is housed in a ceramic substrate and is electrically connected in a flip-chip form. However, ceramic has poor external formability, and the semiconductor element is not easily accommodated. In addition, the bumps had large variations in height. Therefore, the smoothness of the interlayer insulating layer is impaired, and the connection is reduced.

Japanese Patent Application Laid-Open No. 11-126978 discloses a multilayer printed wiring board in which electronic components such as a semiconductor element are embedded in a space accommodating portion, connected to a conductor circuit, and stored through via holes. ing. However, since the accommodating portion is an air gap, it is easy to cause a positional shift and disconnection to a pad of the semiconductor element is apt to occur. Further, since the die pad and the conductor circuit are directly connected, there is a problem that an oxide film is easily formed on the die pad and the insulation resistance is increased.

An object of the present invention is to propose a printed wiring board which can stably house a semiconductor element and can be directly electrically connected to an IC chip without using a lead component.

[0011]

As a result of intensive studies made by the inventors, the present invention has created that a printed wiring board in which a semiconductor element can be housed, housed, embedded or embedded can be obtained.

According to the first aspect of the present invention, in a printed wiring board in which an interlayer insulating layer and a conductor circuit are repeatedly laminated on a substrate to make electrical connection via via holes, a cavity is formed in the substrate. In the cavity, two or more semiconductor elements are housed, housed, or embedded. Thereby, a plurality of semiconductor elements are provided. Since a plurality of semiconductor elements are provided, mounting density is increased, and further higher density is achieved.

Further, since the semiconductor element is embedded therein, the wiring length to the external substrate and the external terminals can be shorter than that of the conventional flip-chip mounted printed wiring board. In addition, there is no need to provide unnecessary wiring for connection between semiconductors. Therefore, the delay and malfunction of the speeded up signal are reduced, and the loop inductance is further reduced. Further, the total thickness including the semiconductor element can be made smaller than that of the conventional flip chip. Therefore, it is optimally used for various electronic devices such as a notebook computer, a mobile phone, a mobile product, a communication device, and the like that require a thin housing.

The printed wiring board in which the cavities are formed is preferably composed mainly of resin. A material impregnated with a reinforcing material such as glass epoxy or a core material, a copper-clad laminate, or a substrate on which various prepregs are laminated can be used. Specific examples include an epoxy resin, a phenol resin, a polyimide resin, a BT resin, and a polyester resin.

The use of ceramic substrates and their main substrates (materials requiring high-temperature sintering such as ALN, mullite, silicon nitride, and alumina) and the like have also been considered, but the external formability is poor, and Since the difference in thermal expansion coefficient from the interlayer insulating layer is large, it cannot be used.

According to a second aspect of the present invention, in a printed wiring board in which an interlayer insulating layer and a conductor circuit are repeatedly laminated on a substrate to make an electrical connection through a via hole, a cavity is formed in the substrate. The printed circuit board has two or more semiconductor elements having a transition layer accommodated, accommodated, or embedded in the cavity.

A transition layer is provided between the die pad and the via hole of the interlayer insulating layer. If a via hole is formed directly on the die pad without forming a transition layer, if a photosensitive resin is used for the interlayer insulating layer, the via hole is formed through exposure and development. It was easy to remain. Further, the discoloration of the die pad was caused by the adhesion of the developer.
When the via hole was formed by laser, when the via diameter was larger than the die pad diameter, the die pad and the passivation film (IC protection film) were destroyed by the laser. By providing a transition layer on the die pad of the semiconductor element, it was possible to prevent them.

The die pad is covered with a transition layer. For this reason, discoloration and dissolution of the die pad do not occur even after being immersed in an acid or oxidizing agent or an etching solution through various steps, or through an annealing step or heat curing. Further, no oxide film of the die pad is formed.
Therefore, the connectivity and reliability between the pad and the via hole are improved.

The transition layer may be formed on a semiconductor element in advance, and then housed, housed, built-in or embedded in a printed wiring board. After being embedded in the printed wiring board, it may be formed.

According to the third aspect of the present invention, at least one of the semiconductor elements is a semiconductor element having an arithmetic function (CPU), and at least one is a semiconductor element having a storage function (memory).

A single semiconductor element having an arithmetic function (CPU) and a storage function (memory) may be mounted. However, the size of the semiconductor element is increased. It is cheaper to make them separately, and since the semiconductor elements are located near each other, transmission delay and malfunction do not occur. Further, even when the design of the printed wiring board is changed, there is no need to change the design of the semiconductor element itself, which has the effect of increasing the degree of freedom of formation.

According to the fourth aspect of the present invention, at least one selected from the group consisting of a resistor, a capacitor, and an inductance is housed, housed, or embedded in the cavity.

Since a resistor, a capacitor or an inductance is provided in addition to the semiconductor element, electric characteristics,
In particular, the operation in the initial operation can be performed without delay or malfunction. In addition, since the distance from the semiconductor element to the resistor, the capacitor, or the inductance can be shortened, the loop inductance can be surely reduced.

It is preferable to apply plating (particularly copper plating) to the surface of the terminal of the resistor, capacitor or inductance. This is because adhesion to via holes formed by plating (particularly, copper plating) is enhanced.

According to the fifth aspect of the present invention, it is preferable that the semiconductor device has at least two transition layers. At least the metal formed on the die pad and the metal formed on the via hole are preferably formed of different metals. More preferably, the metal connected to the die pad is formed of a thin and hard metal formed by sputtering, vapor deposition, and electrodeposition. The metal and the die pad are firmly joined. The metal connected to the via hole is formed by electrolytic plating. The electrolytic plating film is soft and highly malleable. Therefore, even if a stress is applied in the vicinity of the transition, it can be reduced. Since it is formed by the above combination, the vicinity of the die pad is strong, but the vicinity of the via hole is soft, so that the reliability can be improved even under heat cycle conditions.

According to the sixth aspect of the present invention, at least one of tin, chromium, titanium, nickel, zinc, cobalt, gold and copper is laminated on the lowermost layer of the transition layer of the semiconductor element. ing.

The metal formed on the die pad is tin,
Any of chromium, titanium, nickel, zinc, cobalt, gold, and copper is preferable. As a forming method, it is performed by any of sputtering, vapor deposition, electrodeposition, and plating. In particular, it is preferable that the film is formed of chromium, titanium, and nickel. These metals have good compatibility with not causing a chemical reaction or electrode reaction with the die pad, and with a metal formed thereon (particularly a metal formed by plating). Also, this is because the electric conductivity is not reduced. This is because there is no penetration of moisture from the interface and the metal adhesion is excellent.

According to the present invention, the uppermost layer of the transition layer of the semiconductor element is preferably selected from nickel, copper, gold and silver. The metal forming the transition layer and connecting to the via hole is preferably selected from nickel, copper, gold and silver. The formation is performed by electroless plating or electrolytic plating. In particular, it is desirable to be formed of either silver or copper. This is because silver has good electric characteristics, and copper has good electric characteristics and can be formed at low cost. In addition, since the wiring of the via hole is mainly formed of copper, the same metal does not cause peeling or cracking in the metal.

According to the present invention, the transition layer of the semiconductor device is formed of the first thin film layer, the second thin film layer, and the thick layer. The first thin film layer, the second thin film layer, and the thick layer are preferably formed in this order on the die pad of the semiconductor device.
The first thin film layer is preferably formed by sputtering, vapor deposition, and electrodeposition. The thickness is formed in the range of 0.001 to 2.0 μm. In particular, it is desirable that the thickness be 0.01 to 1.0 μm. The reason is that the die pad can be completely covered, and the electrical characteristics of the transition layer do not deteriorate. The second thin film layer is preferably formed by sputtering, vapor deposition, electrodeposition, and plating.
The thickness is formed in the range of 0.01 to 5.0 μm. In particular, it is desirable that the thickness be 0.1 to 3.0 μm.
The reason is the same as that of the first thin film layer. The thick layer is preferably formed by electroless plating or electrolytic plating. The thickness is formed in the range of 1 to 20 μm. It is particularly desirable that the thickness be 5 to 15 μm. This is because it is hardly affected by the formation of the via hole and the stress is easily relaxed during the heat cycle.

According to the ninth aspect of the present invention, the first thin film layer of the transition layer of the semiconductor element includes tin, chromium, titanium,
A material selected from nickel, zinc, cobalt, gold, and copper is preferred.

According to the tenth aspect, the second thin film layer of the transition layer of the semiconductor element is preferably selected from nickel, copper, gold, and silver.

In the eleventh aspect of the present invention, the cavity includes:
The adhesive layer is filled. The semiconductor element and the resistor, the capacitor or the inductance of the cavity can be joined, and the adhesive suppresses the behavior of the semiconductor element and the like even after the heat history at the time of heat cycle or via hole formation, and the smoothness is maintained. . For this reason, peeling or disconnection at the connection portion with the via hole or cracking of the interlayer insulating layer is not caused. In addition, the reliability can be improved.

In the twelfth aspect of the present invention, the thickness of the adhesive is
It varies depending on the thickness of the semiconductor element and the electronic component in the cavity. As a result, there is no unevenness on the upper surface of the cavity and an interlayer insulating layer is formed, so there is no swelling.
The via hole is reliably connected to the semiconductor element and other terminals so as to have a desired size and shape. Therefore,
Connectivity and reliability can also be improved.

The transition layer defined in the present invention will be described. The transition layer means an intermediate mediation layer provided for directly connecting an IC chip as a semiconductor element and a printed wiring board without using a conventional IC chip mounting technique. It is characterized in that it is formed of two or more metal layers and is larger than a die pad of an IC chip as a semiconductor element. Thereby, electrical connection and alignment are improved, and via holes can be formed by laser or photoetching without damaging the die pad. Therefore, embedding, accommodation, accommodation, and connection of the IC chip in the printed wiring board can be ensured. In addition, it is possible to directly form a metal which is a conductor layer of a printed wiring board on the transition layer.
Examples of the conductor layer include via holes in an interlayer resin insulating layer and through holes on a substrate.

[0035]

Embodiments of the present invention will be described below with reference to the drawings. First, the configuration of the multilayer printed wiring board according to the first embodiment of the present invention will be described with reference to FIG.

As shown in FIG. 7, the multilayer printed wiring board 10
Is composed of a core substrate 30 containing an IC chip (CPU) 20A and an IC chip (cache memory) 20B, an interlayer resin insulation layer 50, and an interlayer resin insulation layer 150. Via holes 60 and conductive circuits 58 are formed in interlayer resin insulating layer 50, and via holes 160 and conductive circuits 158 are formed in interlayer resin insulating layer 150.

The IC chips 20A and 20B are covered with a passivation film 24.
A die pad 22 that constitutes an input / output terminal is disposed in the opening. A transition layer 38 is formed on the die pad 22 made of aluminum. The transition layer 38 includes a first thin film layer 33, a second thin film layer 36,
It has a three-layer structure of the thick film 37.

On the interlayer resin insulation layer 150, a solder resist layer 70 is provided. The conductor circuit 158 below the opening 71 of the solder resist layer 70 is provided with a BGA 76 for connection to an unillustrated external board such as a daughter board or a motherboard.

In the multilayer printed wiring board 10 of this embodiment, the IC chips 20A and 20B are preliminarily built in the core substrate 30, and the die pads 2 of the IC chips 20A and 20B are provided.
2, a transition layer 38 is provided. Therefore, the electrical connection between the IC chip and the multilayer printed wiring board (package substrate) can be established without using a lead component or a sealing resin. Further, since the transition layer 38 is formed in the IC chip portion, the IC chip portion is flattened, so that the upper interlayer insulating layer 50 is also flattened and the film thickness becomes uniform. Furthermore, the transition layer can maintain the shape stability even when the upper via hole 60 is formed.

Further, by providing a copper transition layer 38 on the die pad 22, resin residue on the die pad 22 can be prevented. Also, in a later step, the resin is immersed in an acid, an oxidizing agent, an etching solution, or the like. Discoloration and dissolution of the die pad 22 do not occur even after various annealing processes. This improves the connectivity and reliability between the die pad of the IC chip and the via hole. Further, by interposing the transition layer 38 having a diameter of 60 μm or more on the die pad 22 having a diameter of about 40 μm, a via hole having a diameter of 60 μm can be reliably connected.

In the present embodiment, the CPU IC chip 20
A and the cache memory IC chip 20B are individually embedded in the printed wiring board. It is cheaper to produce the IC chips separately, and since each IC chip is located in the vicinity, there is no occurrence of transmission delay or malfunction. Further, even when the design of the printed wiring board is changed, the design of the IC chip itself is not required to be changed, and the degree of freedom of formation can be increased.

The recess 32 of the printed wiring board of this embodiment is filled with an adhesive layer 34. IC of the recess 32
The chips 20A and 20B can be joined, and the adhesive 34 suppresses the behavior of the IC chips 20A and 20B even after a heat history during a heat cycle or a via hole formation, and the smoothness is maintained. Therefore, peeling or disconnection at a connection portion with a via hole, or interlayer insulating layers 50 and 150
Does not cause cracks. In addition, the reliability can be improved.

Next, a method of manufacturing the multilayer printed wiring board described above with reference to FIG. 7 will be described with reference to FIGS.

(1) First, an insulating resin substrate (core substrate) 30 in which a prepreg obtained by impregnating a resin such as epoxy into a core material such as glass cloth is used as a starting material (FIG. 1A).
reference). Next, on one surface of the core substrate 30,
A concave portion 32 for accommodating the C chip is formed (see FIG. 1B). Here, the concave portion is formed by counterboring, but a core substrate having an accommodating portion can be formed by laminating an insulating resin substrate having an opening and a resin insulating substrate having no opening.

(2) Thereafter, an adhesive material 34 is applied to the recess 32 using a printing machine. At this time, besides coating,
Potting may be performed. Next, the IC chip 20
A and 20B are placed on the adhesive material 34 (see FIG. 1C).

(3) Then, the IC chips 20A and 20B
Is pressed or hit to completely house the recess 32 (see FIG. 2A). Thereby, the core substrate 30
Can be smoothed.

(4) Thereafter, the IC chips 20A and 20B
The conductive first thin film layer 33 is formed on the entire surface of the core substrate 30 in which is accommodated (FIG. 2B). The metals include nickel, zinc,
Chromium, cobalt, titanium, gold, copper, tin, iron and the like are preferred. In particular, using nickel, chromium, and titanium
Suitable for film formation and electrical characteristics. As the thickness,
It is preferred that the thickness be formed between 0.001 and 2.0 μm. In the case of chromium, a thickness of 0.1 μm is desirable.

The die pad 22 is covered with the first thin film layer 33, so that the adhesion between the transition layer and the IC chip at the interface with the die pad 22 can be enhanced. Also,
By coating the die pad 22 with these metals, it is possible to prevent moisture from entering the interface, prevent the die pad from dissolving and corroding, and improve reliability. In addition, the first thin film layer 33 allows connection with an IC chip by a lead-free mounting method. Here, it is desirable to use chromium or titanium in order to prevent moisture from entering the interface.

(5) A second thin film layer 36 is formed on the first thin film layer 33 by sputtering, vapor deposition, or electroless plating (FIG. 2C). Nickel as the metal,
Copper, gold, silver and the like. It is preferable to use copper because the electrical characteristics, economy, and the conductor layer, which is a build-up formed later, are mainly copper.

The reason for providing the second thin film layer is that the first thin film layer cannot take a lead for electrolytic plating for forming a thick layer described later. Second thin film layer 3
Reference numeral 6 is used as a thick lead. The thickness is preferably in the range of 0.01 to 5 μm. 0.01 μm
If it is less than 5 μm, it may not serve as a lead, and if it exceeds 5 μm, the lower first thin film layer may be shaved more to form a gap at the time of etching, making it easier for moisture to enter,
This is because the reliability decreases.

(6) After that, a resist is applied,
After development, a plating resist 35 is provided so as to provide an opening above the die pad of the IC chip, electrolytic plating is performed under the following conditions, and an electrolytic plating film (thick film) 37 is provided (FIG. 3A).

[Aqueous electrolytic plating solution] Sulfuric acid 2.24 mol / l Copper sulfate 0.26 mol / l Additive (captoside HL, manufactured by Atotech Japan) 19.5 ml / l [Electroplating conditions] Current density 1 A / dm ² Time 65 minutes Temperature 22 ± 2 ℃

After removing the plating resist 35, the electroless second thin film layer 36 and the first thin film layer 3 under the plating resist 35 are removed.
3 is removed by etching to form a transition layer 38 on the die pad 22 of the IC chip.
(B)). Here, the transition layer is formed by a plating resist. However, after an electrolytic plating film is uniformly formed on the electroless second thin film layer 36, an etching resist is formed, and exposure and development are performed to obtain portions other than the transition layer. It is also possible to form a transition layer on the die pad of the IC chip by exposing the metal of the above to the etching. The thickness of the electrolytic plating film is preferably in the range of 1 to 20 μm. If the thickness is larger than that, an undercut occurs at the time of etching, and a gap may be generated at the interface between the formed transition layer and the via hole.

(7) Next, a roughened surface 38α is formed by spraying an etching solution onto the substrate by spraying and etching the surface of the transition layer 38 (FIG. 3C).
reference). The roughened surface can be formed by using electroless plating or oxidation-reduction treatment. The transition layer 38 is a first layer.
It has a three-layer structure of a thin film layer 33, a second thin film layer 36, and a thick film 37.

(8) A substrate having a thickness of 50 μm
m thermosetting resin sheet is vacuum-press-laminated at a pressure of 5 kg / cm ² while the temperature is raised to a temperature of 50 to 150 ° C.,
An interlayer resin insulating layer 50 is provided (see FIG. 4A). The degree of vacuum during vacuum compression is 10 mmHg.

(9) Next, using a CO ₂ gas laser having a wavelength of 10.4 μm, a beam diameter of 5 mm, a top hat mode,
Under the conditions of a pulse width of 5.0 μsec, a mask hole diameter of 0.5 mm, and one shot, a via hole opening 48 having a diameter of 80 μm is provided in the interlayer resin insulating layer 50 (see FIG. 4B). The residual resin in the opening 48 is removed using chromic acid. By providing the transition layer 38 made of copper on the die pad 22, resin residue on the die pad 22 can be prevented, thereby improving the connectivity and reliability between the die pad 22 and via holes 60 described later. In addition, 40μ
By interposing the transition layer 38 having a diameter of 60 μm or more on the die pad 22 having a diameter of about m, the via hole opening 48 having a diameter of 60 μm can be reliably connected. Here, the resin residue is removed using permanganic acid, but it is also possible to perform desmear treatment using oxygen plasma. Here, the opening 48 is formed by a laser.
Is formed, but it is also possible to form an opening by exposure and development processing.

(10) Next, the surface of the interlayer resin insulating layer 50 is roughened with an acid or an oxidizing agent to form a roughened surface 50α (see FIG. 4C). The rough surface is preferably formed with an average roughness of 1 to 5 μm.

(11) Next, an electroless plating film 52 is provided on the interlayer resin insulating layer 50 on which the roughened surface 50α is formed (see FIG. 5A). Copper and nickel can be used as the electroless plating. The thickness is 0.3
The range of μm to 1.2 μm is good. If it is less than 0.3 μm,
In some cases, a metal film cannot be formed on the interlayer resin insulating layer. If the thickness exceeds 1.2 μm, the metal film remains due to the etching, and a short circuit between conductors is easily caused. A plating film was formed under the following plating solution and plating conditions. [Electroless plating aqueous solution] NiSO ₄ 0.003 mol / l tartaric acid 0.200 mol / l copper sulfate 0.030 mol / l HCHO 0.050 mol / l NaOH 0.100 mol / l α, α'-bipyryl 100 mg / l Polyethylene glycol (PEG) 0.10 g / l [Electroless Plating Condition] Dipped at a liquid temperature of 34 ° C. for 40 minutes.

Other than the above, using the same apparatus as the above-described plasma processing, sputtering using a Ni—Cu alloy as a target was performed at a pressure of 0.6 Pa, a temperature of 80 ° C., and a power of 200
The process is performed under the condition of W for 5 minutes to form a Ni—Cu alloy 52 on the surface of the interlayer resin insulating layer 50. At this time, the thickness of the formed Ni—Cu alloy layer 52 is 0.2 μm.

(12) A commercially available photosensitive dry film is affixed to the substrate 30 that has been subjected to the above processing, a chromium glass mask is placed thereon, and after exposing at 40 mJ / cm ² , the substrate is dried.
Develop with 8% sodium carbonate to provide a plating resist 54 having a thickness of 25 μm. Next, electrolytic plating is performed under the following conditions to form an electrolytic plating film 56 having a thickness of 18 μm (see FIG. 5B). The additive in the electrolytic plating aqueous solution is Capparaside HL manufactured by Atotech Japan.

[Aqueous electrolytic plating solution] Sulfuric acid 2.24 mol / l Copper sulfate 0.26 mol / l Additive (captoside HL, manufactured by Atotech Japan) 19.5 ml / l [Electroplating conditions] Current density 1 A / dm ² Time 65 minutes Temperature 22 ± 2 ℃

(13) The plating resist 54 is made of 5% NaO
After removing with H, the plating film layer 52 under the plating resist is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and a thickness of 16 μm comprising the plating film layer 52 and the electrolytic plating film 56 is formed. Are formed, and roughened surfaces 58α and 60α are formed using an etching solution containing a cupric complex and an organic acid (see FIG. 5C). The roughened surface can be formed by using electroless plating or oxidation-reduction treatment.

(14) Next, the above steps (9) to (13) are repeated to form an upper interlayer resin insulation layer 150 and a conductor circuit 158 (including via holes 160) (FIG. 6 ( A)).

(15) Next, a cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) so as to have a concentration of 60% by weight was used. Oligomer for imparting properties (molecular weight 4000) 46.67
15 parts by weight of a bisphenol A type epoxy resin (trade name: Epicoat 1001 manufactured by Yuka Shell Co., Ltd.) of 80% by weight dissolved in methyl ethyl ketone, imidazole hardener (trade name: 2E4MZ-CN)
1.6 parts by weight, 3 parts by weight of a polyfunctional acrylic monomer (manufactured by Kyoei Chemical Co., trade name: R604) as a photosensitive monomer,
Similarly, polyvalent acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., trade name:
1.5 parts by weight of DPE6A) and 0.71 part by weight of a dispersant antifoaming agent (manufactured by San Nopco, trade name: S-65) are placed in a container, stirred and mixed to prepare a mixed composition. Of benzophenone (manufactured by Kanto Kagaku) and 0.2 parts by weight of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer were added to give a viscosity of 25.
A solder resist composition (organic resin insulating material) adjusted to 2.0 Pa · s at ° C is obtained. The viscosity was measured using a B-type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.) at 60 rpm and rotor No. 4 at 6 rpm.
According to

(16) Next, the above-mentioned solder resist composition is applied to the substrate 30 at a thickness of 20 μm,
After performing a drying process at 70 ° C. for 30 minutes for 0 minutes, a 5 mm-thick photomask on which a pattern of the opening of the solder resist resist is drawn is brought into close contact with the solder resist layer 70, and an ultraviolet ray of 1000 mJ / cm ² is applied. And developing with a DMTG solution to form an opening 71 having an opening diameter of 460 μm (see FIG. 6B).

(17) Next, the substrate on which the solder resist layer (organic resin insulating layer) 70 has been formed is coated with nickel chloride (2.3 × 10 ⁻¹ mol / l) and sodium hypophosphite (2.8 × 10 ⁻¹ mol / l). 10 ^-1 mol / l) and an electroless nickel plating solution having a pH of 4.5 containing sodium citrate (1.6 × 10 ^-1 mol / l) for 20 minutes.
Then, a nickel plating layer 72 having a thickness of 5 μm is formed. Further, the substrate was subjected to potassium gold cyanide (7.6 × 10 ^−3).
mol / l), ammonium chloride (1.9 × 10 ^-1 mo)
1 / l), sodium citrate (1.2 × 10 ^-1 mol)
/ L), sodium hypophosphite (1.7 × 10 ^-1 mol)
/ L) is immersed for 7.5 minutes at 80 ° C. in an electroless plating solution containing
By forming the gold plating layer 74 of the length m, the conductor circuit 158 can be formed.
Then, a solder pad 75 is formed (see FIG. 6C).

(18) Thereafter, the solder resist layer 70
BGA 76 is formed by printing a solder paste in opening 71 of the substrate and performing reflow at 200 ° C. Thereby, the IC chips 20A and 20B are built in, and the BGA7
6 can be obtained (see FIG. 7). PGA (conductive connection pin) may be used instead of BGA.

In the above embodiment, the interlayer resin insulation layer 5
A thermosetting epoxy resin sheet was used for Nos. 0 and 150.
This epoxy resin contains a hardly soluble resin, soluble particles, a curing agent, and other components. Each is described below.

[0069] The epoxy resin used in the production method of the present invention comprises particles soluble in an acid or an oxidizing agent (hereinafter referred to as "soluble particles") in a resin which is hardly soluble in an acid or an oxidizing agent (hereinafter referred to as a "slightly soluble resin"). It is distributed in. The terms "sparingly soluble" and "soluble" used in the present invention are referred to as "soluble" for convenience when those immersed in a solution comprising the same acid or oxidizing agent for the same time have a relatively high dissolution rate. Those having a relatively low dissolution rate are referred to as "poorly soluble" for convenience.

Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble resin particles”), inorganic particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble inorganic particles”), and an acid or an oxidizing agent. Soluble metal particles (hereinafter referred to as “soluble metal particles”) and the like. These soluble particles may be used alone or in combination of two or more.

The shape of the soluble particles is not particularly limited.
Spherical, crushed and the like. The shape of the soluble particles is desirably a uniform shape. This is because a roughened surface having unevenness with a uniform roughness can be formed.

The average particle size of the above-mentioned soluble particles is 0.1.
1 to 10 μm is desirable. Within this particle size range, 2
More than one kind of particles having different particle sizes may be contained. That is, it contains soluble particles having an average particle size of 0.1 to 0.5 μm and soluble particles having an average particle size of 1 to 3 μm.
Thereby, a more complicated roughened surface can be formed,
Excellent adhesion to conductor circuits. In the present invention, the particle size of the soluble particles is the length of the longest portion of the soluble particles.

Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like. When immersed in a solution containing an acid or an oxidizing agent, the soluble resin particles have a higher dissolution rate than the hardly soluble resin. If it is, there is no particular limitation. Specific examples of the soluble resin particles include, for example, those made of epoxy resin, phenol resin, polyimide resin, polyphenylene resin, polyolefin resin, fluororesin, and the like, and may be made of one of these resins. Alternatively, it may be composed of a mixture of two or more resins.

As the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, various modified polybutadiene rubbers such as epoxy-modified, urethane-modified, (meth) acrylonitrile-modified, and (meth) acrylonitrile-butadiene rubber containing a carboxyl group. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. In other words, when dissolving the soluble resin particles using an acid, an acid other than a strong acid can be dissolved, and when dissolving the soluble resin particles using an oxidizing agent, permanganese having a relatively weak oxidizing power is used. Acid salts can also be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, the acid or the oxidizing agent does not remain on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after forming the roughened surface, the catalyst is not applied or the catalyst is oxidized. Or not.

Examples of the soluble inorganic particles include particles made of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds and silicon compounds.

Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and
Examples of the potassium compound include potassium carbonate.Examples of the magnesium compound include magnesia, dolomite, and basic magnesium carbonate.Examples of the silicon compound include silica and zeolite. Is mentioned. These may be used alone or in combination of two or more.

The soluble metal particles include, for example,
Copper, nickel, iron, zinc, lead, gold, silver, aluminum,
Examples include particles made of at least one selected from the group consisting of magnesium, calcium, and silicon. These soluble metal particles may have a surface layer coated with a resin or the like in order to ensure insulation.

When two or more of the above-mentioned soluble particles are used in combination, the combination of the two types of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both have low conductivity, so that the insulation of the resin sheet can be ensured, and the thermal expansion can be easily adjusted with the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin sheet. This is because peeling does not occur between the interlayer resin insulating layer and the conductor circuit.

The hardly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed by using an acid or an oxidizing agent in the interlayer resin insulating layer. Examples thereof include thermosetting resins, thermoplastic resins, and composites thereof. Further, a photosensitive resin obtained by imparting photosensitivity to these resins may be used. By using a photosensitive resin, an opening for a via hole can be formed in an interlayer resin insulating layer by using exposure and development processes. Among these, those containing a thermosetting resin are desirable. Thereby, the shape of the roughened surface can be maintained even by the plating solution or various heat treatments.

Specific examples of the hardly soluble resin include, for example, epoxy resin, phenol resin, phenoxy resin,
Examples thereof include a polyimide resin, a polyphenylene resin, a polyolefin resin, and a fluorine resin. These resins may be used alone or in combination of two or more. Further, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the above-described roughened surface be formed, but also excellent in heat resistance, etc., even under heat cycle conditions, stress concentration does not occur in the metal layer, and peeling of the metal layer does not easily occur. Because.

Examples of the epoxy resin include cresol novolak type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolak type epoxy resin, alkylphenol novolak type epoxy resin, biphenol F type epoxy resin, and naphthalene type epoxy resin. Resin, dicyclopentadiene type epoxy resin, epoxidized product of condensate of phenols and aromatic aldehyde having phenolic hydroxyl group,
Triglycidyl isocyanurate, alicyclic epoxy resin and the like. These may be used alone or in combination of two or more. Thereby, it becomes excellent in heat resistance and the like.

In the resin sheet used in the present invention, it is desirable that the soluble particles are substantially uniformly dispersed in the hardly-soluble resin. It is possible to form a roughened surface with unevenness of uniform roughness, and even if via holes and through holes are formed in the resin sheet, it is possible to secure the adhesion of the metal layer of the conductor circuit formed thereon. Because you can.
Alternatively, a resin sheet containing soluble particles only in the surface layer forming the roughened surface may be used. Thereby, since the portions other than the surface layer of the resin sheet are not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulating layer is reliably maintained.

In the above resin sheet, the amount of the soluble particles dispersed in the poorly soluble resin is preferably 3 to 40% by weight based on the resin sheet. If the amount of the soluble particles is less than 3% by weight, a roughened surface having desired irregularities may not be formed.
When the soluble particles are dissolved using an acid or an oxidizing agent, they dissolve to the deep part of the resin sheet, failing to maintain the insulation between the conductor circuits via the interlayer resin insulation layer made of the resin sheet, and causing a short circuit. It may be.

The resin sheet desirably contains a curing agent and other components in addition to the soluble particles and the hardly-soluble resin. Examples of the curing agent include imidazole-based curing agents, amine-based curing agents, guanidine-based curing agents, epoxy adducts of these curing agents and those obtained by microencapsulating these curing agents, triphenylphosphine, and tetraphenylphosphonate. Organic phosphine-based compounds such as ammonium tetraphenylborate.

The content of the curing agent is desirably 0.05 to 10% by weight based on the resin sheet. 0.0
If the content is less than 5% by weight, the resin sheet is insufficiently cured, so that the degree of penetration of acid or oxidizing agent into the resin sheet becomes large, and the insulating property of the resin sheet may be impaired. On the other hand, when the content exceeds 10% by weight, an excessive curing agent component may modify the composition of the resin, which may cause a decrease in reliability.

Examples of the other components include fillers such as inorganic compounds or resins which do not affect the formation of the roughened surface. As the inorganic compound, for example,
Examples of the resin include silica, alumina, and dolomite. Examples of the resin include a polyimide resin, a polyacryl resin, a polyamideimide resin, a polyphenylene resin, a melanin resin, and an olefin resin. By incorporating these fillers, the performance of the multilayer printed wiring board can be improved by matching thermal expansion coefficients, improving heat resistance and chemical resistance, and the like.

Further, the resin sheet may contain a solvent. Examples of the solvent include ketones such as acetone, methyl ethyl ketone and cyclohexanone, ethyl acetate, butyl acetate, aromatic hydrocarbons such as cellosolve acetate, toluene and xylene. These may be used alone or in combination of two or more. However, these interlayer resin insulation layers are dissolved and carbonized when a temperature of 350 ° C. or more is applied.

[Second Embodiment] Next, a printed wiring board according to a second embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 9, in the second embodiment, an IC chip (CP
U) A chip capacitor 19A, a chip resistor 19B, and a chip inductance 19C are accommodated together with an IC chip (cache memory) 20B. here,
Copper plating film 19 is provided on terminals 19a of chip capacitor 19A, chip resistor 19B, and chip inductance 19C.
b is coated. Thereby, the connectivity with the via hole 60 made of copper plating is improved.

A method for manufacturing a printed wiring board according to the second embodiment will be described with reference to FIG. (1) First, a concave portion 32 for accommodating an IC chip is formed on one surface of an insulating resin substrate (core substrate) 30 in which a prepreg obtained by impregnating a resin such as epoxy with a core material such as glass cloth is laminated (see FIG. 8 (A)).

(2) Then, an adhesive material 34 is applied to the recess 32 using a printing machine. At this time, besides coating,
Potting may be performed. Next, the IC chip 20
A, 20B, chip capacitor 19A, chip resistor 19
B, the chip inductance 19C is placed on the adhesive material 34 (see FIG. 8B).

(3) Then, the IC chips 20A, 20
B, the top surfaces of the chip capacitor 19A, the chip resistor 19B, and the chip inductance 19C are pushed or hit to completely accommodate the recess 32 (see FIG. 8C). Thereby, the core substrate 30 can be smoothed. Subsequent steps are the same as in the first embodiment described above with reference to FIGS.

[Third Embodiment] Next, a printed wiring board according to a third embodiment will be described with reference to FIG. As shown in FIG. 10B, in the third embodiment, an IC chip (CPU) 20 is provided in a concave portion 32 of a core substrate 30.
A, an IC chip (cache memory) 20B, a chip capacitor 19A, a chip resistor 19B, and a chip inductance 19C are accommodated. In the third embodiment, below the IC chip (CPU) 20A, IC chip (cache memory) 20B, chip capacitor 19A, chip resistor 19B, and chip inductance 19C,
A connection layer 31 for adjusting the height is provided.

A method for manufacturing a printed wiring board according to the third embodiment will be described with reference to FIG. (1) Below the IC chip (CPU) 20A, IC chip (cache memory) 20B, chip capacitor 19A, chip resistor 19B, and chip inductance 19C,
A connection layer 31 for adjusting the height is provided, and a core substrate 30 is provided.
Is accommodated in the concave portion 32. Subsequent steps are the same as in the first embodiment described above with reference to FIGS.

[Fourth Embodiment] Next, a printed wiring board according to a fourth embodiment will be described with reference to FIGS. FIG. 21 shows a printed wiring board according to the fourth embodiment. The printed wiring board according to the fourth embodiment is shown in FIG.
This is the same as the printed wiring board of the first embodiment described above with reference to FIG. However, in the first embodiment described above, after the IC chip is housed in the core substrate 30, the transition layer 38
Was formed. On the other hand, in the fourth embodiment, the transition layer 38 is formed on the IC chip and then housed in the core substrate. Therefore, first, a method of forming the transition layer 38 on the IC chip will be described.

A. First, regarding a configuration of a semiconductor element (IC chip) according to the fourth embodiment of the present invention, FIG. 13A showing a cross section of the semiconductor element 20 and FIG. This will be described with reference to FIG.

As shown in FIG. 13B, the semiconductor device 20
A die pad 22 and a wiring (not shown) are provided on the upper surface of the substrate, and a passivation film 24 is coated on the die pad 22 and the wiring, and an opening of the passivation film 24 is formed in the die pad 22. Have been.
On the die pad 22, a transition layer 38 mainly made of copper is formed. Transition layer 38
Comprises a thin film layer 33 and an electrolytic plating film 37.

[First Manufacturing Method] Subsequently, FIG.
The method of manufacturing the semiconductor device described above with reference to FIG. 11 will be described with reference to FIGS.

(1) First, the wiring 21 and the die pad 22 are formed on the silicon wafer 20A shown in FIG. 11A by a conventional method (FIG. 11B and FIG. 14B showing a plan view of FIG. 11B). A), and FIG. 11B shows a cross section taken along line BB of FIG. 14A). (2) Next, a passivation film 24 is formed on the die pad 22 and the wiring 21, and an opening 24a is provided on the die pad 22 (FIG. 11C).

(3) A conductive metal film (thin film layer) 33 is formed on the entire surface of the silicon wafer 20A by physical vapor deposition such as vapor deposition or sputtering (FIG. 12).
(A)). The thickness is preferably in the range of 0.001 to 2.0 μm. If it is below the range, a thin film layer cannot be formed on the entire surface. If it is higher than this range, the thickness of the formed film will vary. The optimal range is from 0.01 to 1.0 μm. Metals to be formed include tin, chromium, titanium, nickel,
It is preferable to use one selected from zinc, cobalt, gold, and copper. These metals serve as a protective film for the die pad and do not degrade the electrical characteristics. In the first manufacturing method, the thin film layer 33 is formed of chromium.

(4) Thereafter, a resist layer of any of a liquid resist, a photosensitive resist and a dry film is formed on the thin film layer 33. A mask (not shown) on which a portion for forming the transition layer 38 is drawn is placed on the resist layer, and exposed and developed, and the plating resist 35 is formed.
To form a non-formed portion 35a. Thick layer (electrolytic plating film) on the non-formed portion 35a of the resist layer by applying electrolytic plating
37 are provided (FIG. 12B). Examples of the type of plating formed include copper, nickel, gold, silver, zinc, and iron. Since the electrical characteristics, economy, and the conductor layer which is a build-up formed later are mainly copper, copper is preferably used. In the first manufacturing method, copper is used. The thickness is preferably in the range of 1 to 20 μm.

(5) After the plating resist 35 has been removed with an alkaline solution or the like, the metal film 33 under the plating resist 35 is coated with sulfuric acid-hydrogen peroxide, ferric chloride, cupric chloride, cupric complex-organic By removing with an etching solution such as an acid salt, the transition layer 38
Is formed (FIG. 12C).

(6) Next, a roughened surface 38α is formed by spraying an etching solution on the substrate by spraying and etching the surface of the transition layer 38 (FIG. 13).
(A)). The roughened surface can be formed by using electroless plating or oxidation-reduction treatment.

(7) Lastly, the silicon wafer 20A on which the transition layer 38 is formed is divided into individual pieces by dicing or the like to form the semiconductor elements 20 (FIG. 1).
FIG. 14 (B) which is a plan view of FIGS. 3 (B) and 13 (B).
reference). Thereafter, if necessary, an operation check and an electrical inspection of the divided semiconductor elements 20 may be performed. Since the semiconductor element 20 has the transition layer 38 larger than the die pad 22, the probe pins can be easily applied to the semiconductor element 20, and the inspection accuracy is high.

[Second Manufacturing Method] A semiconductor device 20 according to a second manufacturing method will be described with reference to FIG. In the semiconductor device according to the first manufacturing method described above with reference to FIG. 13B, the transition layer 38 has a two-layer structure including the thin film layer 33 and the electrolytic plating film 37.
On the other hand, in the second manufacturing method, as shown in FIG. 17B, the transition layer 38 has a three-layer structure including the thin film layer 33, the electroless plating film 36, and the electrolytic plating film 37. It is configured.

Next, a method of manufacturing a semiconductor device according to the second manufacturing method described above with reference to FIG. 17B will be described with reference to FIGS.

(1) First, the wiring 21 and the die pad 22 are formed on the silicon wafer 20A shown in FIG. 15A (FIG. 15B). (2) Next, a passivation film 24 is formed on the die pad 22 and the wiring (FIG. 15C).

(3) By performing physical vapor deposition such as vapor deposition and sputtering on the silicon wafer 20A, a conductive metal film (first thin film layer) 33 is formed on the entire surface (FIG. 15).
(D)). The thickness is preferably in the range of 0.001 to 2.0 μm. If it is below the range, a thin film layer cannot be formed on the entire surface. If it is higher than this range, the thickness of the formed film will vary. The optimal range is from 0.01 to 1.0 μm. Metals to be formed include tin, chromium, titanium, nickel,
It is preferable to use one selected from zinc, cobalt, gold, and copper. These metals serve as a protective film for the die pad and do not degrade the electrical characteristics. In the second manufacturing method, the first thin film layer 33 is formed of chromium.

(4) Sputtering is performed on the first thin film layer 33.
An electroless plating layer (second thin film layer) 36 is laminated by vapor deposition and electroless plating (FIG. 16A). The thickness is 0.0
The thickness is preferably 1 to 5 μm, particularly preferably 0.1 to 3.0 μm. In this case, the metal that can be laminated is preferably selected from nickel, copper, gold, and silver. In particular, it is good to form with either copper or nickel. Copper is inexpensive and has good electrical conductivity. Nickel has good adhesion to a thin film and is unlikely to cause peeling or cracking. Second
In the manufacturing method described above, the second thin film layer 36 is formed by electroless copper plating. Desirable combinations of the first thin film layer and the second thin film layer are chromium-copper, chromium-nickel, titanium-copper, and titanium-nickel. It is superior to other combinations in terms of bonding to metals and electrical conductivity.

(5) Then, a resist layer is formed on the second thin film layer 3
6 is formed. A mask (not shown) is placed on the resist layer, and after exposure and development, a plating resist 35 is formed.
To form a non-formed portion 35a. Thick layer (electrolytic plating film) on the non-formed portion 35a of the resist layer by applying electrolytic plating
37 are provided (FIG. 16B). Examples of the type of plating formed include copper, nickel, gold, silver, zinc, and iron. Since the electrical characteristics, economy, and the conductor layer which is a build-up to be formed later are mainly made of copper, copper is preferably used. In the second manufacturing method, copper is used. The thickness is 1
It is preferably in the range of 20 μm.

(6) After removing the plating resist 35 with an alkaline solution or the like, the electroless plating film 36 and the metal film 33 under the plating resist 35 are removed by using sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, The transition layer 38 is formed on the pad 22 of the IC chip by removing the copper oxide complex with an etching solution such as an organic acid salt (FIG. 16C).

(7) Next, a roughened surface 38α is formed by spraying an etching solution onto the substrate by spraying and etching the surface of the transition layer 38 (FIG. 17).
(A)).

(8) Finally, the semiconductor element 20 is formed by dividing the silicon wafer 20A on which the transition layer 38 is formed into individual pieces by dicing or the like (FIG. 1).
7 (B)).

[Third Manufacturing Method] A method of manufacturing the semiconductor device 20 according to the third manufacturing method will be described with reference to FIG. The structure of the semiconductor device according to the third manufacturing method is shown in FIG.
This is almost the same as the first manufacturing method described above with reference to FIG. However, in the first manufacturing method, the transition layer 38 was formed by forming the thickening layer 37 in the non-resist forming portion using a semi-additive process. On the contrary,
In the third manufacturing method, a transition layer 38 is formed by forming a thick layer 37 uniformly by using a full additive process, providing a resist, and removing the resist non-formed portion by etching.

The manufacturing method of the third manufacturing method will be described with reference to FIG. (1) As described above with reference to FIG. 12B in the first manufacturing method, physical vapor deposition such as vapor deposition or sputtering is performed on the silicon wafer 20A to form a conductive metal film 33 on the entire surface. (FIG. 18A). Its thickness is 0.
The range of 001 to 2.0 μm is good. If it is below the range, a thin film layer cannot be formed on the entire surface. If it is higher than this range, the thickness of the formed film will vary. The optimum range is preferably formed in the range of 0.01 to 1.0 μm. The metal to be formed is tin,
It is preferable to use one selected from chromium, titanium, nickel, zinc, cobalt, gold, and copper. These metals serve as a protective film for the die pad and do not degrade the electrical characteristics. In the third manufacturing method, the thin film layer 33
Is formed by chromium.

(2) A thick layer (electrolytic plating film) 37 is uniformly provided on the thin film layer 33 by electrolytic plating (FIG. 1).
8 (B)). Examples of the type of plating formed include copper, nickel, gold, silver, zinc, and iron. Since the electrical characteristics, economy, and the conductor layer, which is a build-up formed later, are mainly made of copper, copper is preferably used. In the third manufacturing method, copper is used. The thickness is preferably in the range of 1 to 20 μm. If the thickness is larger than that, an undercut occurs during the etching described later, and a gap may be generated at the interface between the formed transition layer and the via hole.

(3) Thereafter, a resist layer 35 is formed on the thick layer 37 (FIG. 18C).

(4) The metal film 33 and the thickening layer 37 where the plating resist 35 is not formed are made of sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, cupric complex-organic acid salt or the like. After the removal by the etchant, the plating resist 35 is peeled off to form a transition layer 38 on the pad 22 of the IC chip (FIG. 18D). The subsequent steps are:
The description is omitted because it is similar to the first manufacturing method.

[Fourth Manufacturing Method] A method of manufacturing the semiconductor device 20 according to the fourth manufacturing method will be described with reference to FIG. In the semiconductor device according to the third manufacturing method described above with reference to FIG.
3 and an electrolytic plating film 37. On the other hand, in the fourth manufacturing method, as shown in FIG. 19D, the transition layer 38 has a three-layer structure including the thin film layer 33, the electroless plating film 36, and the electrolytic plating film 37. It is configured.

The manufacturing method of the fourth manufacturing method will be described with reference to FIG. (1) Similar to the second manufacturing method described with reference to FIG. 16A in the first manufacturing method, the second thin film layer is formed on the first thin film layer 33 by sputtering, vapor deposition, and electroless plating. 36 are laminated (FIG. 19A). In this case, the metal that can be laminated is preferably selected from nickel, copper, gold, and silver. In particular, it is good to form with either copper or nickel. Copper is inexpensive and has good electrical conductivity. Nickel has good adhesion to a thin film and is unlikely to cause peeling or cracking. In the fourth manufacturing method, the second thin film layer 36 is formed by electroless copper plating. A desirable combination of the first thin film layer and the second thin film layer is chromium-
Copper, chromium-nickel, titanium-copper, and titanium-nickel. It is superior to other combinations in terms of bonding to metals and electrical conductivity.

(2) The second thin film layer 36 is formed by electrolytic plating.
A thick layer (electrolytic plating film) 37 is uniformly provided on the substrate (FIG. 19B).

(3) Thereafter, a resist layer 35 is formed on the thick layer 37 (FIG. 19C).

(4) The first thin film layer 33, the second thin film layer 36, and the thickening layer 37 where the plating resist 35 is not formed are formed of sulfuric acid-hydrogen peroxide, ferric chloride, cupric chloride, After removal with an etching solution such as a copper complex-organic acid salt, the plating resist 35 is peeled off to form a transition layer 38 on the pad 22 of the IC chip (FIG. 19).
(D)). Subsequent steps are the same as in the first manufacturing method, and a description thereof will be omitted.

B. Multilayer Printed Wiring Board Incorporating Semiconductor Element Next, according to the fourth embodiment shown in FIG. 21 in which the semiconductor element (IC chip) 20 of the above-described first to fourth manufacturing methods is housed in a through hole of a core substrate. A method for manufacturing a multilayer printed wiring board will be described with reference to FIG.

(1) First, an insulating resin substrate (core substrate) 30 in which a prepreg obtained by impregnating a resin such as epoxy into a core material such as glass cloth is used as a starting material (FIG. 20).
(A)). Next, a recess 32 for accommodating an IC chip is formed on one surface of the core substrate 30 by counterboring.
(B)). Here, the concave portion is formed by counterboring, but a core substrate having an accommodating portion can be formed by laminating an insulating resin substrate having an opening and a resin insulating substrate having no opening.

(2) Thereafter, an adhesive material 34 is applied to the recess 32 using a printing machine. At this time, besides coating,
Potting may be performed. Next, the IC chip 20
A and 20B are placed on the adhesive material 34 (FIG. 20C).
reference).

(3) Then, the IC chips 20A and 20B
Is pressed or hit to completely house the recess 32 (see FIG. 20D). Thereby, the core substrate 3
0 can be smoothed. Subsequent steps are the same as those in the first embodiment described above with reference to FIGS.

[Fifth Embodiment] Next, a printed wiring board according to a fifth embodiment of the present invention will be described with reference to FIG. As shown in FIG. 23, in the fifth embodiment,
In the recess 32 of the core substrate 30, the transition layer 3
8 together with an IC chip (CPU) 20A and an IC chip (cache memory) 20B, a chip capacitor 19A, a chip resistor 19B, and a chip inductance 1
9C is accommodated.

A method for manufacturing a printed wiring board according to the fifth embodiment will be described with reference to FIG. (1) First, a concave portion 32 for accommodating an IC chip is formed on one surface of an insulating resin substrate (core substrate) 30 in which a prepreg obtained by impregnating a resin such as epoxy with a core material such as glass cloth is laminated (see FIG. 22 (A)).

(2) Thereafter, an adhesive material 34 is applied to the recess 32 using a printing machine. At this time, besides coating,
Potting may be performed. Next, the IC chip 20
A, 20B, chip capacitor 19A, chip resistor 19
B, the chip inductance 19C is placed on the adhesive material 34 (see FIG. 22B).

(3) Then, the IC chips 20A and 20A
B, the top surfaces of the chip capacitor 19A, the chip resistor 19B, and the chip inductance 19C are pushed or hit to completely house the recesses 32 (see FIG. 22C).
Subsequent steps are the same as in the first embodiment described above with reference to FIGS.

[Sixth Embodiment] Next, a printed wiring board according to a sixth embodiment will be described with reference to FIG. As shown in FIG. 24B, in the sixth embodiment, an IC chip (CPU) 20 is provided in a concave portion 32 of a core substrate 30.
A, an IC chip (cache memory) 20B, a chip capacitor 19A, a chip resistor 19B, and a chip inductance 19C are accommodated. In the sixth embodiment, an IC chip (CPU) 20A, an IC chip (cache memory) 20B, a chip capacitor 19A, a chip resistor 19B, and a chip inductance 19C are provided below.
A connection layer 31 for adjusting the height is provided.

A method for manufacturing a printed wiring board according to the sixth embodiment will be described with reference to FIG. (1) IC chip (CPU) 20A on which transition layer 38 has been formed in advance, IC chip (cache memory)
20B, chip capacitor 19A, chip resistor 19B,
A connection layer 31 for equalizing the height is provided below the chip inductance 19C, and is accommodated in the recess 32 of the core substrate 30. Subsequent steps are the same as in the first embodiment described above with reference to FIGS.

[Seventh Embodiment] Next, a printed wiring board according to a seventh embodiment will be described with reference to FIGS. In the first to sixth embodiments described above, the IC chip and the like are accommodated in the recess. On the other hand, in the seventh embodiment, as shown in FIG. 27, an IC chip is housed in a resin substrate in which a through hole 32 is formed.

A method of manufacturing a printed wiring board according to the seventh embodiment will be described with reference to FIGS. (1) A starting material is a 0.5 mm thick insulating resin substrate 30A obtained by laminating and curing a prepreg in which a core material such as a glass cloth is impregnated with a resin such as BT (bismaleimide triazine) resin or epoxy (see FIG. 25 (A)). First, a through hole 32 for accommodating an IC chip is formed in the insulating resin substrate 30A (FIG. 25B). The IC chips 20A and 20B of the above-described first to fourth manufacturing methods are accommodated in the through holes 32 (see FIG. 25C).

(3) Then, the IC chips 20A and 20B
Resin substrate (core substrate) 30B having a thickness of 0.2 mm and cured by laminating a core material such as glass cloth or a prepreg impregnated with a resin such as BT or epoxy. Are laminated with an uncured prepreg 30C (0.1 mm thick) in which a core material such as glass cloth is impregnated with a resin such as epoxy (FIG. 26).
(A)). Here, the resin substrate 30B in which the core material is impregnated with the resin is used, but a resin substrate having no core material may be used. Further, instead of the prepreg, various thermosetting resins or a sheet obtained by impregnating a core material with a thermosetting resin and a thermoplastic resin can be used.

(4) Stainless steel (SUS) press plate 10
At 0A and 100B, the above-described laminate is pressed from above and below. At this time, the epoxy resin 3 is removed from the prepreg 30C.
0α exudes, the through hole 32 and the IC chips 20A, 20B
Between the IC chips 20A,
Cover the top surface of OB. Thereby, the IC chips 20A,
0B and the upper surface of the insulating resin substrate 30A become completely flat. (FIG. 26 (B)). For this reason, when forming the build-up layer, via holes and wiring can be appropriately formed, and the reliability of wiring of the multilayer printed wiring board can be improved.

(5) After that, the uncured epoxy resin 30α is cured by heating, so that the IC chips 20A,
26B is formed to house the core substrate 30 (FIG. 26).
(C)). Subsequent steps are the same as in the first embodiment, and a description thereof will be omitted.

[Eighth Embodiment] A printed wiring board according to an eighth embodiment will now be described with reference to FIGS. In the first to sixth embodiments described above, the IC chip and the like are accommodated in the recess. On the other hand, in the eighth embodiment, as shown in FIG. 29, the IC chips 20A and 20B are mounted on the heat sink 30D.

A method for manufacturing a printed wiring board according to the eighth embodiment will be described. (1) A heat conductive adhesive 29 is printed on a heat sink 30D (FIG. 28A) made of a metal such as aluminum or stainless steel or ceramic (FIG. 28B). here,
The heat conductive adhesive 29 is thickly printed at a position where a thin electronic component, a semiconductor element or the like is mounted (here, a position of a chip capacitor). On the other hand, the positions where thick electronic components and semiconductor elements are mounted (here, IC chips 20A and 20A)
(Position B), the heat conductive adhesive 29 is printed thinly.
In addition, as a heat conductive adhesive, average particle diameter 2-5 micrometers
Can be used.

(2) Next, on the heat conductive adhesive 29,
IC chip 20A, 2 on which transition layer 38 is formed
0B and the chip capacitor 19 (FIG. 28)
(C)). Note that it is also possible to form a transition layer on the terminal of the chip capacitor 19.

(3) The heat sink 30D and the insulating resin substrate 30A provided with the opening 32 for accommodating the IC chips 20A and 20B and the chip capacitor 19 are connected to the opening for accommodating the IC chips 20A and 20B and the chip capacitor 19. Uncured prepreg 30C (thickness 0.3 mm) obtained by impregnating a resin such as epoxy into a core material such as a glass cloth provided with 30 h.
(FIG. 29A). And stainless steel (SUS) press plates 100A, 100B
Then, the above-described laminate is pressed from above and below. At this time, the epoxy resin 30α seeps out of the prepreg 30C to fill the space between the through hole 32 and the IC chips 20A and 20B and cover the upper surfaces of the IC chips 20A and 20B. Thereby, the upper surfaces of the IC chips 20A and 20B and the insulating resin substrate 30A become completely flat. (FIG. 29
(B)). Therefore, when forming the build-up layer,
Via holes and wiring can be properly formed, and the reliability of wiring of a multilayer printed wiring board can be improved.

(4) Thereafter, heating is performed to cure the uncured epoxy resin 30α, so that the IC chips 20A,
Core substrate 30 containing OB and chip capacitor 19
To form Subsequent steps are the same as in the first embodiment, and a description thereof will be omitted.

In the printed wiring board manufactured in the above-described embodiment, the electric conductivity is stable, and particularly, disconnection or the like due to disconnection between the die pad and the via hole does not occur. In addition, the adhesive layer in the cavity stabilizes the mounting of the semiconductor element and other electronic components, so that the behavior is reduced even during a heat cycle, and the semiconductor element and other electronic components are removed from the cavity of the printed wiring board. It does not protrude, and the occurrence of peeling or cracking of the interlayer insulating layer or disconnection or cracking at the connection portion with the terminal is eliminated.

[0144]

According to the present invention, a semiconductor element is housed in a printed wiring board.
Since it is housed, built-in or embedded, the total thickness can be reduced, so that it can be housed in an electronic device with a thinner housing. In addition, since a plurality of semiconductor elements are provided, the length of the wiring to be connected is short, so that a printed wiring board with high functionality and high density is obtained. Since the transition layer was formed on the semiconductor element, the formation of the via hole in the interlayer insulating layer was stabilized, and the electrical connectivity was improved. In addition, since no lead component is used, the occurrence of various problems is reduced.

[Brief description of the drawings]

FIGS. 1A, 1B, and 1C are manufacturing process diagrams of a multilayer printed wiring board according to a first embodiment of the present invention.

FIGS. 2A, 2B, and 2C are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 3A, 3B, and 3C are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 4A, 4B, and 4C are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 5A, 5B, and 5C are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 6A, 6B, and 6C are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 7 is a sectional view of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 8A, 8B, and 8C are manufacturing process diagrams of a multilayer printed wiring board according to a second embodiment of the present invention.

FIG. 9 is a sectional view of a multilayer printed wiring board according to a second embodiment of the present invention.

FIG. 10A is a manufacturing process diagram of a multilayer printed wiring board according to a third embodiment of the present invention, and FIG. 10B is a cross-sectional view of the multilayer printed wiring board.

FIGS. 11A, 11B, and 11C are manufacturing process diagrams of a semiconductor device according to a first manufacturing method of a fourth embodiment of the present invention.

FIGS. 12A, 12B, and 12C are manufacturing process diagrams of a semiconductor device according to a first manufacturing method of a fourth embodiment of the present invention.

FIGS. 13A and 13B are manufacturing process diagrams of a semiconductor device according to a first manufacturing method of a fourth embodiment of the present invention.

FIG. 14A is a plan view of a silicon wafer according to a fourth embodiment of the present invention, and FIG. 14B is a plan view of a singulated semiconductor element.

FIGS. 15A, 15B, and 15C are manufacturing process diagrams of a semiconductor device according to a second manufacturing method of the fourth embodiment of the present invention.

FIGS. 16A, 16B and 16C are manufacturing process diagrams of a semiconductor device according to a second manufacturing method of the fourth embodiment of the present invention.

17A and 17B are manufacturing process diagrams of a semiconductor device according to a second manufacturing method of the fourth embodiment of the present invention.

FIGS. 18A, 18B, 18C and 18D are manufacturing process diagrams of a semiconductor device according to a third manufacturing method of the fourth embodiment of the present invention.

FIGS. 19 (A), (B), (C) and (D) are manufacturing process diagrams of a semiconductor device according to a fourth manufacturing method of the fourth embodiment of the present invention.

FIG. 20 (A), (B), (C), (D), (E)
FIG. 9 is a manufacturing process diagram of the multilayer printed wiring board according to the fourth embodiment of the present invention.

FIG. 21 is a sectional view of a multilayer printed wiring board according to a fourth embodiment.

FIGS. 22A, 22B, and 22C are manufacturing process diagrams of a multilayer printed wiring board according to a fifth embodiment of the present invention.

FIG. 23 is a sectional view of a multilayer printed wiring board according to a fifth embodiment.

FIG. 24A is a manufacturing process diagram of the multilayer printed wiring board according to the sixth embodiment, and FIG. 24B is a cross-sectional view.

FIGS. 25A, 25B, and 25C are manufacturing process diagrams of the multilayer printed wiring board according to the seventh embodiment of the present invention.

FIGS. 26A, 26B, and 26C are manufacturing process diagrams of the multilayer printed wiring board according to the seventh embodiment of the present invention.

FIG. 27 is a sectional view of a multilayer printed wiring board according to a seventh embodiment of the present invention.

FIGS. 28A, 28B, and 28C are manufacturing process diagrams of the multilayer printed wiring board according to the eighth embodiment of the present invention.

FIGS. 29A and 29B are manufacturing process diagrams of the multilayer printed wiring board according to the eighth embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 20A IC chip (CPU) 20B IC chip (cache memory) 22 die pad 24 passivation film 30 core substrate 32 through hole 36 resin layer 38 transition layer 50 interlayer resin insulating layer 58 conductive circuit 60 via hole 70 solder resist layer 76 solder bump 90 daughter board 96 Conductive connection pin 97 Conductive adhesive 120 IC chip 150 Interlayer resin insulation layer 158 Conductor circuit 160 Via hole

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 25/18 H05K 1/11 H H05K 1/09 1/18 R 1/11 3/24 D 1/18 H01L 25/04 Z 3/24 F term (reference) 4E351 AA02 BB01 BB23 BB24 BB26 BB32 BB33 BB38 BB49 CC01 CC06 DD04 DD05 DD06 DD11 DD12 DD17 DD19 GG11 GG13 5E317 AA24 BB02 BB11 BB12 BB13 CD05 5E336 AA08 AA11 BB03 BB15 BC26 BC31 CC32 CC55 GG14 5E343 AA02 AA12 AA17 BB08 BB17 BB23 BB24 BB25 BB34 BB35 BB38 BB44 BB45 BB61 BB71 DD22 DD32 EE22 EE52 GG01 GG20 CC15A06A33 CCB DD22 DD32 EE33 FF04 FF45 GG15 GG17 GG22 GG27 GG28 HH11 HH13 HH24 HH25

Claims (12)

[Claims] 1. A printed wiring board in which an interlayer insulating layer and a conductive circuit are repeatedly laminated on a substrate to make an electrical connection through a via hole, wherein the substrate has a cavity formed therein. , A printed wiring board in which two or more semiconductor elements are housed, housed or embedded. 2. A printed wiring board in which an interlayer insulating layer and a conductor circuit are repeatedly laminated on a substrate to make electrical connection via via holes, wherein the substrate has a cavity formed therein. A printed wiring board in which two or more semiconductor elements having a transition layer are accommodated, accommodated or embedded. 3. The semiconductor device according to claim 1, wherein at least one of the semiconductor elements includes:
The printed wiring board according to claim 1, wherein the printed wiring board is a semiconductor element having an arithmetic function (CPU), at least one of which is a semiconductor element having a storage function (memory). 4. The printed wiring board according to claim 1, wherein the cavity has an adhesive for bonding a semiconductor element and a resistor, a capacitor, or an inductance. 5. The method of claim 1, wherein the transition layer comprises at least two layers.
The printed wiring board according to any one of claims 2 to 4, which has at least one layer. 6. The lowermost layer of the transition layer includes tin, chromium, titanium, nickel, zinc, cobalt, gold,
The printed wiring board according to any one of claims 2 to 5, wherein the printed wiring board is laminated with at least one kind selected from copper. 7. The printed wiring board according to claim 2, wherein the uppermost layer of the transition layer is selected from nickel, copper, gold, and silver. 8. The transition layer includes a first thin film layer,
The printed wiring board according to any one of claims 2 to 7, wherein the printed wiring board is formed of a second thin film layer and a thick layer. 9. The method according to claim 8, wherein the first thin film layer of the transition layer is laminated with at least one selected from the group consisting of tin, chromium, titanium, nickel, zinc, cobalt, gold and copper. The printed wiring board as described. 10. The printed wiring board according to claim 8, wherein the second thin film layer of the transition layer is selected from nickel, copper, gold, and silver. 11. The printed wiring board according to claim 1, wherein the cavity is filled with an adhesive layer. 12. The printed wiring board according to claim 11, wherein the thickness of the adhesive varies depending on the thickness of the semiconductor element and the electronic component in the cavity.