JP2002246581A - Image sensor and method of manufacturing the same - Google Patents

Abstract

(57) [Problem] To increase the unit area of a photodiode without lowering the degree of integration. SOLUTION: In a unit pixel portion, a read transistor 31, a reset transistor 32, an amplifying transistor 33, and a select transistor 34 are formed by forming a channel region 23 vertically formed on a side surface of a trench 22 formed on a surface of a semiconductor substrate 21. It has a vertical transistor. Therefore, when a predetermined design rule is applied, the space between the element isolation region 36 and the read transistor 31 can be increased. Thus, by reducing the area occupied by the transistor region, the area occupied by the photodiode can be increased without lowering the integration degree, and the light sensitivity characteristics can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a submicron C
CMOS using MOS (complementary metal oxide semiconductor) technology
The present invention relates to an image sensor and a method for manufacturing the same.

[0002]

2. Description of the Related Art In addition to the existing image sensor market, a CMOS image sensor is a digital still camera (DS).
Demands in the fields of C), mobile phones, personal computers (PC), personal digital assistants (PDAs) and the like are rapidly expanding, and their technical importance is increasing.

The above-mentioned CMOS image sensor is a CCD (Charge Coup) which is widely used at present as an image sensor.
Compared to an image sensor (led Device), it has excellent features in single power supply, low voltage drive, and low power consumption. Further, the driving method is simple, and a versatile scanning method can be put to practical use, and the signal processing circuit can be integrated on a single chip, so that the product can be reduced in size and weight. Furthermore,
Since a CMOS technology similar to the logic process is used, a dedicated manufacturing line such as a CCD image sensor is not required even during manufacturing.

The above CMOS image sensor is also the above CCD.
In the same manner as described above, the number of pixels is increasing, and a configuration in which a photoelectric conversion element and a transistor are provided on the same substrate is employed. The signal charge generated by the photoelectric conversion element modulates the potential of the signal charge accumulating portion, and the potential modulates the amplifying transistor inside the pixel to provide an amplifying function inside the pixel.

The photodiode of the photoelectric conversion unit in the CMOS image sensor also has a structure embedded in the substrate and a structure in which the substrate surface of the photodiode is shielded by a P-type semiconductor layer, as in the case of the CCD. Recently it is becoming mainstream. FIG. 9 shows the conventional C
2 shows a cross section of a unit pixel portion in a MOS image sensor. In FIG. 9, the unit pixel portion is a P ⁺ silicon substrate 1
Element isolation region 3 in upper P-type epitaxial layer 2
Is formed from four transistors 4 to 7 and a photodiode 8 formed in a region defined by. Then, the photodiode 8 includes a P-type semiconductor layer 9 on the substrate surface.
And an N ^- region 10 thereunder. Further, each of the transistors 4 to 7 has N as a source / drain region.
⁺ Regions 11 and 12 are formed.

In the CMOS image sensor having the above configuration,
As described above, since the surface of the photodiode 8 is shielded by the P-type semiconductor layer 9, it is possible to prevent a current generated from a defect level existing on the substrate surface of the photodiode 8 from flowing into the photodiode 8. As a result, defects such as white scratches can be greatly reduced.

Reference numeral 13 denotes a channel stopper region,
14 is a gate insulating film, 15 is a gate electrode,
16 is a CVD (Chemical Vapor Deposition) oxide film, and 17 is P
^- it is well.

[0008]

However, in the above-mentioned conventional CMOS image sensor, the buried photodiode 8 is formed in a certain area between the readout transistor 4 and the element isolation region 3, so that the buried photodiode 8 is formed. In order to increase the unit area of No. 8, there is a problem that the degree of integration must be reduced. In addition, since the area of the embedded photodiode 8 is reduced as the design rule is miniaturized, there is a problem that the sensitivity is significantly reduced with the miniaturization.

In order to increase the unit area without lowering the degree of integration, there has been proposed a photodiode formed along a wall surface of a trench formed in a semiconductor substrate.
(JP-A-2000-31455). However, in this case, there is a concern that junction leakage current may increase due to etching damage during the formation of the trench or stress due to an insulating film or the like filling the trench. Furthermore, it is difficult to accurately form a P / N / P junction on the concave / convex portion, and there is a problem in that when oblique ion implantation is used, the throughput is increased and the production efficiency is significantly deteriorated.

It is an object of the present invention to provide a CM capable of increasing the unit area of a photodiode using a predetermined design rule without lowering the degree of integration.
An object of the present invention is to provide an OS image sensor and a manufacturing method thereof.

[0011]

According to a first aspect of the present invention, a photoelectric conversion element formed on a semiconductor substrate and selection, amplification and reset of a signal charge generated by the photoelectric conversion element are performed. In an image sensor having at least three transistors as a unit pixel, a channel region of the transistor is arranged in a direction perpendicular to a surface of the semiconductor substrate.

According to the above configuration, in the unit pixel, the channel regions of at least three transistors for selecting, amplifying, and resetting the signal charge generated by the photoelectric conversion element are arranged in a direction perpendicular to the surface of the semiconductor substrate. Have been. Therefore, if the same design rule as that of the conventional image sensor is applied, the area occupied by the transistor region is reduced, the area occupied by the photoelectric conversion element is increased, and the light sensitivity characteristics are improved. Alternatively, if the same light sensitivity characteristics as those of a conventional image sensor are obtained, the degree of integration is improved.

Further, the image sensor of the first embodiment has
In the image sensor according to the first aspect, the transistor includes a channel region formed on a side surface of a concave portion formed on a surface of the semiconductor substrate, and a gate insulating film formed on a surface of the concave portion including the channel region. When,
A gate electrode formed on the channel region on the side surface of the recess through the gate insulating film, and a high-concentration impurity region formed on the surface of the semiconductor substrate including the bottom surface of the recess adjacent to the channel region Wherein the photoelectric conversion element is a photodiode formed on the semiconductor substrate and having at least a junction of a first conductivity type and a second conductivity type.

According to this embodiment, the channel region is formed on the side surface of the concave portion formed on the surface of the semiconductor substrate, and the gate insulating film and the gate electrode are sequentially formed on the channel region on the side surface of the concave portion. . In this manner, the channel region is arranged in a direction perpendicular to the surface of the semiconductor substrate, and the transistor is easily formed by a conventional film forming technique, doping technique, photo etching technique and the like.

Further, the image sensor of the second embodiment is
In the image sensor according to the first aspect of the invention, the photodiode is formed on a surface of the semiconductor substrate, the first conductive layer including a high-concentration impurity layer that does not deplete a substrate interface, and a photodiode immediately below the first conductive layer. The first conductive layer is formed of a second conductive layer having a conductivity type different from that of the first conductive layer, and a third conductive layer formed immediately below the second conductive layer and having the same conductivity type as the first conductive layer. It is characterized by:

According to this embodiment, the surface portion of the semiconductor substrate is shielded by the first conductive layer made of a high-concentration impurity layer that does not deplete the substrate interface. Therefore,
A current generated from a defect level existing on the surface of the semiconductor substrate is prevented from flowing into the photodiode, and defects such as white scratches are reduced.

Further, a method of manufacturing an image sensor according to a second aspect of the present invention includes a step of forming a plurality of recesses on a surface of a semiconductor substrate, and filling each of the recesses with an insulating film to form an element isolation region. Removing an insulating film filled in the concave portion other than the element isolation region for defining a unit pixel, and forming a channel region on a side surface of the concave portion after the insulating film is removed; and Forming a gate insulating film on the surface including the channel region, forming a gate electrode on the channel region on the side surface of the concave portion via the gate insulating film, and forming the gate electrode adjacent to the channel region. Forming a high concentration impurity region on the surface of the semiconductor substrate including the bottom of the concave portion.

According to the above configuration, the channel region of the transistor that performs a read operation including selection, amplification, and reset of the signal charge generated by the photoelectric conversion element is arranged in a direction perpendicular to the surface of the semiconductor substrate. . Therefore, if the same design rule as that of the conventional image sensor is applied, the area occupied by the transistor region is reduced, the area occupied by the photoelectric conversion element is increased, and the light sensitivity characteristics are improved. Alternatively, if the same light sensitivity characteristics as those of a conventional image sensor are obtained, the degree of integration is improved.

In the method for manufacturing an image sensor according to the first embodiment, in the method for manufacturing an image sensor according to the second aspect of the present invention, the step of forming the gate electrode may include the steps of: The gate electrode is formed in a self-aligned manner by forming a conductive layer on the substrate and etching back the conductive layer.

According to this embodiment, the formation of the gate electrode is performed in a self-aligned manner with respect to the side wall of the recess.
Thus, the gate electrode is formed without increasing the misalignment and the number of manufacturing steps. Further, by using a relatively simple method, it is possible to easily cope with miniaturization.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. FIG. 1 is a cross-sectional view illustrating a configuration of a unit pixel portion in a CMOS image sensor that is the image sensor according to the present embodiment. FIG. 2 is a circuit diagram of the unit pixel section.

As shown in FIG. 1, the CMOS image sensor according to this embodiment mainly includes a semiconductor substrate 21.
And four transistors including a read transistor 31, a reset transistor 32, an amplification transistor 33, and a selection transistor 34 formed on the side surface of the concave portion 22 formed on the surface of the semiconductor substrate 21 and at least the first conductivity type formed on the surface of the semiconductor substrate 21. A photodiode 29 comprising a junction of the region 27 and the second conductivity type region 28.

The four transistors 31 to 3
4 is a channel region 2 formed on the side surface of the recess 22.
3 and semiconductor substrate 2 including channel region 23 of recess 22
1, a gate insulating film 24 formed on the surface of
A gate electrode 25 formed on the side channel region 23 via the gate insulating film 24 and a high-concentration impurity region 26 formed on the surface of the semiconductor substrate 21 including the bottom surface of the concave portion 22 so as to be adjacent to the channel region 23 Consists of
Incidentally, 36 is an element isolation region, and 37 is a channel stopper.

The semiconductor substrate 21 is not particularly limited as long as it is a semiconductor substrate used in manufacturing an ordinary semiconductor device. For example, a semiconductor substrate of silicon, germanium, etc., SiC, GaAs, InGaAs, etc. And the like. Among them, a silicon substrate is preferable, and a substrate such as an SOI (silicon-on-insulator) substrate, a bonded SOI or SIMOX (separation by implanted oxygen) may be used.

Each trench 22 including a concave portion (trench) for element isolation formed on the semiconductor substrate 21 is formed such that its side wall has an angle of 90 degrees with respect to the surface of the semiconductor substrate 21. Alternatively, the side wall may be formed to have a taper of about 85 degrees. Note that the depth of the trench 22 can be appropriately adjusted depending on the gate length of the transistor to be obtained, element isolation withstand voltage, and the like.
It is preferably about 0 nm to 700 nm. Further, after the trench 22 is formed, the surface and bottom corners are rounded to suppress the effects of electric field concentration and generation of crystal defects.
It is desirable to perform oxidation of about 0 nm.

A well 35 and a channel region 23 are formed by ion implantation in a region of the semiconductor substrate 21 where the amplifying transistor 33 and the selection transistor 34 are to be formed. At that time, the channel region 23
It is formed on the side wall of the trench 22 in the well 35. The channel regions 23 of the read transistor 31 and the reset transistor 32 are formed on the sidewalls of the trench 22 outside the well 35. The gate electrodes 25 of the transistors 31 to 34 are formed after forming the gate insulating film 24 so as to cover the surface of the semiconductor substrate 21 including the trench 22.

The gate insulating film 24 can be usually formed by forming a material used as a gate insulating film to a desired thickness by thermal oxidation or the like. The thickness at this time is desirably, for example, about 3 nm to 10 nm.

The gate electrode 25 may be formed of any material as long as it functions as an electrode.
It is desirable to form polysilicon having an impurity concentration on the order of E + 20 / cm ³ . The film thickness is
Although there is no particular limitation as long as the transistor can function as a gate electrode, it is necessary to appropriately adjust the length of a low-concentration region of a transistor to be obtained, electric characteristics, and the like. The thickness of the gate electrode 25 is, for example, 100
It is desirably about nm to 200 nm.

The gate electrode 25 can be processed in a self-aligned manner by etching if the trench 22 is formed in advance at a depth that assumes the channel region 23 of the transistor. However, in many cases, it is necessary to define transistors in regions other than the pixel portion having different channel lengths, and thus it is better to use normal photoetching. In that case, the gate length can be appropriately formed on the front surface side of the semiconductor substrate 21 in addition to the side surface portion of the trench 22. Each of the transistors 31 to 3
It is preferable to form a low-concentration impurity region 30 between the high-concentration impurity region (drain region) 26 disposed on one side of the fourth channel region 23 and the channel region 23. In this case, the low-concentration impurity region 30 is formed in a self-aligned manner immediately below the gate electrode 25 formed later in a sidewall shape by ion-implanting the semiconductor substrate 21 in the vertical direction before the gate electrode 25 is formed. Can be formed. The high-concentration impurity regions 26 and 27 serving as source / drain regions are formed at the bottom of the trench 22 serving as each transistor, the surface of the semiconductor substrate 21 between the trenches 22, and the portion serving as the photodiode 29.

The photodiode 2 serving as a photoelectric conversion unit
Generally, an N ⁺ / P junction is widely used as 9, but its structure can be appropriately changed according to the purpose and device specifications. For example, as in the present embodiment, a P ⁺ / N ⁻ / P structure in which the surface of the semiconductor substrate 21 is shielded by a P-type semiconductor layer may be used. In this case, by shielding with a P-type semiconductor layer, it is possible to prevent a current generated from a defect level existing on the substrate surface of the photodiode from flowing into the photodiode,
Defects such as white scratches can be reduced.

Next, referring to FIG.
The operation of the MOS image sensor will be described. First,
The voltage level of the reset line 41 is set to “H” to turn on the reset transistor 32, and the charge remaining on the wiring is discharged to the drain line 42. After that, the reset transistor 32 is turned off. Next, by turning on the read transistor 31, the photodiode 29 is turned on.
The carriers generated by the photoelectric conversion flow into the gate of the amplification transistor 33. At this time, when the read transistor 31 is turned off, charges are accumulated in the gate of the amplification transistor 33, and the amplification transistor 33 is turned on. At the same time, when the level of the address line 43 is set to "H" to turn on the selection transistor 34, a signal is read out to the signal line 44.

Hereinafter, a method of manufacturing the CMOS image sensor having the above configuration will be described. As shown in FIG.
The MOS image sensor is formed on a P-type epitaxial layer 52 formed on a P ⁺ silicon substrate 51 having a specific resistance of 0.01 Ωcm to 0.1 Ωcm. The P-type epitaxial layer 52 has a specific resistance of 10 Ωcm to 20 Ωcm, and a thickness of 5 μm to 10 μm.

First, a trench 53 is formed on the surface of the P-type epitaxial layer 52 to a depth of 300 to 1000 nm. At this time, a mask in which an insulating film and a silicon nitride film are deposited on the P-type epitaxial layer 52 is used as a mask at the time of trench etching, and the side walls of the trench 53 are substantially perpendicular to the surface of the P-type epitaxial layer 52. It is formed as follows. The reason for forming the side walls vertically is to form the transistors in the vertical direction with high precision in the manufacturing process. Next, the surface in the trench 53 is covered with the mask material at a high temperature of 1050 ° C. to 1100 ° C.
Oxidation is performed to a thickness of about 30 nm to about 30 nm, and the surface and bottom corners of the trench 53 are rounded to suppress effects such as electric field concentration and generation of crystal defects. After that, CVD as an insulating film
An element isolation region 54 is formed by embedding a silicon oxide film in the trench 53 by using a CMP (chemical mechanical polishing) method or the like. After that, the silicon nitride film and the insulating film used as the mask are sequentially removed. Thus, the state shown in FIG. 3 is reached.

Next, as shown in FIG. 4, the CVD silicon oxide film buried in the trench 53 in the region where the transistor in the pixel is formed is removed by etching using the photoresist 55 as a mask to form a P-type epitaxial film. The layer 52 is exposed. At the time of this etching, there is no fear of damaging the surface of the P-type epitaxial layer 52 and the wetness using buffered HF (BHF) or the like is considered in consideration of the fact that the inclination of the element isolation region boundary 54 ′ becomes gentle. Etching is preferred. It should be noted that a steep inclination of the element isolation region boundary portion 54 'is not preferable because a remaining film-forming material or the like easily occurs in a later step.

Next, using a photoresist (not shown) having an opening at the element isolation region 54, boron ions are implanted to form a channel stopper 58. Then, as shown in FIG. 5, 1E + 12 cm ^{−2 to} 1E + 13 cm in a region where the amplification transistor 64 and the selection transistor 65 are formed, using the photoresist 56 as a mask.
^A P-type well 57 is formed by implanting about ^-2 boron ions. After that, 1E + 12 cm ⁻² to 1E + 13 is obliquely applied to the side surface of the trench 53 as channel doping.
A channel region 59 is formed by implanting boron ions of about cm ⁻² . Further, using a photoresist (not shown) that opens the location of the trench 53 in a region where the read transistor 62 and the reset transistor 63 are formed, 1E + 12 cm ⁻² to 1E + 13 cm is obliquely applied to the side surface of the trench 53 as channel doping. ^A channel region 59 is formed by implanting about ⁻² adjacent ions.

Next, as shown in FIG.
After the film 60 is formed, the polysilicon which becomes the gate electrode 61 is formed.
In-situ doping using CVD method
It is formed with a film thickness of about 100 nm to 200 nm by the step.
During the polysilicon deposition, the gate insulating film
Non-doped polysilicon and 1E + 20 / cm on 60^Three About
Continuous with doped silicon that is next to the order of degrees
It is desirable to be formed. After that, the gate electrode 61
Defines the channel width and channel length of the transistor
Process using normal photo etching.
But must be processed in a self-aligned manner by etch back.
Can also. Further, as described above, each transistor 62
To 65 channel region 59 and one of the high-concentration impurity regions.
Low-concentration impurity region 66 is formed between the side (drain region)
Is preferred. In that case, the gate electrode 61 is formed.
Before that, ions are implanted in the vertical direction with respect to the semiconductor substrate 51.
As a result, the gate voltage
A low-concentration impurity region 66 is formed directly below the pole 61 in a self-aligned manner.
Can be achieved.

Thereafter, 1E + is applied to the formation region of the photodiode 67 on the surface of the P-type epitaxial layer 52 at 100 keV to 200 keV using a photoresist 68.
Ion implantation of phosphorus of about 12 cm ^{-2 to} 1E + 14 cm ^-2 and N
^- to form a region 69. Further, at 20 keV to 50 keV, about 1E + 13 cm ⁻² to 1E + 15 cm ⁻² of boron fluoride (BF)
₂₎ The ions are implanted, N ^- on the surfaces of the regions 69 ^{P +} region 7
0 is formed. In this case, ion implantation from an oblique direction is also performed so as to be implanted also into the side surface of the trench 53.

Next, as shown in FIG. 7, 1E + 15 cm ^{−2 at} 40 keV to 90 keV using a photoresist 71 in a region other than the photodiode 67 in the pixel portion.
About 5E + 15cm ^-2 arsenic is ion-implanted
An N ⁺ region (high concentration impurity region) 72 serving as a drain is formed.

Next, as shown in FIG. 8, a silicon oxide film 73 is deposited on the entire surface including the above-mentioned transistors 62 to 65 by CVD and flattened. After that, a contact hole 74 is opened in the silicon oxide film 73, a metal layer such as aluminum is laminated on the entire surface, and then photo-etching is performed to form a wiring 75.

As described above, in the unit pixel portion,
CMOS in which a read transistor 62, a reset transistor 63, an amplification transistor 64, and a selection transistor 65, each of which is a vertical transistor having a vertical channel region 59, are formed on side surfaces of a trench 53 formed on the surface of a P-type epitaxial layer 52. An image sensor is formed.

As described above, in the present embodiment, the readout transistors 31 and
62, the reset transistors 32 and 63, the amplifying transistors 33 and 64, and the select transistors 34 and 65 are connected to the trenches 22 and 53 formed on the surfaces of the semiconductor substrates 21 and 52.
Channel regions 23, 60 formed vertically on the side surfaces of
). Therefore, when a predetermined design rule is applied, the region between the element isolation regions 36 and 54 and the read transistors 31 and 62 is changed to the read transistors 4 and 4 as shown in FIG.
The width can be made wider than that of a conventional CMOS image sensor in which the reset transistor 7, the amplification transistor 5, and the selection transistor 6 are formed of horizontal transistors having a horizontal channel region. As a result, the area of the photodiodes 29 and 67 formed between the element isolation regions 36 and 54 and the read transistors 31 and 62 can be increased, and the sensitivity can be improved.

That is, according to the present embodiment, if the same design rule as that of the conventional CMOS image sensor is applied, the area occupied by the transistor region can be reduced and the area occupied by the photodiode can be increased.
Light sensitivity characteristics can be improved. In addition, conventional CM
If the same light sensitivity characteristic as that of the OS image sensor is obtained, the degree of integration can be increased.

At this time, each of the transistors 31, 62;
2, 63; 33, 64; 34, 65 gate electrodes 25, 61
Can be formed by processing into a sidewall shape by self-alignment using the steps of the trenches 22 and 53 formed in the base. In that case, the gate electrode 2
At the time of forming 5,61, misalignment and increase in the number of manufacturing steps can be eliminated. Further, the low concentration impurity region 3 is formed in the semiconductor substrate immediately below the gate electrodes 25 and 61.
0,66 may be formed in a self-aligned manner.

As described above, the gate electrode 25,
By forming 61 in the step between the trenches 22 and 53, the semiconductor substrate can be formed into a flat shape with almost no irregularities. Therefore, the step of flattening the silicon oxide film 73 before wiring the metal layer 75 can be simplified.

The layout of the four transistors can be freely set as required. That is, although the photodiodes 29 and 67 in the above embodiment are of the P / N / P junction type, they may be of the N / P junction type. In that case, the reading transistors 31 and 62 can be omitted. That is, in the present invention, a structure in which at least three transistors are arranged in a unit pixel may be employed.

Although the preferred embodiments of the present invention have been described in the above embodiments, the present invention is not limited to the above embodiments and may be modified as appropriate. For example, annealing in a nitrogen atmosphere after ion implantation for suppressing junction leakage due to crystal defects or the like can be added.

[0047]

As is clear from the above, the image sensor according to the first aspect of the present invention includes a channel region of at least three transistors for selecting, amplifying, and resetting signal charges generated by a photoelectric conversion element, which is formed on a surface of a semiconductor substrate. In the vertical direction, the same design rules as the conventional image sensor can be applied to reduce the area occupied by the transistor region and increase the area occupied by the photoelectric conversion element, thereby improving the light sensitivity characteristics. can do. Alternatively, if the same light sensitivity characteristics as those of a conventional image sensor are obtained, the degree of integration can be improved.

Further, the image sensor according to the first embodiment
A channel region formed on a side surface of a concave portion formed on a surface of the semiconductor substrate; a gate insulating film formed on a surface of the concave portion including the channel region; and a channel formed on a side surface of the concave portion. A gate electrode formed on the region via the gate insulating film, and a high-concentration impurity region formed on the surface of the semiconductor substrate including the bottom surface of the concave portion adjacent to the channel region. In addition, a transistor having a channel region arranged in a direction perpendicular to the surface of the semiconductor substrate can be easily formed by a conventional film forming technique, doping technique, photoetching technique, or the like.

Further, the image sensor of the second embodiment is
A first conductive layer formed of a high-concentration impurity layer formed on a surface of the semiconductor substrate and not depleting a substrate interface; and the first conductive layer formed immediately below the first conductive layer. Since it is composed of a second conductive layer of a different conductivity type and a third conductive layer of the same conductivity type as the first conductive layer formed immediately below the second conductive layer, the second conductive layer is formed from a defect level existing on the surface of the semiconductor substrate. Can be prevented from flowing into the photodiode, and defects such as white scratches can be reduced.

According to a second aspect of the invention, there is provided a method of manufacturing an image sensor, comprising forming a plurality of recesses on a surface of a semiconductor substrate, forming a channel region on a side surface of the recess in a unit pixel, and including the channel region A gate insulating film is formed on the surface, a gate electrode is formed on the channel region on the side surface of the concave portion via the gate insulating film, and a surface of the semiconductor substrate including a bottom of the concave portion adjacent to the channel region Since the high-concentration impurity region is formed in the semiconductor substrate, the channel region of the transistor that performs the operation of reading the signal charge generated by the photoelectric conversion element can be arranged in a direction perpendicular to the surface of the semiconductor substrate.

Therefore, if the same design rule as that of the conventional image sensor is applied, the area occupied by the transistor region can be reduced, the area occupied by the photoelectric conversion element can be increased, and the light sensitivity characteristics can be improved. Alternatively, if the same light sensitivity characteristics as those of a conventional image sensor are obtained, the degree of integration can be improved. Further, a transistor in which the channel region is arranged in a direction perpendicular to the surface of the semiconductor substrate can be easily formed by a conventional film forming technique, doping technique, photo etching technique and the like.

In the method for manufacturing an image sensor according to the first embodiment, a conductive layer is formed on the surface of the semiconductor substrate including the recess, and the gate electrode is self-aligned by etching back the conductive layer. In this case, the gate electrode can be formed without increasing misalignment or increasing the number of manufacturing steps. Further, by using a relatively simple method for forming the gate electrode,
Miniaturization can be easily dealt with.

[Brief description of the drawings]

FIG. 1 shows a CMOS as an image sensor according to the present invention.
FIG. 3 is a cross-sectional view of a unit pixel unit in the image sensor.

FIG. 2 is a circuit diagram of a unit pixel unit shown in FIG.

3 is a cross-sectional view of the CMOS image sensor shown in FIG. 1 in a certain manufacturing process.

FIG. 4 is a sectional view in the manufacturing process following FIG. 3;

FIG. 5 is a sectional view in the manufacturing process following FIG. 4;

FIG. 6 is a sectional view in the manufacturing process following FIG. 5;

FIG. 7 is a sectional view in the manufacturing process following FIG. 6;

FIG. 8 is a sectional view in the manufacturing process following FIG. 7;

FIG. 9 is a sectional view of a unit pixel portion in a conventional CMOS image sensor.

[Explanation of symbols]

21, a semiconductor substrate, 22, 53, a trench, 23, 59, a channel region, 24, 60, a gate insulating film, 25, 61, a gate electrode, 26, 72, a high-concentration impurity region, 27, 70, a P ⁺ region, 28,69 ... N ^- region, 29,67 ... Photodiode, 30,66 ... Low concentration impurity region, 31,62 ... Readout transistor, 32,63 ... Reset transistor, 33,64 ... Amplification transistor, 34,65 ... Selection Transistors, 35, 57: P-type well, 36, 54: element isolation region, 42: drain line, 44: signal line, 51: P ⁺ silicon substrate, 52: P-type epitaxial layer, 73: silicon oxide film, 74 ... Contact hole, 75 ... wiring.

Continued on front page F-term (reference) 4M118 AA01 AA02 AB01 BA14 CA04 CB01 CB02 EA03 EA20 FA06 FA28 FA33 FA42 FA46 5F048 AA01 AC03 AC10 BA14 BA15 BA16 BB05 BB20 BC03 BC06 BD09 BG14 BH07 CA03 DA25 5F049 MA02 MB03 NA03 NA03 NA08 UA13 UA14

Claims (8)

[Claims] A photoelectric conversion element formed on a semiconductor substrate and a signal charge generated by the photoelectric conversion element;
An image sensor using at least three transistors for performing amplification and reset as a unit pixel, wherein a channel region of the transistor is arranged in a direction perpendicular to a surface of the semiconductor substrate. 2. The image sensor according to claim 1, wherein a read transistor is added as a transistor in which the channel region is arranged in a vertical direction. 3. The image sensor according to claim 1, wherein the transistor includes a channel region formed on a side surface of a concave portion formed on a surface of the semiconductor substrate, and the channel region in the concave portion. A gate insulating film formed on the surface including, and a gate electrode formed on the channel region on the side surface of the concave portion via the gate insulating film,
A high-concentration impurity region formed on a surface of the semiconductor substrate including a bottom surface of the concave portion adjacent to the channel region, wherein the photoelectric conversion element includes at least a first conductive layer formed on the semiconductor substrate; An image sensor, which is a photodiode comprising a junction between a mold and a second conductivity type. 4. The image sensor according to claim 3, further comprising a low-concentration impurity region adjacent to one end of said channel region. 5. The image sensor according to claim 3, wherein the photodiode includes a first conductive layer formed on a surface of the semiconductor substrate and including a high-concentration impurity layer that does not deplete a substrate interface. A second conductive layer having a different conductivity type from the first conductive layer formed immediately below the first conductive layer; and a second conductive layer having the same conductivity type as the first conductive layer formed immediately below the second conductive layer. An image sensor comprising three conductive layers. 6. A step of forming a plurality of recesses on the surface of a semiconductor substrate and filling each of the recesses with an insulating film to form an element isolation region, and a step other than the element isolation region for defining a unit pixel. Removing the insulating film filled in the concave portion, forming a channel region on a side surface of the concave portion after the insulating film is removed, and forming a gate insulating film on a surface of the concave portion including the channel region. Forming a gate electrode on the channel region on the side surface of the recess through the gate insulating film; and forming a gate electrode adjacent to the channel region on the surface of the semiconductor substrate including the bottom of the recess. A method for manufacturing an image sensor, comprising a step of forming a concentration impurity region. 7. The method for manufacturing an image sensor according to claim 6, wherein, in the step of forming the gate electrode, a conductive layer is formed on a surface of the semiconductor substrate including the recess, and the conductive layer is etched. A method for manufacturing an image sensor, wherein the gate electrode is formed in a self-aligned manner by backing. 8. The method for manufacturing an image sensor according to claim 6, wherein before forming the gate electrode, an impurity is ion-implanted in a direction perpendicular to the semiconductor substrate to form a bottom surface of the recess. Forming a low-concentration impurity region on the surface of the semiconductor substrate.