JP2002132707A - Memory access arbitrating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory access arbitrating method capable of guaranteeing a data transfer rate to a specified client required to guarantee the data transfer rate. SOLUTION: When memory access requests from plural clients required to guarantee the data transfer rate compete, on the basis of remaining buffer capacity, which is generated by each of clients, showing the storage conditions of data to data buffers provided for respective clients, an access right is arbitrated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access arbitration method in a digital copying machine or the like.

[0002]

2. Description of the Related Art As an arbitration method for a memory access request from a plurality of memory access request sources (hereinafter, referred to as clients), an arbitration method based on a fixed priority,
There is a round-robin arbitration method.

The arbitration method using the fixed priority method and the arbitration method using the round robin method both give priority to a memory access request from a client having a higher priority when memory access requests conflict with each other. In the arbitration method based on the ranking method, the priority is fixed, whereas in the arbitration method based on the round robin method, when a client is selected by arbitration, the priority of the client turns to the lowest, and accordingly, the client The two are different in that the priority of another client that is lower than the priority at the time of arbitration is raised.

[0004] There are many clients, and image input from a scanner, LS
In a system in which a data transfer rate needs to be guaranteed, such as an image output to a U (laser scan unit), in the arbitration method using the fixed priority method or the round robin method, data transfer to a specific client There is a high risk that rates cannot be guaranteed.

That is, in the arbitration method based on the fixed priority system, even if the priorities for a plurality of clients for which the data transfer rate is to be guaranteed are set higher, one of the clients for which the data transfer rate is to be guaranteed is internally provided. FI
When a buffer such as an FO is provided, the memory access of another client whose data transfer rate should be guaranteed may be hindered until the buffer is filled with data.

Further, in the arbitration method based on the round robin method, there is not much room in the memory bandwidth (capacity of the transfer rate possessed by the memory) with respect to the total of the data transfer rates required by the clients to guarantee the data transfer rate. Otherwise, when the priority of a client that does not need to guarantee the data transfer rate is moved up, the memory bandwidth is consumed, and sufficient memory bandwidth is secured for the client that needs to guarantee the data transfer rate May not be possible.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory access arbitration method capable of guaranteeing a data transfer rate for a specific client that needs to guarantee a data transfer rate. .

[0008]

According to a first memory access arbitration method according to the present invention, when a memory access request from a plurality of clients for which a data transfer rate needs to be guaranteed conflicts, a memory access request is generated by each client. And based on the buffer remaining amount indicating the accumulation status of data in the data buffer provided in each client,
Arbitration of access rights is performed.

When the memory access by each client is performed by burst access, the arbitration of the access right is performed based on the buffer remaining amount after the buffer remaining amount generated by each client is corrected by the transfer amount within the burst. It is.

In a second memory access arbitration method according to the present invention, when memory access requests from a plurality of clients that need to guarantee a data transfer rate compete with each other, each memory access request is generated by each client at predetermined intervals and Tentatively determining a transaction to be processed next based on a buffer remaining amount indicating a data accumulation state in a data buffer provided in each client;
A step of checking whether the provisionally determined transaction can be processed in the next predetermined period based on the provisionally determined transaction processing content and the processing content of the preceding transaction, and the provisionally determined transaction can be processed in the next predetermined period If it is determined that
The processing of the provisionally determined transaction is started from the next predetermined period, and if it is determined that the provisionally determined transaction cannot be processed in the next predetermined period, the buffer generated by each client in the next predetermined period A step of temporarily determining a transaction to be processed next based on the remaining amount.

When the memory access by each client is performed by burst access, the tentative determination of the transaction to be processed next is based on the buffer remaining after correcting the remaining buffer generated by each client by the transfer amount within the burst. This is done on a volume basis.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

[1] Description of Configuration of Peripheral Circuit of Memory Control Circuit of Digital Copier

FIG. 1 shows the configuration of a memory control circuit and its peripheral circuits of a digital copying machine.

The memory control circuit 1 has an image input / output I / F
2, HDD I / F 3, SDRAM 4, CPU 5, and image compression / decompression circuit 6 are connected.

[2] Description of the configuration of the memory control circuit of the digital copying machine

FIG. 2 shows the configuration of the memory control circuit 1.

The memory control circuit 1 includes a plurality of interfaces (I / F) 11 to 18, an image processing circuit (RBUF) 1
9. Internal CODEC circuit (MXX) 20 and multiple DMs
A controllers (DMAC) 21 to 33 are provided.

In this embodiment, image data input from a scanner (not shown) to an image input I / F (IDIN0) 15 is transferred to a DMA controller (DMAC 10) 21 and an SD card.
A memory access request for storing in the SDRAM 4 by the RAM I / F (SDRAMIF) 14 and image data stored in the SDRAM 4 are transferred to a DMA controller (DMAC 20).
The arbitration operation of the memory control circuit 1 will be described with respect to a case where a memory access request for outputting to the image output I / F (VDOUT0) 17 and performing printing processing by the SDRAMIF 23 and the SDRAM I / F (SDRAMIF) 14 competes. explain.

[3] Description of the configuration of the data buffer built in the image input I / F (IDIN0) 15 and its peripheral circuits

FIG. 3 shows the configuration of the data buffer built in the image input I / F (IDIN0) 15 and its peripheral circuits.

The image input I / F (IDIN0) 15 includes a data buffer 40, a selector 56, a store control signal generator 57, a load control signal and a selection control signal generator 58.
And an encoder 59.

The data buffer 40 has an image input I / F (I
DIN0) The input image data IDIN [31: 0] is taken in synchronization with the operation clock WCK of 15, and the image data idData [31: 0] is output in synchronization with the system clock SCK. In addition, SDR
The AM I / F (SDRAMIF) 14 also operates in synchronization with the system clock SCK. The data buffer 40
It has 15-stage word buffer flag generators 41 to 55, operates as a 15-stage × 32-bit FIFO, and has the number of word buffer flag generators whose data is latched (the amount of data stored in the data buffer 40). )
Is output as the buffer remaining amount idFlag [3: 0].

The data buffer 40 has an image input I / F (I
(DIN0) 15 While the image data write control signal IDACK to the data buffer generated inside 15 is asserted ("H" level), the image data IDIN is fetched in synchronization with the operation clock WCK. Which of the word buffer flag generators 41 to 55 stores the image data IDIN is determined by a store control signal generated by the store control signal generator 57.
Controlled by st [14: 0].

The store control signal generator 57 has a first counter 57a and a first decoder 57b. The first counter 57a performs an up-count operation each time the image data write control signal IDACK is asserted. The count value of the first counter 57a is 14 at the maximum, and returns to 0 when it exceeds 14.

The first decoder 57b includes a first counter 57
The count value of “a” is decoded, and fifteen decoded signals are generated. The store control signal generator 57 calculates the logical product of the image data write control signal IDACK and these tecode signals to generate a store control signal st [14: 0].

Each of the word buffer flag generators 41 to 55
Indicates that the store control signals st0 to st14 input thereto are "H".
At this time, the input image data IDIN is latched. When the word buffer flag generators 41 to 55 latch the data, they assert the data storage flags oflag0 to oflag14. Then, each of the word buffer flag generators 41-55
When the latched data is read, the data storage flags oflag0 to oflag14 are negated.

The encoder 59 has a data storage flag ofla
The number of asserted flags among g0 to oflag14 is encoded to generate a buffer remaining amount flag idFlag [3: 0].

The data buffer 40 has an SDRAM I /
While the data transfer acknowledge signal sdAck10 sent from the F (SDRAMIF) 14 is asserted ("H"), image data is output in synchronization with the system clock SCK. Which of the word buffer flag generators 41 to 55 outputs the image data is determined by the load control signal ld [14: generated by the selection control signal generator 58.
0] and the selection control signal Select.

The load control signal / selection control signal generator 58 has a second counter 58a and a second decoder 58b. The second counter 58a performs an up-count operation each time the data transfer acknowledge signal sdAck10 is asserted. The count value of the second counter 58a is 14 at the maximum, and returns to 0 when it exceeds 14.

The second decoder 58b includes a second counter 58
The count value of “a” is decoded, and fifteen decoded signals are generated. Load control signal and selection control signal generator 5
8 calculates the logical product of the data transfer acknowledge signal sdAck10 and these tecode signals to obtain the load control signal ld.
Generate

Each of the word buffer flag generators 41 to 55
Indicates that the load control signals ld0 to ld14 input thereto are "H".
At this time, the image data is read and the data storage flags oflag0 to oflag14 are negated.

The load control signal and selection control signal generator 58 outputs the count value of the second counter 58a to the selector 56 as a selection control signal Select. Selector 56
Are image data Do0 to image data Do0 to read out from the word buffer flag generators 41 to 55 corresponding to the selection control signal Select.
Select Do14 and output data buffer output signal idData [31: 0]
Output as

[4] Description of the configuration of the data buffer incorporated in the image output I / F (VDOUT0) 17 and its peripheral circuits

FIG. 4 shows the configuration of the data buffer built in the image output I / F (VDOUT0) 17 and its peripheral circuits.

The image output I / F (VDOUT0) 17 includes a data buffer 60, a selector 76, a store control signal generator 77, an encoder 78, and a load control signal / selection control signal generator 79.

The data buffer 60 has a system clock.
In synchronization with SCK, the output data sdData [31: 0] of the SDRAM I / F (SDRAMIF) 14 is taken in, and the image output I / F (VD
OUT0) The image data is synchronized with the operation clock RCK of 17.
Outputs ODOUT [31: 0]. In addition, SDRAM I / F
(SDRAMIF) 14 also operates in synchronization with the system clock SCK. The data buffer 60 has built-in 15-stage word buffer flag generators 61 to 75.
It operates as a 5-stage × 32-bit FIFO, and determines the number of word buffer flag generation units (data free space of the data buffer 60) for which data is not latched by the buffer remaining capacity odFlag.
Output as [3: 0].

The data buffer 60 has an SDRAM I /
While the data transfer acknowledge signal sdAck20 sent from the F (SDRAMIF) 14 is asserted ("H" level), the SDRAMIF is synchronized with the system clock SCK.
14 output data sdData is taken in. Input image data sd
Data is stored in any of the word buffer flag generators 61 to 75.
Is controlled by the store control signal st [14: 0] generated by the store control signal generator 77.

The store control signal generator 77 has a first counter 77a and a first decoder 77b. The first counter 77a performs an up-count operation each time the data transfer acknowledge signal sdAck20 is asserted. First
The count value of the counter 77a is 14 at the maximum, and 14
When it exceeds, it returns to 0.

The first decoder 77b includes a first counter 77
The count value of “a” is decoded, and fifteen decoded signals are generated. The store control signal generator 77 calculates the logical product of the data transfer acknowledge signal sdAck20 and these decode signals to generate a store control signal st [14: 0].

Each of the word buffer flag generators 61 to 75
Indicates that the store control signals st0 to st14 input thereto are "H".
At this time, the output data sdData of the SDRAM IF 14 is latched. Each word buffer flag generator 61-75
When the data is latched, the data storage flags iflag0 to
Assert iflag14. After reading the latched data, the word buffer flag generators 61 to 75 negate the data storage flags iflag0 to iflag14.

The encoder 78 has a data storage flag ifla
The number of negated flags among g0 to iflag14 is encoded to generate a buffer remaining amount flag odFlag [3: 0].

The data buffer 60 includes an image output IF 17
While the image data read control signal ODACK to the data buffer generated internally is asserted ("H"), the image data is output in synchronization with the operation clock RCK of the image output IF 17. Which of the word buffer flag generators 61 to 75 outputs the image data is determined by the load control signal ld [14: 0] and the selection control signal generated by the load control signal and the selection control signal generator 79. Controlled by Select.

The load control signal / selection control signal generator 79 includes a second counter 79a and a second decoder 79b. The second counter 79a performs an up-count operation each time the image data read control signal ODACK is asserted. The count value of the second counter 79a is 14 at the maximum, and returns to 0 when it exceeds 14.

The second decoder 79b includes a second counter 79
The count value of “a” is decoded, and fifteen decoded signals are generated. Load control signal and selection control signal generator 7
Reference numeral 9 calculates the logical product of the image data read control signal ODACK and these tecode signals to generate the load control signal ld.

Each word buffer flag generator 61-75
Indicates that the load control signals ld0 to ld14 input thereto are "H".
At this time, the image data is read and the data storage flags iflag0 to iflag14 are negated.

The load control signal / selection control signal generation section 79 outputs the count value of the second counter 79a to the selector 76 as a selection control signal Select. Selector 76
Are the image data Do0 to image data Do0 to read out from the word buffer flag generation units 61 to 75 corresponding to the selection control signal Select.
Select Do14 and set the data buffer output signal ODOUT [31: 0]
Output as

[5] SDRAM I / F (SDRAMIF) 14
Description of configuration

FIG. 5 shows an SDRAM I / F (SDRAMIF) 1
4 shows the configuration of FIG.

The SDRAM I / F (SDRAMIF) 14 includes the DMA controllers 21 to 33 and the I / F 1 shown in FIG.
Although the I / F has 1/13 and 15/18, here, typically, the DMA controller (DMAC10) 21,
DMA controller (DMAC20) 23, image input I / F
Only the I / F with (IDIN0) 15, the image output I / F (VDOUT0) 17, and the CPU I / F (CPUIF) 13 are shown.

In FIG. 5, the DMAC 10 I / F 81
Controller (DMAC10) 21 and image input I / F (ID
IN0) 15 and the DMAC 20 I / F 82
Controller (DMAC20) 23 and image output I / F (VD
OUT0) 17 and the CPUIF I / F 83 is a CP
The I / F with the U I / F (CPUIF) 13 is shown.

The SDRAM I / F (SDRAMIF) 14 includes an arbitration circuit 84, a transaction file 85, a command generation circuit 86, a strobe generation circuit 87, and the like, in addition to the I / Fs 81, 82, and 83.

The DMAC10 I / F 81 has an image input I / F (IDIN
0) A value obtained by subtracting the buffer remaining amount correction value (internal signal FlagAdj10) from the buffer remaining amount flag idFlag from 15
It is sent to the arbitration circuit 84 as 10. Also, DMAC10 I / F81
Is based on a data transfer acknowledge signal sdAck10 sent from the strobe generating circuit 87.
Data10 is generated by masking ta (logical product of each bit). Then, the logical sum for each bit of Data10 and the output data DataCpu of the CPUIF I / F 83 is calculated to generate the SDRAM write data WriteData.

The DMAC 20 I / F 82 has an image output I / F (VDOU
T0) subtracting the buffer remaining amount correction value (internal signal FlagAdj20) from the buffer remaining amount flag odFlag from 17
It is sent to the arbitration circuit 84 as ag20.

The CPUIF I / F 83 receives the SDR from the CPU 5
Corresponds to AM access. The arbitration circuit 84 arbitrates transaction processing requests from each client. The transaction file 85 is stored in the S
The transaction processing content to which the DRAM access is assigned is held, and the number of cycles after the arbitration is counted.

The command generation circuit 86 issues a command to the SDRAM 4 based on the contents of the transaction file 85 and the number of cycles after arbitration. The strobe generation circuit 87 outputs a data transfer acknowledge signal sdAc
k10 and 20 are generated and the data bus of the SDRAM 4 is controlled.

The main input / output signals of each section will be described below.

(1) DMAC10 I / F81, DMAC20 I / F82,
CPUIF I / F 83 input / output signal. Dm10Req, dm20Req, cpuSdramReq: transaction processing request to SDRAM4. IdFlag: a flag indicating the remaining buffer capacity of the image input I / F (IDIN0). OdFlag: a flag indicating the remaining buffer capacity of the image output I / F (VDOUT0). CpuDir: a signal indicating the direction of data transfer (read / write). Dm10Address, dm20Address: DMA address.

SdDispatch10, sdDispatch20: SDRA
A signal indicating that the transaction processing has been accepted by the M I / F (SDRAMIF) 14. DMAC10 I / F81, DM
The AC20 I / F 82 transfers these signals sdDispatch10 and sdDispatch20 generated by the arbitration circuit 84 to the client as they are.

SdAck10, sdAck20: SDRAM I / F
(SDRAMIF) Data transfer acknowledge signal from 14. DM
The AC10 I / F 81 and the DMAC20 I / F 82 output these signals sdAck10 and sdAck sent from the strobe signal generation circuit 87.
20 is transferred to each client as it is.

(2) Output signal of the arbitration circuit 84 Register: A control signal for registering the transaction processing assigned by the arbitration circuit 84 in the transaction file 85. Client: The client (the DMA controller (DMAC10) 21 and the DMA controller (DMAC20) 2) provisionally determined by the arbitration circuit 84 to have the highest priority at this time.
3. Code indicating CPU IF (CPUIF) 13).

Bank, Row, Col: addresses obtained by decomposing the address sent from the highest priority client into a bank number, a row address and a column address. TransType: Code (READ, WRITE) indicating the transaction processing content of the above-mentioned highest priority client. SdDispatch10, sdDispatch20, sdDispatchCpu: a signal indicating that the arbitration circuit 84 has accepted a transaction processing request by a corresponding client.

(3) Output signal of transaction file 85

FileState: A signal indicating whether the contents of the transaction file 85 are valid (VALID) or invalid (INVALID). CTransType: Code (READ, WRITE) indicating the currently registered transaction processing content. CClient: A code indicating the request source of the currently registered transaction processing.

CBank, CRow, CCol: addresses obtained by decomposing the currently registered transaction processing target addresses into bank numbers, row addresses, and column addresses. CycleCount: a signal indicating a counter value of a counter that counts the number of cycles since the transaction processing is registered in the transaction file 85.

(4) Output signal of command generating circuit 86 ReadTrigger: a trigger signal for designating the timing of read data to the strobe generating circuit 87. WriteTrigger: a trigger signal for designating write data timing to the strobe generating circuit 87. • / CS, / RAS, / CAS, / WE, BA, MA: SDRAM control signal.

(5) Output signal of strobe generating circuit 87.・ SdAck10,20: Data transfer acknowledge signal. SdData: read data from SDRAM4. MD: SDRAMIF data bus.

[6] Description of Access Arbitration Method

For accessing the SDRAM 4,
Examples include the following: (1) Transaction processing request from each of the DMA controllers 21 to 33 (2) Transaction processing request (CPU access) from the CPU I / F (CPUIF) 13

The SDRAM I / F (SDRAMIF) 14 arbitrates these access requests according to the priority order, and gives the access right to the highest priority. The priority is fixed for each client. The priority is determined in advance as follows.

DMAC10, DMAC11, DMAC20, DMAC21> CPU access>DMAC7> DMAC30, DMAC6> DMAC40, DMAC5>DMAC31>
DMAC41>DMAC8> DMAC9

Those separated by commas have the same priority.

When access requests of the same priority conflict, the SDRAM I / F (SDRAMIF) 14 arbitrates based on the remaining buffer flag of the client buffer.
However, for clients without a buffer,
The buffer remaining amount is regarded as a specific value.

When a transaction processing request is continuously issued from the transaction processing request source client currently being processed, the burst length is calculated based on the remaining buffer capacity.
Reconciliation is based on the result of subtracting (4 in this example). Further, even when receiving an access request, the SDRAM I / F (SDRAMIF) 14 excludes the access request from arbitration targets if the remaining buffer capacity of the requesting client has not reached the burst length.

The SDRAM I / F (SDRAMIF) 14 tentatively determines a transaction candidate to be processed next every cycle in the above procedure. Further, it is checked whether the provisionally determined transaction can be processed in the next cycle, and if it can be processed, the processing of the provisionally determined transaction is actually started from the next cycle (SDRA
Command issuance for M4).

Whether the provisionally determined transaction can be processed in the next cycle is determined based on the processing content of the preceding transaction, the processing content of the provisionally determined transaction, and the elapsed time from the start of the preceding transaction processing.

[7] Description of Specific Example of Access Arbitration Method

Hereinafter, based on FIG. 6, the DMA controller (DMAC 10) 21 and the DMA controller (DMAC 20) 2
An arbitration method for a case where access requests conflict between the two clients No. 3 and No. 3 will be specifically described.

[7-1] Description of Block Internal Signal

First, the block internal signal shown in FIG. 6 will be described.

FlagAdj20: Buffer remaining amount flag odFlag
The buffer remaining flag correction value for correcting. The initial value of the correction value is 0, a signal sd indicating that a transaction processing request from the DMA controller (DMAC 20) 23 has been accepted.
Each time Dispatch 20 is asserted, the burst length (4 in this example) is added, and the data transfer acknowledge signal sdAck2
While 0 is asserted, it is decremented by one.
However, the minimum value of FlagAdj20 is 0.

FlagAdj10: Buffer remaining amount flag idFlag
The buffer remaining flag correction value for correcting. The initial value of the correction value is 0, and a signal sd indicating that a transaction processing request from the DMA controller (DMAC10) 21 has been accepted.
Each time Dispatch 10 is asserted, the burst length (“4” in this example) is added, and the data transfer acknowledge signal sd
While Ack10 is asserted, it is decremented by one. However, the minimum value of FlagAdj10 is 0.

RClient: A signal obtained by latching a currently registered code CClient indicating a transaction processing request source on the condition that a signal ReadTrigger indicating read data timing is asserted. • ReadTrigger_ssss: A signal obtained by delaying ReadTrigger by 4 clocks of the system clock SCK and latching it.

ReadAck: A one-shot signal with a 4-clock cycle width that operates using ReadTrigger_ssss as a trigger.・ WriteAck: Operate using WriteTrigger as a trigger 4
One-shot signal with clock cycle width.

RRClient: ReadTrigger_ss for RClient
Signal latched on condition of ss assert.・ WClient: Signal that latches CClient under the condition of WriteTrigger assertion.

[7-2] Explanation of Preconditions for Specific Example in FIG.

The preconditions for the specific example of FIG. 6 are as follows.

(1) The client accessing the SDRAM 4 is the DMA controller (DMAC 10) 21 and the D
It is assumed that there is only the MA controller (DMAC 20) 23.

(2) The operation clock (WCK) of the image input I / F (IDIN0) 15, the operation clock of the image output I / F (VDOUT0) 17, and the system clock (SCK) are all the same clock (same frequency). Suppose there is.

(3) The image input I / F (IDIN0) 15
Once every three clocks, data is written to the data buffer 40 (IDACK assertion) and the image output I / F (VO
UT0) 17 reads data from the data buffer 60 once every two clocks (ODACK assertion).

(4) DMA controller (DMAC10) 21
Is Am, and the transfer start address set in the DMA controller (DMAC 20) 23 is An. In both Am and An, the lower 4 bits are set to “0” so that the burst boundary starts from bank # 0.

(5) DMA address (dm10Address, dm20)
Address) indicates an address in word units. Therefore, the DMA address increases by the burst length (4) each time arbitration is performed once.

[7-3] Explanation of the timing chart of FIG.

At time T1, the DMA controller (DMAC10)
21 and the DMA controller (DMAC20) 23 are activated (dm10Req, dm20Req assertion). At time T1, the image input I / F (IDIN0) 15 is activated, and at time T4, the image output I / F (VOUT0) 17 is activated.

Starting time T1 of the image input I / F (IDIN0) 15
In, since the data buffer 40 is empty, the buffer remaining amount flag idFlag becomes “0”. Also, the image output I /
At the start time T4 of F (VDOUT0) 17, since the data buffer 60 is empty, the buffer remaining amount flag odFlag is set to "1".
5 ".

The buffer remaining amount correction value FlagAdj10 is 0 at the start time T1 of the image input I / F (IDIN0) 15, and the buffer remaining amount correction value FlagAdj20 is the image output I / F (VDOUT
0) It is 0 at the start time T4 of 17. Therefore, Flag10 (idFlag−Fl) output from DMAC10 I / F81
agAdj10) is the starting point of the image input I / F (IDIN0) 15.
It becomes 0 at T1, and Flag20 (o is output from DMAC20 I / F82.
dFlag-FlagAdj20) is the image output I / F (VDOUT0) 1
At the start time T4 of 7, the value is 15.

The arbitration circuit 84 receives the request signal (dm10Re
q, dm20Req) from among the clients asserting Flags Flag10 and Flag20 indicating the remaining amount of the data buffer.
, And temporarily determine the highest priority client.

Immediately after the image input I / F (IDIN0) 15 and the image output I / F (VDOUT0) 17 are started, the Flag
Since 10: Flag20 = 0: 15, the DMA controller (DMAC20) 23 is provisionally determined as the highest priority client. That is, at time T4, the signal Client output from the arbitration circuit 84 is a signal representing the DMAC 20 ("20" in FIG. 6).
Notation).

At time T4, the signal FileState output from the transaction file 85 is in the "INVALID" state. Therefore, the arbitration circuit 84 determines that a command can be issued to the SDRAM 4, and asserts Register.
The arbitrated transaction contents are registered in the transaction file 85.

When registering the transaction contents in the transaction file 85, the DMA address (dm20Address = An in this case) is set to the bank address (Ban
k), and is decomposed into a row address (Row) and a column address (Col). The bank address (Bank) is obtained by performing bank interleaving using a DMA address (dm20Address in this case).

In the following description, dm10Address and
When collectively referring to dm20Address, it will be described as dm # Address. Row address (Row) is FC (dm # Address) =
{Dm # Address [12: 6], dm # Address [3: 2] Decomposed and generated from dm # Address by the function of {}. Column address
(Col) is decomposed and generated from dm # Address by the function of FR (dm # Address) = dm # Address [24:13].

At time T4, the arbitration circuit 84
Assert a signal sdDispatch20 indicating that a transaction processing request from the controller (DMAC20) 23 has been accepted. This signal sdDispatch20 sets the signal Register to 1
It is generated by the logical product of the clock-delayed signal and the signal obtained by decoding the content of the signal CClient. sdDispat
While the ch20 is asserted, the arbitration circuit 84 prohibits the arbitration.

At time T5, the arbitration circuit 84 sets the sdDisp
Based on the assertion of atch20, the buffer remaining amount correction value Flag
Add 4 to Adj20.

When sdDispatch 20 is negated (time T
6) The arbitration circuit 84 resumes the arbitration. At time T6, since Flag10: Flag20 = 1: 11, the DMA controller (DMAC20) 23 is provisionally determined as the highest priority client again.

At time T6, since the signal FileState output from the transaction file 85 is in the "VALID" state, the arbitration circuit 84 determines whether it is possible to issue a command to the SDRAM 4 in relation to the contents of the preceding transaction. Is determined. The preceding transaction is "R
ead ", it is determined whether a command can be issued to the SDRAM 4 based on the read operation preceding operation pattern of FIG.

In this example, since the contents of the follow-up transaction are also "Read" and the bank is non-conflicting, the pattern corresponds to the pattern (1) in FIG. It is necessary to wait for the burst length BL (4 clocks in this example) after the is registered.

The contents of the preceding transaction are "Writ
If e ", it is determined whether or not a command can be issued to the SDRAM 4 based on the write operation preceding operation pattern of FIG.

7 and 8, BL is the burst length (4 in this example), Tarb is the arbitration-command issue latency (2 in this example), and Trcd is / RAS or / CAS delay (2 in this example). ), CL is / CAS latency (2 in this example), Trec is bus recovery time (1 in this example)
And Tdal indicates [WRITA] time data input- [ACT] issue interval (3 in this example).

At time T6, even if the highest priority client is tentatively determined, it is necessary to wait for the burst length BL (4 clocks in this example) after the preceding transaction is registered, as described above. Becomes a BL, and the newly provisionally determined transaction contents are registered in the transaction file 85.

Hereinafter, similar operations are repeatedly performed.

The operation from time T14 to time T19 will be described.

At time T14, the arbitration circuit 84 resumes arbitration, but at time T14, both Flag10 and Flag20 become 3
Since the burst length is smaller than the burst length (4), arbitration is not performed. At time T15, since Flag10: Flag20 = 4: 3, the DMA controller (DMAC10) 21 is provisionally determined as the highest priority client.

At time T15, the signal FileState output from the transaction file 85 is "VALID".
Since it is in the state, the arbitration circuit 84 determines whether or not a command can be issued to the SDRAM 4 in relation to the contents of the preceding transaction. The preceding transaction is "Rea
Since it is d ", it is determined whether or not a command can be issued to the SDRAM 4 based on the read operation preceding operation pattern of FIG.

In this example, since the content of the follow-up transaction is "Write" and the bank is non-conflicting, it corresponds to the pattern of (2) in FIG. , CL +
It is necessary to wait for BL + Trec (7 clocks in this example). The time point seven clocks after the time point T12 is T19.
Therefore, the transaction content provisionally determined at time T15 is not registered at the next time T16.

The provisional determination of the highest priority client is performed every cycle until it is registered in the transaction file.

At the time points T16 and T17, Flag10: Flag
Since 20 = 4: 3, the DMA controller (DMAC10)
Although the client 21 is provisionally determined as the highest priority client, the provisionally determined transaction content is not registered for the same reason as described above. At time T18, Flag10: Flag
Since 20 = 5: 4, the DMA controller (DMAC10)
21 is provisionally determined as the highest priority client. Then, at the next time point T19, the transaction content provisionally determined at the time point T18 is registered.

The operation from time T25 to time T29 will be described.

At time T25, the arbitration circuit 84 resumes arbitration, but at time T25, Flag10 and Flag20 are both 3, which is smaller than the burst length (4), so that arbitration is not performed. At time T26, since Flag10: Flag20 = 3: 4, the DMA controller (DMAC20) 23 is provisionally determined as the highest priority client. In this case, the pattern corresponds to the pattern (1) in FIG. 8, and in order to register a new transaction, it is necessary to wait for BL (4 clocks in this example) after the preceding transaction is registered. No new transaction is registered at time T27.

At time T27, Flag10: Flag20 = 4: 4, which is the same, so that a predetermined client, in this example, the DMA controller (DMAC10) 21, is provisionally determined as the highest priority client. In this case, FIG.
In order to register a new transaction that corresponds to the pattern above, after the preceding transaction is registered,
Since it is necessary to wait for BL (4 in this example) clocks, no new transaction is registered at the next time point T28.

At time T28, since Flag10: Flag20 = 4: 5, the DMA controller (DMAC20) 23 is provisionally determined as the highest priority client. In this case, FIG.
(1), and a new transaction is registered at the next time point T29.

The buffer remaining amount flag idFlag is decreased by 1 with a latency of 1 by sdAck10.
Increases one by one with a latency of 4. However, when both signals are asserted at the same time, the buffer remaining amount flag idFlag does not change. Similarly, the buffer remaining amount flag odFlag decreases by one with a latency of 1 by sdAck20 and increases by one with a latency of 4 by ODACK. However, when both signals are asserted at the same time, the buffer remaining amount flag odFlag does not change.

The dm10Address increases by 4 each time sdDispath10 is asserted. Similarly, dm20Address
Increases by 4 each time sdDispath20 is asserted.

Cyclecount = 3 and CTranceType = "REA
ReadTrigger is asserted at D ". Cyclecou
When nt = 3 and CTranceType = "WRITE", WriteT
rigger is asserted.

The strobe generation circuit 87 asserts the data transfer acknowledge signal sdAck20 to the client held in the RRClient when the ReadAck is asserted. Further, the strobe generating circuit 87 asserts the data transfer acknowledge signal sdAck10 to the client held in WClient when WriteAck is asserted.

When the sdAck10 is asserted, the data buffer 40 of the image input I / F (IDIN0) 15 outputs the SDRAM I / F (IDIN0).
/ F (SDRAMIF) 14 to output data. The data buffer 60 of the image output I / F (VDOUT) 17 stores sdAck2
0 is asserted, the SDRAM I / F (SDRAMIF) 14
Captures the output data sdData of

The command generation circuit 86 determines that Cyclecount = 1
In the next cycle, an [ACT] command and CRow as a row address are issued to the SDRAM 4. In the next cycle of Cyclecount = 3, the command generation circuit 86 issues a [READA] / [ERIRA] command (these commands are switched by CTransType) and CCol as a column address to the SDRAM 4.

According to the above embodiment, when a memory access request from a client for which the data transfer rate needs to be guaranteed conflicts, the data buffers 40, 60
Since the arbitration is performed based on the remaining buffer capacity, the data can be transferred without interruption even to the client that needs to guarantee the data transfer rate.

Further, by combining the arbitration method based on the fixed priority method and the arbitration based on the remaining buffer capacity as in the above-described embodiment, it is possible to prioritize each client group divided into clusters. In addition, access rights can be allocated among a plurality of clients in the same cluster according to the data transfer rate requested by each client.

When memory access by each client is performed by burst access, access right arbitration is performed based on the buffer remaining amount generated by correcting the buffer remaining amount generated by each client by the transfer amount within the burst. SDRAM
Concealing the memory access latency seen in memories such as, and enabling continuous data transfer.

Further, a transaction to be processed next is provisionally determined, and whether the provisionally determined transaction can be processed in the next cycle is determined by the number of cycles after arbitration, the provisionally determined transaction processing content, and the processing content of the preceding transaction. Therefore, the efficiency of memory access can be improved.

[0131]

According to the present invention, a memory access arbitration method capable of guaranteeing a data transfer rate for a specific client which needs to guarantee a data transfer rate is realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a memory control circuit 1 and its peripheral circuits of a digital copying machine.

FIG. 2 is a block diagram showing a configuration of a memory control circuit 1.

FIG. 3 is a block diagram showing a configuration of a data buffer incorporated in an image input I / F (IDIN0) 15 and its peripheral circuits.

FIG. 4 is a block diagram showing a configuration of a data buffer built in an image output I / F (VDOUT0) 17 and its peripheral circuits.

FIG. 5 is a block diagram showing a configuration of an SDRAM I / F (SDRAMIF) 14.

FIG. 6 shows a DMA controller (DMAC10) 21 and a DMA controller.
6 is a time chart for explaining an arbitration method when an access request conflicts between two clients with a controller (DMAC 20) 23.

FIG. 7 is a time chart showing a read operation preceding operation pattern;

FIG. 8 is a time chart showing a write operation preceding operation pattern.

[Explanation of symbols]

 1 Memory Control Circuit 4 SDRAM 5 CPU 14 SDRAM I / F (SDRAMIF) 15 Image Input I / F (IDIN0) 17 Image Output I / F (VDOUT0) 21 DMA Controller (DMAC10) 23 DMA Controller (DMAC20) 40, 60 Data buffer

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Masanobu Takai 1-2-28 Tamazo, Chuo-ku, Osaka-shi, Osaka F-term in Kyocera Mita Corporation (reference) 5B021 AA01 AA19 CC04 DD02 EE01 5B060 CD14 KA04 5B061 BA03 BB01 BC05 DD09 5B077 AA23 BA07 DD12

Claims (4)

[Claims] When a memory access request from a plurality of clients for which a data transfer rate needs to be guaranteed conflicts, a state of accumulation of data in a data buffer generated by each client and provided in each client. A memory access arbitration method for arbitrating an access right based on a remaining buffer amount indicating a buffer amount. 2. When the memory access by each client is performed by burst access, the arbitration of the access right is based on the buffer remaining amount generated by correcting the buffer remaining amount generated by each client by the transfer amount within the burst. 2. The memory access arbitration method according to claim 1, wherein the arbitration method is performed. 3. When memory access requests from a plurality of clients that need to guarantee a data transfer rate conflict with each other, a memory buffer generated by each client and provided to each client is provided at predetermined time intervals. Tentatively determining the next transaction to be processed based on the buffer remaining amount indicating the data accumulation status of the data, and tentatively determining whether or not the tentatively determined transaction can be processed in the next predetermined period, Step of checking based on the processing content of the preceding transaction, and if it is determined that the provisionally determined transaction can be processed in the next predetermined period,
The processing of the provisionally determined transaction is started from the next predetermined period, and if it is determined that the provisionally determined transaction cannot be processed in the next predetermined period, the buffer generated by each client in the next predetermined period Tentatively determining the next transaction to be processed based on the remaining amount. 4. When a memory access by each client is performed by burst access, a tentative decision of a transaction to be processed next is made after correcting a buffer remaining amount generated by each client by a transfer amount in a burst. 4. The memory access arbitration method according to claim 3, wherein the method is performed based on a remaining buffer amount.