JP2002118234A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely prevent generation of malfunction of an element. SOLUTION: A retaining substrate 1 composed of N+ type silicon is electrically insulated from an active layer substrate 202 composed of N- type silicon by using an insulating film 104. A plurality of semiconductor regions which are insulated and isolated from each other by using trench isolating regions are formed in the active layer substrate 202. An N- type high resistance layer 2 is formed on an interface between the retaining substrate 1 and the insulating film 104, and a back side of the retaining substrate 1 is grounded. By the resistance layer 2, displacement current generated in at least one region out of the semiconductor regions is prevented from propagating to the other semiconductor region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an SOI type semiconductor substrate in which a supporting substrate and an active layer substrate are electrically separated by an insulating film, and the active layer substrate is provided with a plurality of semiconductor regions insulated from each other. And a semiconductor device having the same.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional semiconductor device (Japanese Unexamined Patent Publication No.
FIG. As shown in the figure, a P-type support substrate 103 and an active layer substrate 201 made of silicon (Si) are electrically insulated by an insulating film 104 to constitute an SOI type semiconductor substrate. The thickness is about 500 μm. Further, an insulating film 105 buried inside the trench and a buried polycrystalline silicon 106 are formed as a trench isolation region for separating the active layer substrate 201 in a lateral direction (horizontal direction in FIG. 5) to form a semiconductor region. Have been. An N ⁺ type buried layer 102 is formed at the interface between the active layer substrate 201 and the insulating film 104. Further, an N ⁻ type collector region 115 a is formed in the semiconductor region formed in the active layer substrate 201.
Is formed. That is, a collector contact region 111 made of an N ⁺ type high concentration diffusion layer is formed on the surface of the active layer substrate 201,
^{A +} type base region 108 is formed on the surface, and an emitter region 110 made of an N ⁺ type high concentration diffusion layer is formed inside the base region 108. In the other semiconductor region of the active layer substrate 201, a device having a MOS structure is formed inside the N ⁻ type active layer region 115b. That is,
A channel region 112 made of a P ⁻ type well is formed on the surface of the active layer region 115 b, and a source region 113 and a drain region 114 made of an N ⁺ type diffusion layer are formed inside the channel region 112. A gate electrode 204 is formed above the active layer substrate 201 via a gate insulating film 107 so that a channel is formed in contact with the drain region 114 and the source region 113 on the surface of the substrate. In addition, N sandwiched between two trench isolation regions
^A contact region 109 made of an N ⁺ type high concentration diffusion layer is formed inside the ⁻ type active layer region 115 c, the active layer region 115 c is fixed at the ground potential, and the semiconductor regions are completely separated in the lateral direction. The supporting substrate 103 is also fixed at the ground potential, and the impurity concentration of the supporting substrate 103 is 1 × 10 ¹⁶ c
m ⁻³ or less.

In this semiconductor device, an active layer substrate 2
The insulating film 104 exists between each semiconductor region in the semiconductor device 01 and the support substrate 103, and parasitic capacitances C1 to C5 are formed. If a potential change such as dV / dt is applied to the semiconductor region where the MOS device is formed, a displacement current flows through the capacitors C1 to C5.
Displacement current flows to the support substrate 103 side via 4. Here, the impurity concentration of the support substrate 103 is 1 × 10 ¹⁶ cm.
⁻³ or less, and the back surface of the support substrate 103 is fixed at the ground potential.
The displacement current flows to the back surface through the resistor R7 of the support substrate 103, and capacitive coupling of the semiconductor region in which the MOS structure device is formed with the peripheral semiconductor region is suppressed, and malfunction of elements in the peripheral semiconductor region is reduced.

[0004]

However, in such a semiconductor device, the thickness of the supporting substrate 103 is 5 mm.
Since the thickness is as thick as 00 μm, the impurity concentration is 1 × 10 ¹⁶ cm
^{Even when} the low-resistance support substrate 103 of ⁻³ or less is used, the resistance value of the resistor R7 is larger than the resistance values of the resistors R1 to R6 and the like directly below other semiconductor regions. This is apparent from the consideration that the arrangement of other semiconductor regions is not 500 μm apart from the thickness of the supporting substrate 103. Therefore, the current flowing to the support substrate 103 side via the capacitor C4 flows while spreading in the horizontal direction. For this reason, a displacement current also flows immediately below the semiconductor region around the semiconductor region in which the device having the MOS structure is formed, and this current causes the semiconductor region in which the bipolar device is formed via, for example, the capacitor C2. The displacement current also flows in the circuit portion, and there is a possibility that a malfunction of an element in a semiconductor region where a bipolar device is formed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a semiconductor device capable of reliably preventing a malfunction of an element.

[0006]

Means for Solving the Problems In order to achieve the above object, the present invention is configured as described in the claims. That is, in the first aspect, the supporting substrate and the active layer substrate have an SOI type semiconductor substrate electrically separated by an insulating film, and the active layer substrate has a plurality of semiconductor regions isolated from each other. In a semiconductor device, a resistance region is formed in a portion including a region where a supporting substrate and an insulating film are in contact with each other so that a displacement current generated in at least one of the semiconductor regions does not propagate to another semiconductor region. did.

According to a second aspect of the present invention, the resistance region includes:
The support substrate was formed to have higher resistance than the support substrate, and the support substrate was configured to be grounded.

According to a third aspect of the present invention, the resistance region includes:
N ^- consists of type semiconductor, the support substrate was to be composed of N ⁺ -type semiconductor.

According to a fourth aspect of the present invention, the resistance region includes:
It was made of N ^- type silicon or N ^- type polycrystalline silicon.

According to a fifth aspect of the present invention, the active layer substrate is provided with a current extraction region which is in contact with the resistance region and has a lower resistance than the support substrate, and the resistance region is formed to have a lower resistance than the support substrate. I made it.

Further, in claim 6, the resistance region is
Is composed of N ⁺ -type semiconductor, the supporting substrate is N ^- consists of type semiconductor, the current extraction area was to be composed of N ⁺ -type semiconductor.

According to a seventh aspect of the present invention, the current is taken out.
The area is N⁺Mold silicon or N ⁺Type polycrystalline silico
To be configured by

According to the present invention, the current extracting region is arranged around the semiconductor region having high sensitivity to disturbance.

According to a ninth aspect of the present invention, the current extracting region is arranged around a semiconductor region to which a displacement current due to a sudden change in potential from the outside may be applied.

[0015]

According to the first aspect of the present invention, a displacement current generated in at least one semiconductor region among the semiconductor regions is determined by:
A resistance region is formed in a portion including a region where the supporting substrate and the insulating film are in contact with each other so as not to propagate to another semiconductor region. Therefore, a displacement current generated in one semiconductor region is transmitted to another semiconductor region by the resistance region. Even if a displacement current is generated in one semiconductor region without propagating to another semiconductor region, it is possible to reliably prevent the other semiconductor region from malfunctioning due to the displacement current.

According to the second aspect of the present invention, since the resistance region is formed to have a higher resistance than the support substrate and the support substrate is grounded, the displacement current generated in one semiconductor region is high resistance. Therefore, the displacement current propagates through the low-resistance support substrate and flows to the ground, so that the displacement current does not propagate to other semiconductor regions. In addition, it is possible to reliably prevent other semiconductor regions from malfunctioning due to the displacement current.

[0017] According to a third aspect of the invention, the resistor region, N ^- constituted by type semiconductor, the supporting substrate is obtained by to be composed of N ⁺ -type semiconductor, and the invention of claim 2, wherein An equivalent effect can be obtained.

According to a fourth aspect of the present invention, the resistance region is made of N ^- type silicon or N ^- type polycrystalline silicon. Is obtained.

According to a fifth aspect of the present invention, the active layer substrate is provided with a current extraction region which is in contact with the resistance region and has a lower resistance than the support substrate, and the resistance region is formed to have a lower resistance than the support substrate. As a result, when a displacement current is generated in one semiconductor region, the displacement current flows through the resistance region and the current extraction slope, so that the displacement current does not propagate to the other semiconductor region, and therefore, the displacement current It is possible to reliably prevent a malfunction from occurring.

According to a sixth aspect of the present invention, the resistance region is composed of an N ⁺ type semiconductor, the support substrate is composed of an N ⁻ type semiconductor, and the current extraction region is composed of an N ⁺ type semiconductor. Therefore, the same effect as the fifth aspect of the invention can be obtained.

According to the seventh aspect of the present invention, the current extracting region is made of N ⁺ -type silicon or N ⁺ -type polycrystalline silicon. Is obtained.

Further, in the invention according to claim 8, since the current extracting region is arranged around the semiconductor region having high sensitivity to disturbance, malfunction occurs due to the displacement current flowing into the semiconductor region having high sensitivity to disturbance. Can be reliably prevented, and the chip area can be reduced as compared with the case where the current extraction region is formed between all the semiconductor regions.

According to the ninth aspect of the present invention, since the current extracting region is arranged around the semiconductor region to which the displacement current due to the sudden potential change from the outside may be applied, the displacement current is applied. From the semiconductor region, the displacement current flows through the current extraction region, and it is possible to reliably prevent the occurrence of malfunction due to flowing out to another semiconductor region, and to form the current extraction region between all the semiconductor regions. As compared with the case, the chip area can be reduced.

[0024]

(First Embodiment) FIG. 1 is a sectional view showing a part of a semiconductor device according to a first embodiment of the present invention. First, the configuration of the semiconductor device of the present embodiment will be described with reference to FIG. As shown in the figure, a support substrate 1 made of N ⁺ type silicon and an active layer substrate 202 made of N ⁻ type silicon are electrically separated by an insulating film (oxide film) 104. The thickness of the support substrate 1 is about 500 μm. Also,
A trench is formed in the active layer substrate 202, an insulating film 105 is buried inside the trench, a polycrystalline silicon 106 is formed inside the insulating film 105, and the insulating film 1 is formed.
05 and the buried polycrystalline silicon 106, a trench isolation region for forming a semiconductor region (island) by forming a semiconductor region (island) in the horizontal direction (the horizontal direction in FIG. 1) is formed. It has a plurality of semiconductor regions that are insulated from each other. Further, a bipolar device having an N ⁻ -type collector region 115a is formed in at least one of the plurality of semiconductor regions formed on the active layer substrate 202. That is, a collector contact region 111 made of an N ⁺ -type high concentration diffusion layer is formed on the surface of the active layer substrate 202, a P ⁺ -type base region 108 is formed on the surface, and an N ⁺ -type high concentration An emitter region 110 made of a diffusion layer is formed. In the other semiconductor region of the active layer substrate 202, a device having a MOS structure is formed inside the N ⁻ type active layer region 115b. That is, the active layer region 11
A channel region 1 made of a P ^- type well is formed on the surface portion of 5b.
12, a source region 113 and a drain region 114 made of an N ⁺ type diffusion layer are formed inside the channel region 112.
Is formed on the active layer substrate 202 so that a channel is formed in contact with the drain region 114 and the source region 113 on the surface of the channel region 112.
The gate electrode 204 is formed through the gate electrode. Further, a contact region 109 made of an N ⁺ -type high-concentration diffusion layer is formed inside an N ⁻ -type active layer region 115 c sandwiched between two trench isolation regions, and the active layer region 115 c is fixed to the ground potential, The regions are completely separated laterally. Further, the interface with the support substrate 1 and the insulating film 104 N ^- -type high resistance layer 2 (resistive region of high resistance) is formed, N ^- -type high resistance layer 2 is N ^- type ^- type silicon or N of The N ⁻ -type high-resistance layer 2 is made of polycrystalline silicon and has higher resistance than the support substrate 1, and the back surface of the support substrate 1 is grounded. That is, in the semiconductor device of the first embodiment, as compared with the conventional semiconductor device shown in FIG.
The N ⁺ -type buried layer 102 is not formed on the active layer substrate 202, and the N ⁻ -type high-resistance layer 2 is formed on the interface between the support substrate 1 made of N ⁺ -type silicon and the insulating film 104. They differ in the point.

Next, the operation and effect of this embodiment will be described.
I do. In the semiconductor device shown in FIG.
N at the interface between⁻Mold high resistance layer 2 is formed
Therefore, the resistors R8 to R1 directly under each semiconductor region
3 is a ratio of the resistance values of the resistors R1 to R6 shown in FIG.
This is a large value compared to the above. The support substrate 1 has a low resistance.
The resistance value of the resistor R14 is equal to the resistance value of the resistor R7 shown in FIG.
The back side of the support substrate 1 is grounded.
You. For this reason, the device of the MOS structure in the active layer substrate 202
Potential fluctuation such as dV / dt in the semiconductor region where the chair is formed
Is applied, the active layer region 115b and the supporting substrate
1 through a capacitor C4 made of an insulating film 104.
Although the displacement current flows to the support substrate 1 side, N⁻Type high resistance layer 2
Due to the presence of a semiconductor device with a MOS structure
Bipolar device around the body region
The displacement current can be prevented from propagating to the conductor area.
You. In other words, the half of the device having the MOS structure is formed.
Bipolar device formed around conductor area
A shunt (sh
unt). Therefore, MOS structure
Displacement current occurred in the semiconductor region where the device was formed
In the semiconductor area where MOS devices are formed,
With bipolar devices formed around the area
Dramatic suppression of capacitive coupling to the area, bipolar type
Of the elements (circuits) in the semiconductor region where
Ensure that malfunctions due to potential currents do not occur
Semiconductor devices can operate safely enough.
Wear. (Second Embodiment) FIG. 2 shows a second embodiment according to the present invention.
FIG. 4 is a cross-sectional view showing a part of a semiconductor device of an embodiment. First, figure
2 will be used to describe the configuration of the semiconductor device of the present embodiment.
You. As shown in FIG.⁻Support base made of mold silicon
Plate 3 and N⁻Is the active layer substrate 203 made of silicon
It is electrically separated by an insulating film 104, and is formed of an SOI type semiconductor.
A conductor substrate is formed, and the thickness of the support substrate 3 is 500 μm.
m. Also, a trench is formed in the active layer substrate 203.
And the insulating film 105 is buried inside the trench,
Polycrystalline silicon 106 for embedding in insulating film 105
Is formed, and the insulating film 105 and the polycrystalline silicon for embedding are formed.
106, the active layer substrate 203 is moved in the horizontal direction (the left side in FIG.
Trench that forms a semiconductor region that is insulated and separated (to the right)
Isolation regions are formed and isolated from each other in the active layer substrate 203
It has a plurality of separated semiconductor regions. Also, the active layer base
Of the plurality of semiconductor regions formed on the plate 203, at least
N in one semiconductor region⁻Type collector region 115a
Is formed. You
That is, the surface of the active layer substrate 203 has N⁺Type high concentration diffusion layer
A collector contact region 111 made of
⁺A mold base region 108 is formed on the surface and the base region
N inside 108⁺Region consisting of high-concentration diffusion layers
An area 110 is formed. In addition, the active layer substrate 203
N in other semiconductor regions⁻Inside active layer region 115b
A device having a MOS structure is formed. That is,
The surface of active layer region 115b has P⁻Consists of a mold well
A channel region 112 is formed.
N inside⁺Region 113 composed of a diffusion layer
In region 114 is formed and the surface of channel region 112 is formed.
In contact with the drain region 114 and the source region 113
The active layer substrate 203 has
A gate electrode 204 is formed via the gate insulating film 107.
Have been. Further, at the interface between the support substrate 3 and the insulating film 104,
N⁺Mold silicon or N⁺From polycrystalline silicon
N⁺Type low resistance layer 4 (low resistance resistance region) is formed,
N⁺The low resistance layer 4 has a lower resistance than the support substrate 3. Ma
In addition, a tray for separating each semiconductor region on the active layer substrate 203 side.
Between the separation regions, and N⁺Type low resistance layer 4
The current extraction region 5 is formed so as to reach
The output area 5 is N ⁺Mold silicon or N⁺Mold polycrystalline silicon
It is made of silicon and the current extraction region 5 is
Also has a low resistance, and the surface side of the current extraction region 5 is
It is fixed to a potential (for example, a ground potential). Note that this
To form the current extracting region 5, etching is performed.
After forming a trench penetrating the insulating film 104
Then, an epitaxial layer of silicon is formed inside the trench.
Length, and N⁺Diffuses high-concentration impurities in the mold
Or N inside the trench⁺Low-resistance polycrystalline
Fill with silicon. On the other hand, the back surface of the support substrate 3 is grounded.
It is not necessary to fix to the position. Also, the active layer substrate 203
N⁺The mold burying layer 102 is not formed. Sand
The semiconductor device according to the first embodiment and the semiconductor device according to the second embodiment
Of the supporting substrate 1 and 3 and the insulating film 104
It is the same in that a resistance region is formed at the interface, but the first
In the semiconductor device of the embodiment, N⁺Mold of silicon
The interface between the support substrate 1 made of⁻Mold height
While the resistance layer 2 is formed, the second embodiment
In the semiconductor device of⁻Support made of mold silicon
N at the interface between the carrier substrate 3 and the insulating film 104⁺Type low resistance layer 4
Formed and N from the surface side ⁺Reaching the low resistance layer 4
The difference is that the take-out area 5 is formed.

Next, the operation and effect of this embodiment will be described. In the semiconductor device shown in FIG. 2, the resistance values of the resistors R15 to R20 immediately below the respective semiconductor regions are as low as the resistance values of the resistors R1 to R6 shown in FIG. Further, since the support substrate 3 is of the N ⁻ type, the resistance value of the resistor R21 of the support substrate 3 itself is higher than the resistance value of the resistor R7 shown in FIG. For this reason, dV is applied to the semiconductor region in the active layer substrate 203 where the device having the MOS structure is formed.
When a potential fluctuation such as / dt is applied, a displacement current flows to the support substrate 3 side via the capacitor C4 formed of the insulating film 104 between the active layer region 115b and the support substrate 3, but the displacement current Flows laterally through the N ⁺ -type low-resistance layer 4, flows vertically through the low-resistance current extraction region 5, is extracted to the surface of the SOI substrate, and is a bipolar around the semiconductor region where the MOS structure device is formed. It is possible to prevent the displacement current from propagating to the semiconductor region in which the type device is formed. In other words, the structure is such that a current path wrapping around the semiconductor region where the bipolar device is formed around the semiconductor region where the MOS structure device is formed can be shunted halfway. Therefore, even if a displacement current occurs in the semiconductor region where the MOS device is formed, the capacitive coupling to the semiconductor region where the bipolar device is formed around the semiconductor region where the MOS device is formed is dramatically increased. And a malfunction due to a displacement current of an element in a semiconductor region where a bipolar device is formed can be reliably prevented, and the semiconductor device can operate sufficiently safely.

Next, how the current extraction region shown in FIG. 2 is laid out when a plurality of semiconductor regions are insulated from each other by the trench isolation region will be described with reference to FIGS. I do.

First, a current extraction region is laid out as shown in FIG. That is, the semiconductor region 30 of the semiconductor regions 30 to 33 in the active layer substrate has a relatively high circuit impedance and a circuit block having a high sensitivity to disturbance such as displacement current, for example, a latch circuit formed of a bipolar transistor. Circuit block is formed. Further, a circuit block having relatively low sensitivity to disturbance such as displacement current is formed in the semiconductor regions 31 and 32. In the semiconductor region 33, a circuit block having a terminal to which a sudden potential change (dV / dt or the like) from the outside may be applied is formed. Also,
Trench isolation region 3 surrounding each of semiconductor regions 30-33
4 to 37 are formed, and a current extraction region 38 is formed so as to surround the semiconductor region 30.

Next, the operation and effect when the current extraction region is laid out as shown in FIG. 3 will be described. In this case, since the current extraction region 38 is disposed around the semiconductor region 30, when a sudden potential change is applied to the semiconductor region 33 from the outside, a displacement current flowing in the N ⁺ -type low resistance layer 4 in the lateral direction causes a current. Since the displacement current is taken out by the take-out region 38, the displacement current does not flow into the semiconductor region 30 in which the circuit block having high sensitivity to disturbance is formed, so that the malfunction of the device in the semiconductor region 30 due to the displacement current is reliably prevented. can do. Further, as compared with the case where the current extraction regions 38 are arranged in all the regions between the semiconductor regions, the effective area that can be occupied by the elements is increased, and the chip area can be reduced.

As another example, a current extraction region is laid out as shown in FIG. That is, the semiconductor region 30 of the semiconductor regions 30 to 33 in the active layer substrate has a relatively high circuit impedance and a circuit block having a high sensitivity to disturbance such as displacement current, for example, a latch circuit formed of a bipolar transistor. Circuit block is formed. Further, a circuit block having relatively low sensitivity to disturbance such as displacement current is formed in the semiconductor regions 31 and 32. In the semiconductor region 33, a circuit block having a terminal to which a sudden potential change (dV / dt or the like) from the outside may be applied is formed. Further, trench isolation regions 34 to 37 surrounding the respective semiconductor regions 30 to 33 are formed, and a current extraction region 38
Are formed so as to surround the periphery of the semiconductor region 33.

Next, the operation and effect when the current extraction region is laid out as shown in FIG. 4 will be described. In this case, when a sudden potential change is applied to the semiconductor region 33 from the outside, the displacement current once flows in the N ⁺ -type low resistance layer 4 in the lateral direction, and is immediately taken out to the surface side in the surrounding current taking out region 38. It is. Therefore, the semiconductor regions 30 to 32 around the semiconductor region 33 can avoid the inflow of the displacement current regardless of whether the semiconductor regions 30 to 32 have good or poor sensitivity to the displacement current. It is possible to reliably prevent a malfunction due to the current from occurring. Further, compared with the case where the current extraction region 38 is arranged in all regions between the semiconductor regions,
The effective area that can be occupied by the elements is increased, and the chip area can be reduced.

In the first embodiment described above,
The support substrate 1 made of N ⁺ type silicon was formed.
A support substrate made of another ⁺ type semiconductor may be formed. In the first embodiment, N ⁻
Made of silicon of N ^- type or N ^- type polycrystalline silicon
^{Although the −} type high resistance layer 2 is formed, a high resistance resistance region made of another N ⁻ type semiconductor may be formed. In the second embodiment, the support substrate 3 made of N ⁻ type silicon is formed. However, a support substrate made of another N ⁻ type semiconductor may be formed. In the second embodiment, N ⁺ type silicon or N ^{+
Although the} N ⁺ -type low-resistance layer 4 made of ⁺ -type polycrystalline silicon is formed, a low-resistance resistance region made of another N ⁺ -type semiconductor may be formed. In the second embodiment, the current extraction region 5 made of N ⁺ type silicon or N ⁺ type polycrystalline silicon is formed, but the current extraction region 5 made of another N ⁺ type semiconductor is formed. May be formed. In the first and second embodiments, the bipolar device and the MOS device are formed in the semiconductor regions of the active layer substrates 202 and 203.
Another device may be formed in the semiconductor region of the active layer substrate. In the first and second embodiments, the N-channel MOS is used for the semiconductor regions of the active layer substrates 202 and 203.
FET was formed, but Pch was added to the semiconductor region of the active layer substrate.
May be formed.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a part of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a sectional view showing a part of a semiconductor device according to a second embodiment of the present invention;

FIG. 3 is a diagram showing an example of a layout of a current extraction region shown in FIG. 2;

FIG. 4 is a diagram showing another example of the layout of the current extraction region shown in FIG. 2;

FIG. 5 is a cross-sectional view showing a part of a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Support substrate 2 ... N ^- type high resistance layer 3 ... Support substrate 4 ... N ⁺ type low resistance layer 5 ... Current extraction region 30-33 ... Semiconductor region 38 ... Current extraction region 104 ... Insulating film 202 ... Active layer substrate 203 … Active layer substrate

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/78 623Z 626C (72) Inventor Teruyuki Mihara 2 Takaracho, Kanagawa-ku, Yokohama-shi, Kanagawa Nissan Motor Co., Ltd. (72) Inventor Masakatsu Hoshi 2 Takaracho, Kanagawa-ku, Yokohama City, Kanagawa Prefecture Nissan Motor Co., Ltd. (72) Inventor Toshiro Shinohara 1370 Onna, Atsugi-shi, Kanagawa Prefecture Unicity Jex Inc. (72) Inventor Yutaka Tajima 1370 Onna, Atsugi-shi, Kanagawa F-term (reference) in Unisia Jex Co., Ltd. DD21 DD22 GG21 NN62 NN71 NN77

Claims (9)

[Claims] 1. A semiconductor having an SOI type semiconductor substrate in which a supporting substrate and an active layer substrate are electrically separated by an insulating film, and having a plurality of semiconductor regions insulated and separated from each other in the active layer substrate. In the device, in order to prevent a displacement current generated in at least one semiconductor region among the semiconductor regions from propagating to another semiconductor region, a resistance region is included in a portion including a region where the support substrate and the insulating film are in contact with each other. A semiconductor device characterized by forming: 2. The semiconductor device according to claim 1, wherein
The semiconductor device, wherein the resistance region is formed to have a higher resistance than the support substrate, and the support substrate is grounded. 3. The semiconductor device according to claim 2, wherein
Said resistor region, N ^- consists of type semiconductor, the support substrate is a semiconductor device characterized by being composed of N ⁺ -type semiconductor. 4. The semiconductor device according to claim 3, wherein
The semiconductor device, wherein the resistance region is made of N ^- type silicon or N ^- type polycrystalline silicon. 5. The semiconductor device according to claim 1, wherein
A semiconductor, wherein the active layer substrate is provided with a current extraction region having a lower resistance than the support substrate while being in contact with the resistance region, wherein the resistance region is formed to have a lower resistance than the support substrate. apparatus. 6. The semiconductor device according to claim 5, wherein
The resistance region is N⁺The support group comprising
The board is N⁻Current extraction region composed of a semiconductor
Is N ⁺Characterized in that it is made of a semiconductive semiconductor
Conductor device. 7. The semiconductor device according to claim 6, wherein
The current extraction region is made of N ⁺ type silicon or N ⁺
A semiconductor device comprising a polycrystalline silicon. 8. The semiconductor device according to claim 5, wherein said current extraction region is arranged around said semiconductor region having high sensitivity to disturbance. 9. The semiconductor device according to claim 5, wherein said current extracting region is arranged around a semiconductor region to which a displacement current due to a sudden potential change from the outside may be applied. A semiconductor device characterized by the above-mentioned.