JP2002118115A - Semiconductor device and its manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a power semiconductor rectifier.

[0002]

2. Description of the Related Art At present, power semiconductor rectifiers (diodes) are used for various applications including inverters, and their application range is from small / medium capacity withstand voltage of 600 V or less to large capacity with 2.5 kV or more. And wide. In recent years, IGBT
For high-voltage and large-capacity applications, such as those described above, switching elements that can operate at low loss and at high frequencies have been developed and put to practical use. Especially in the field of large capacity, GT
O (Gate Turn-Off Thyrisuto)
r) is being replaced with an IGBT (insulated gate bipolar transistor). Accordingly, high-speed recovery characteristics that enable low-loss and high-frequency operation are required for diodes in similar applications. Furthermore, in recent years, a soft recovery characteristic has been required in order to reduce EMI noise (electromagnetic noise) during operation of a diode in a power electronic device.

A typical example of a power semiconductor rectifier is pi
The n-diode has p-contact with the anode electrode.
⁺ N in contact with the anode layer and the cathode electrode
^It has a structure having an n ⁻ drift layer (i-layer) having a higher specific resistance than both layers in order to secure a high breakdown voltage between the positive electrode layer and the ⁺ cathode layer, and is a rectifying element widely used at present. FIG. 12 is a sectional view of such a conventional pin diode. In this figure, an n ⁻ drift layer 51 having a high specific resistance is shown.
An n ⁺ cathode layer 52 is formed on one surface of
It is in contact with the cathode electrode 55. In addition, n ^-
The surface of the drift layer 51, p ⁺ anode layer 53 is formed, the p ⁺ anode layer 53 is an anode electrode 56
Contact.

When the diode switches from the on state to the off state (at the time of reverse recovery), a transiently large reverse current flows through the diode. This is called a reverse recovery current. At this time, a larger electric loss occurs in the diode than in a steady state. Reducing this loss is strongly required for the characteristics of the diode. Further, at this time, a higher electric duty is generated inside the diode than in the steady state. Increasing the steady-state current flowing through the diode or increasing the voltage in the blocking state increases this electrical responsibility, which can destroy the diode. In order to guarantee high reliability in a power application diode, it is strongly required that the reverse recovery withstand capability be much larger than the rating.

At present, as a measure for improving the reverse recovery characteristic and the withstand voltage of a pin diode, minority carrier lifetime control using heavy metal diffusion or electron beam irradiation is widely applied. That is, since the total carrier concentration in the steady state is reduced by reducing the lifetime, the carrier concentration discharged by the expansion of the space charge region during the reverse recovery is reduced, and the reverse recovery time, the reverse recovery peak current, and the reverse The recovery charge can be reduced. Also, the electric field strength during reverse recovery due to holes passing through the space charge region is reduced by the decrease in the hole concentration,
Electrical responsibilities are reduced and reverse recovery withstand capability is improved.

Further, for the same purpose, Japanese Patent Laid-Open No. 7-3789
In the structure disclosed in Japanese Patent Laid-Open Publication No. 5 (1993) -175, a first region having a high concentration of an anode layer and a second region having a low concentration formed by lateral diffusion are provided.
There is a structure formed by a third region where the second region overlaps. Further, there is a structure disclosed in JP-A-7-235683 in which the third region is not provided and the second regions are in contact with each other on the surface.

FIG. 13 shows a sectional structure of a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 7-37895. The p ⁺ anode layer 53 is formed of a plurality of p ⁺ layer 53a, the p ⁺ layer 5
3a are overlapped in the horizontal direction. By making the width B of the overlapping portion 54 smaller than the diffusion depth Xj of the p ⁺ layer 53a, the reverse recovery current decrease rate dIR / dt can be made smaller than that of the above-mentioned pin structure. That is, a soft recovery characteristic can be obtained. In addition, 5 in the figure
Reference numerals 5 and 56 are a cathode electrode and an anode electrode.

Further, for the same purpose, a merged pin /
Schottky diode (Merged pin / S
A structure that lowers the injection efficiency of minority carriers and improves the reverse recovery characteristics, such as a Cottky Diode (hereinafter abbreviated as “MPS”; see US Pat. No. 4,641,174), has also been developed. FIG. 14 is a sectional view of such a conventional MPS diode. In this figure, one surface of a high resistivity n ⁻ drift layer 51 has n ⁺
A cathode layer 52 is formed and is in contact with a cathode electrode 55. Further, p ⁺ anode layer 53 is formed on a part of one surface of n ⁻ drift layer 51, and p ⁺ anode layer 53 is in contact with anode electrode 56. The n ⁻ drift layer 51 and the anode electrode 56 form a Schottky junction 60 in parallel with the p ⁺ anode layer 53. By forming the Schottky junction 60 as described above, the reverse recovery characteristic is improved.

[0009]

However, as the characteristics of the IGBT are improved, the reverse recovery characteristics of the diode used as the freewheeling diode of the IGBT are improved, that is, the reverse recovery loss and the reverse recovery current are reduced. There is an increasing demand for a reduction in reverse recovery charge, a reduction in reverse recovery time, and a soft recovery, and at the same time, a reduction in reverse leakage current and a reduction in on-state voltage, which are static characteristics.

In the semiconductor device shown in FIG. 14, although the reverse recovery characteristic is improved, the leakage current at the Schottky junction 60 increases. Further, in the semiconductor device of FIG. 13 described above, the reverse recovery characteristic and the leakage current are improved by overlapping the lateral diffusion regions. Normally, impurity diffusion approximately follows a Gaussian distribution, so that the concentration of the vertical and horizontal diffusions decreases exponentially as one proceeds in the depth direction and the horizontal direction. Therefore, when the lateral diffusion regions overlap, as the degree of overlap increases, the density of the overlapping region increases exponentially. Correspondingly, hole injection increases and accumulated carriers increase,
The reverse recovery current is greatly affected by the overlapping concentration, and becomes significantly larger as this concentration increases. Further, when the overlapping concentration becomes large, a ringing phenomenon in which the current waveform oscillates at the time of low current reverse recovery occurs.

An object of the present invention is to provide a semiconductor device which can solve the above-mentioned problems, improve the reverse recovery characteristic, reduce the leakage current, and suppress the voltage reduction at which the ringing phenomenon occurs. .

[0012]

In order to achieve the above object, a second conductivity type diffusion region is formed through a plurality of openings in a surface layer of a first conductivity type semiconductor substrate. The conductivity type diffusion region includes a first region formed immediately below the opening by vertical diffusion and a second region formed outside the opening by lateral diffusion, and the second regions overlap with each other on the surface layer. Third
In the semiconductor device having the region, the maximum concentration of the third region is set to be 1 to 10 times the concentration of the first conductivity type semiconductor substrate.

A second conductivity type diffusion region is formed in the surface layer of the first conductivity type semiconductor substrate through a plurality of openings, and
The conductivity type diffusion region includes a first region formed immediately below the opening by vertical diffusion and a second region formed outside the opening by lateral diffusion, and the second regions overlap with each other on the surface layer. In the semiconductor device having the third region, it is preferable that the first conductivity type semiconductor has a first conductivity type region selectively on its surface.

The maximum concentration of the third region is preferably not less than 1 and not more than 10 times that of the first conductivity type semiconductor substrate. In the plane cross section at the point where the width of the second conductivity type diffusion region is maximum,
The area of the first region may be 50% or less of the area of the second conductivity type diffusion region.

A second conductivity type diffusion region is formed in a surface layer of the first conductivity type semiconductor substrate through a plurality of openings, and
The conductivity type diffusion region includes a first region formed immediately below the opening by vertical diffusion and a second region formed outside the opening by lateral diffusion, and the second regions overlap with each other on the surface layer. In the method of manufacturing a semiconductor device having a third region, the second conductivity type diffusion region is formed by setting an ion implantation depth (an average range of ions) of the second conductivity type impurity to Rp and vertically diffusing the impurity. Assuming that the depth is Xj and the distance between the adjacent openings is W, 1.5 (Xj ² −2Xj · Rp) ^1/2 ≦
It is effective to satisfy the relational expression of W ≦ 1.5 (Xj−Rp).

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, the first conductivity type is represented by n.
The type and the second conductivity type will be described as p-type, but may be reversed. FIG. 1 is a sectional view of a main part of a semiconductor device according to a first embodiment of the present invention. An n ⁺ cathode layer 2 is formed on a surface layer on one main surface of the n-type semiconductor substrate 100, an impurity is implanted on the surface layer on the other main surface by ion implantation, and then ap ⁺ layer 3 a is formed by thermal diffusion. Are formed so as to overlap in the horizontal direction. The whole p ⁺ layer 3 a overlapping in the lateral direction becomes the p ⁺ anode layer 3. A cathode electrode 5 is formed on the n ⁺ cathode layer 2 and an anode electrode 6 is formed on the n ⁺ anode layer 3. An n-type semiconductor substrate sandwiched between n ⁺ cathode layer 2 and n ⁺ anode layer 3 serves as n ⁻ drift layer 1. The p ⁺ anode layer 3 is a resist 1 indicated by a dotted line having a large number of openings.
1 is used as a mask, a p-type impurity is ion-implanted at an implantation depth Lp (average ion range), and then thermally diffused so as to overlap with each other in the lateral direction. The highest density point 7 of the overlapping point 4 exists on the Lp line. By setting the highest concentration at the overlapping portion 4 to be 1 to 10 times the concentration of the n ^- drift layer 1, the reverse recovery characteristic is improved and the voltage at which ringing occurs (this is called a ringing generation voltage) is reduced. Can be suppressed. Further, the leakage current can be significantly reduced as compared with the MPS having the diffusion junction and the Schottky junction. When a lifetime killer is introduced into a semiconductor device manufactured in this manner, it is possible to further improve the reverse recovery characteristic and prevent the ringing generation voltage from lowering. It is effective that the lifetime killer is introduced in the n ⁻ drift layer 1 near the p ⁺ anode layer 3 and the entire n ⁻ drift layer 1 immediately below the opening 12. In addition, W in the figure
Is the distance between adjacent openings 12. The third region described in the claims is, of course, the overlapping portion 4.

FIG. 2 shows the relationship between the highest concentration (acceptor concentration N _A ) at the overlapping portion and the reverse recovery current in the semiconductor device of FIG. In the figure, the vertical axis represents the ratio of the reverse recovery current density JRP to the forward current density JF immediately before the reverse recovery process. When the highest concentration (acceptor concentration N _A ) of the overlapping portion 4 exceeds 10 times the concentration of the n-type semiconductor substrate 100 (concentration of the n ⁻ drift layer 1: donor concentration N _D ), the reverse recovery current rapidly increases. Become. This is because the injection of holes increases and the number of accumulated carriers increases rapidly. Therefore, the highest concentration of the overlapping portion 4 is 1 to 1 times the concentration of the n-type semiconductor substrate 100.
A range of 0 times is preferable.

[0018] Figure 3, in the semiconductor device of FIG. 1, p ⁺
In a plane cross section at the point where the width of the anode layer 3 is maximum (in this figure, the position of LP from the surface), a vertical diffusion region relative to the entire area of the p ⁺ anode layer 3 (first region of claim 1)
FIG. 4 is a diagram showing a relationship between a ratio R (%) of the area and a reverse recovery current. 100% -R is the ratio of the area of the lateral diffusion region to the area of the p ⁺ anode layer 3. In the figure, the vertical axis is
It is indicated by the ratio of the reverse recovery current density JRP to the forward current density JF immediately before the reverse recovery process.

The increase in R means that the area of the vertical diffusion region (equal to the area of the opening 12) increases and the area of the lateral diffusion region decreases. The total amount of impurities diffused in the horizontal direction (total amount of holes) is smaller than the total amount of impurities diffused in the vertical direction (total amount of holes). Therefore, as R increases, the area of the vertical diffusion region increases and the area of the lateral diffusion region decreases, as described above.
^- holes injected into the drift layer 1 is increased. When the density of injected holes increases, excess carriers accumulated in the n drift layer 1 increase, and therefore, the reverse recovery current increases.

When R exceeds 50%, the rate of increase of the reverse recovery current increases as shown in FIG. Therefore, it is desirable that R is set to 50% or less. R is preferably as small as possible, but practically, the minimum value of R is set to several percent to 10%.
%. In addition, the leakage current depends on the pn junction (p
^{Since the} reverse voltage is blocked by the (junction of the anode layer 3 and the n-drift layer 1), it is of course as small as a pin diode.

FIG. 4 shows the relationship between the highest concentration at the overlapping portion and the ringing generation voltage in the semiconductor device of FIG. The vertical axis indicates the ringing generation voltage V RB (th) and the punch-through voltage V
Shown in PT ratio. In the case where the reverse recovery is performed by a very small current such as 1/10 or less of the rating, the concentration of the n-type semiconductor
If it exceeds twice, the ringing generation voltage drops sharply.
This is because when the reverse recovery current increases, the current reduction rate of the reverse recovery current increases. Therefore, the highest concentration of the overlapping portion 4 is preferably in the range of 1 to 10 times the concentration of the n-type semiconductor substrate 100. In this range, it is possible to suppress a drop in the ringing generation voltage peculiar to the reverse recovery of the minute current.

FIG. 5 is a sectional view of a principal part of a semiconductor device according to a second embodiment of the present invention. The depth Lp of the ion implantation shown in FIG. 1 is increased so that a portion where the p ⁺ layer 3a does not overlap with the surface layer is formed. This non-overlapping portion is the n ^- layer 8. Further, the highest concentration of the overlapping portion 4 is set to be not less than 1 time and not more than 10 times the concentration of the n ⁻ drift layer 1. By doing so, it is possible to further improve the reverse recovery characteristic and suppress the voltage drop at which ringing occurs, and to reduce the leakage current
It can be significantly smaller than S.

The plane pattern of the n ^- layer 8 may be a stripe or a circular or polygonal island. By leaving n ⁻ layer 8 on the surface layer in this manner, pinch-off of the depletion layer occurs at a depth of Rp from the surface, and the pinch-off voltage is sufficiently reduced, so that the electric field strength on the Schottky surface is reduced. Therefore, the leakage current is suppressed to the level of pin.

When the distance between adjacent openings of the resist is W, the diffusion depth is Xj, the ion implantation depth is Rp, and the lateral diffusion depth is 0.75Xj, W is 1.5 (Xj ² − 2
When Xj · Rp) in the range of ^{1/2 ≦ W ≦ 1.5 (Xj-} Rp), n - directly beneath the layer 8 is the n ^- drift layer 1 ^- point overlapping layers 8 / p ⁺ layer 3a 4 / n . Due to the existence of the n ^- layer 8, injection of holes from the overlapping portion 4 (during forward bias) is suppressed. Therefore, the reverse recovery current can be further reduced as compared with the case where n ⁻ layer 8 does not exist, that is, the case where overlapping portion 4 extends to the surface layer.

Note that W <1.5 (Xj ² -2Xj · Rp)
^{At 1/2} , the p ⁺ layer 3a also overlaps on the surface, and W>
At 1.5 (Xj-Rp), the tip of the p ⁺ layer 3a in the lateral direction is separated. Next, a specific embodiment of FIG. 5 will be described. To form the p ⁺ layer 3a, an acceleration voltage of 300
Boron is ion-implanted at keV and then heat-treated.
The condition of the heat treatment determines the degree of overlap of the p ⁺ layers 3a. Assuming that the depth of ion implantation is Rp = 0.8 μm and the diffusion depth in the vertical direction is Xj = 5 μm, the distance W between adjacent openings is in the range of 6.2 μm to 6.3 μm, and the n ⁻ layer is formed on the surface. 8 will be present (exposed). The relationship between the reverse recovery current and W of the semiconductor device will be described below.

FIG. 6 shows the relationship between the reverse recovery current and W. JR in the figure is a reverse recovery current (peak current), and JF is a forward current immediately before the reverse recovery process. The reverse recovery current is W = 6.2 μ at which the overlapping portion 4 becomes large and the n ⁻ layer 8 disappears.
When W becomes smaller than m, it greatly increases as in the conventional structure. On the other hand, the p ⁺ layer 3a overlaps and the n ⁻ layer 4
In the case where W exists, that is, in the range of 6.2 μm to 6.3 μm, a structure in which the surface of FIG.
That is, the reverse recovery current is smaller than that of the structure having no n ⁻ layer. In this range, n ^- injection of holes from the point 4 overlap in the presence of a layer 8, n ^- is to be suppressed as compared with the case where the layer 8 is not present. Also, the leakage current is as small as pin because the junction between p ⁺ layer 3a and n ⁻ drift layer 1 blocks a reverse voltage.

Further, when the ^{p.sup. +} Layer 3a no longer overlaps (W> 6.3 .mu.m), the reverse recovery current has the same low value in both cases. However, since the Schottky junction is formed between the n ⁻ drift layer 1 and the anode electrode 6 at the position where the p ⁺ layer 3a has no overlap, the leakage current is increased in this range (not shown). Also, the ringing generation voltage does not become lower than the punch-through voltage of the depletion layer.

That is, in the range where the p ⁺ layer 3a overlaps and the n ⁻ layer 8 exists (6.2 μm ≦ W ≦ 6.3 μm), the reverse recovery current has the highest concentration on the surface of FIG. 10 described later. As in the structure, the p ⁺ layer 3a overlaps, the size is smaller than the structure without the n ⁻ layer, and the leakage current is smaller than the MPS. FIGS. 7 to 10 correspond to FIGS.
FIG. 6 is a cross-sectional view of a main part step in the manufacturing step of the semiconductor device shown in FIG.

An n ⁺ cathode layer 2 is formed on a surface layer of one main surface of an n-type semiconductor substrate 100, a resist 11 is coated on the other main surface, and an opening 12 is formed by photolithography. Let W be the distance between adjacent openings 12 (FIG. 7). Next, the ion implantation 13 of the p-type impurity 14 is performed at the implantation depth Lp from the opening 12 (FIG. 8).

Next, the p ⁺ layer 3a is diffused by thermal diffusion so as to overlap in the horizontal direction. This overlapping p ⁺ layer 3
a forms the p ⁺ anode layer 3. When the vertical diffusion depth at this time is X _j and the horizontal diffusion depth is A, A
= A 0.75X _j. Further, the highest density portion 7 of the overlapping portion 4 is located on the Lp line (FIG. 9). Next, n ⁺
A cathode electrode 5 and an anode electrode 6 are formed on the cathode layer 2 and the p ⁺ anode layer 3 (FIG. 10).

By increasing L _P and setting the thermal diffusion conditions to predetermined conditions, as shown in FIG. 5, p ⁺
A portion where the layer 3a does not overlap occurs, and a structure in which the n ^- layer 8 exists can be obtained. FIG. 11 is a sectional view showing a main part of a semiconductor device according to a third embodiment of the present invention. This is the case where the highest concentration point 7 is located on the surface, and where the n ⁻ layer 8 does not exist. This is a case where the p ⁺ layer 3a is formed not by ion implantation but by ordinary diffusion, and the surface concentration is maximized. Also in this case, by setting the highest concentration at the overlapping portion 4 to be at least 1 and at most 10 times the concentration of the n-type semiconductor substrate, the same effect as in FIG. 1 can be expected.

[0032]

According to the present invention, the highest concentration at the overlapping portion of the p ⁺ anode layer is set to be not less than 1 time and not more than 10 times the concentration of the n-type semiconductor substrate (n ⁻ drift layer).
The reverse recovery characteristic and the leakage current can be improved, and furthermore, the drop in the ringing generation voltage can be suppressed.

Further, by having an overlapping portion and exposing the n-type semiconductor substrate layer (n ^- drift layer) on the surface layer, the reverse recovery characteristic can be improved as compared with the structure having the overlapping portion up to the surface layer. . Further, by setting the ratio of the area of the vertical diffusion region to the area of the p ⁺ anode layer to 50% or less,
Reverse recovery characteristics can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a diagram showing the relationship between the highest concentration (acceptor concentration N _A ) and the reverse recovery current of the overlapping portion in the semiconductor device of FIG.

FIG. 3 shows a p ⁺ anode layer 3 in the semiconductor device of FIG.
Showing the relationship between the ratio R of the area of the vertical diffusion region (the first region of claim 1) to the area of R and the reverse recovery current.

FIG. 4 is a diagram showing a relationship between the highest concentration at an overlapping portion and a ringing generation voltage in the semiconductor device of FIG. 1;

FIG. 5 is a sectional view of a main part of a semiconductor device according to a second embodiment of the present invention;

FIG. 6 is a diagram showing a relationship between a reverse recovery current and W.

FIG. 7 is a sectional view of a main part process of the semiconductor device of FIGS. 1 and 5;

8 is a cross-sectional view of a main part process of the semiconductor device of FIGS. 1 and 5, following FIG. 7;

9 is a cross-sectional view of a main part process of the semiconductor device of FIGS. 1 and 5, following FIG. 8;

FIG. 10 is a cross-sectional view of a main part process of the semiconductor device of FIGS. 1 and 5, following FIG. 9;

FIG. 11 is a sectional view of a principal part of a semiconductor device according to a third embodiment of the present invention;

FIG. 12 is a sectional view of a pin diode.

FIG. 13 is a sectional structural view of a semiconductor device disclosed in JP-A-7-37895.

FIG. 14 is a sectional view of an MPS diode.

[Explanation of symbols]

Reference Signs List 1 n ^- drift layer 2 n ⁺ cathode layer 3 p ⁺ anode layer 3 ap ⁺ layer 4 overlapping point 5 cathode electrode 6 anode electrode 7 highest concentration point 8 n ^- layer 11 resist 12 opening 13 ion implantation 14 p-type impurity 100 n-type semiconductor substrate W spacing between adjacent openings Lp implantation depth (average range of ions) Xj vertical diffusion depth A horizontal diffusion depth

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Masato Otsuki 1-1, Tanabe-Nitta, Kawasaki-ku, Kawasaki-city, Kanagawa Prefecture Inside Fuji Electric Co., Ltd. (72) Inventor Tatsuya Naito 1 Tanabe-Nitta, Kawasaki-ku, Kawasaki-ku, Kanagawa Prefecture No. 1 Inside Fuji Electric Co., Ltd.

Claims (5)

[Claims] A second conductive type diffusion region formed in a surface layer of the first conductive type semiconductor substrate through a plurality of openings;
The conductivity type diffusion region includes a first region formed immediately below the opening by vertical diffusion and a second region formed outside the opening by lateral diffusion, and the second regions overlap with each other on the surface layer. In the semiconductor device having the third region, the maximum concentration of the third region is 1 or more times the concentration of the first conductivity type semiconductor substrate.
A semiconductor device characterized by being no more than 0 times. 2. A second conductivity type diffusion region is formed in a surface layer of a first conductivity type semiconductor substrate through a plurality of openings.
The conductivity type diffusion region includes a first region formed immediately below the opening by vertical diffusion and a second region formed outside the opening by lateral diffusion, and the second regions overlap with each other on the surface layer. A semiconductor device having a third region, wherein a first conductivity type region is selectively provided on the surface of the first conductivity type semiconductor. 3. The semiconductor device according to claim 2, wherein the maximum concentration of the third region is at least 1 and at most 10 times that of the first conductivity type semiconductor substrate. 4. A plane cross section at the point where the width of the second conductivity type diffusion region is maximum, wherein the area of the first region is 50% or less of the area of the second conductivity type diffusion region. 3. The semiconductor device according to claim 1, wherein: 5. A second conductivity type diffusion region is formed in a surface layer of a first conductivity type semiconductor substrate through a plurality of openings, and said second conductivity type diffusion region is formed.
The conductivity type diffusion region includes a first region formed immediately below the opening by vertical diffusion and a second region formed outside the opening by lateral diffusion, and the second regions overlap with each other on the surface layer. In the method of manufacturing a semiconductor device having a third region, the second conductivity type diffusion region is formed by setting an ion implantation depth (an average range of ions) of the second conductivity type impurity to Rp and vertically diffusing the impurity. Assuming that the depth is Xj and the distance between the adjacent openings is W, 1.5 (Xj ² −2Xj · Rp) ^1/2 ≦
A method of manufacturing a semiconductor device, wherein a relational expression of W ≦ 1.5 (Xj−Rp) is satisfied.