JP2002118186A - Method for forming contoured floating gate cell - Google Patents

Abstract

(57) [Summary] (With correction) [PROBLEMS] To provide a method of manufacturing a floating gate which can suppress structural defects even if the size of a memory cell is reduced. SOLUTION: A floating gate 12 of a memory cell.
0 is a concave structure including both end regions of the first 111 and the second 113 and a central region thereof, and is formed on the semiconductor substrate 100 to be higher than the vertical thickness of the oxide structure 126;
A third layer 150 of polysilicon that will be the word line control gate is deposited on the polysilicon dielectric film 108. The contact area between the floating gate 120 and the third layer 150 is sufficiently large due to the concave shape, and the coupling ratio with the control gate is kept large.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to non-volatile digital memories and, more particularly, to flash EPROM memories incorporating new floating gates with reduced lateral dimensions.

[0002]

2. Description of the Related Art Flash EPROM memories fall into the category of non-volatile storage integrated circuits. Generally, flash EP
A ROM can electrically erase, program, or read memory cells on a chip. Generally, flash EPROMs include a floating gate and a control gate that form an electrical connection. Flash EPROM
Operates by charging or discharging electrons into the floating gate of a memory cell in a capacitive manner. The floating gate is formed from a conductive material, typically made of polysilicon, insulated from the channel of the transistor by a layer of oxide or other insulating material, and from the control gate or word line of the transistor to a second layer of insulating material. Insulated by

[0003] The charging operation of the floating gate is called an A program @ step of the flash EPROM. The program step is achieved by so-called hot electron injection with a large positive voltage set between the source and the control gate. The discharging operation of the floating gate is called the A erase function of the flash EPROM. The erase function is typically performed by an FN tunneling mechanism between the floating gate and the source of the transistor (source erase) or between the floating gate and the substrate (channel erase).

[0004] Due to increasing memory demand, there is a need to further reduce the size of memory devices such as flash EPROMs. Decreasing the cell size of the memory device increases performance and reduces power consumption.

Several devices with reduced size have been developed. One such device is the "fine HSG
High-coupling ratio A low-voltage operation flash memory cell using a horn-shaped floating gate, "Kitamura et al., 1998, VLSI technical paper abstract. Examples of other memory devices with reduced cell size include "A0.24-Fm cell process with 0.18-Fm width isolation and 3D interpoly dielectric layer for 1 GB flash memory", Kobayashi et al.
There is one described in IEEE 97-275 (1997).

[0006]

As the size of the memory cell is reduced, the memory cell suffers from drawbacks including excessive floating gates which degrade the tunnel oxide and intermediate structures formed during the manufacture of the floating gate. Memory cell. If a sharp edge is formed in the floating gate, charge leakage will occur.

[0007]

SUMMARY OF THE INVENTION A floating gate used for a memory cell is a first floating gate.
A first end region located near the side edge, a second end region located near the second side end of the floating gate, and a first end region adjacent to the floating gate with respect to the first end region and the second region. And a central region located in the central direction. The first region, the central region, and the second end region are formed of the same material during a single manufacturing step, and the central region has a thickness less than the thickness of the first region and the second region.

According to another embodiment of the present invention, the floating gate of the floating gate memory cell includes a first polysilicon layer formed during a first manufacturing step and a first polysilicon layer formed during a second manufacturing step. A second polysilicon layer formed on the polysilicon layer. The second polysilicon layer includes a first end region located near the first side end of the floating gate, a second end region located near the second side end of the floating gate, a first end region, and a second end region. A central region located centrally beside the floating gate with respect to the end region.

In one variation, the first and second end regions each have an outer surface forming one end of the floating gate, an inner surface near the central region, an upper end surface,
An inner surface close to the central region. In this embodiment, the end regions have a uniform thickness between the outer surface and the inner surface.

[0010] In another variation, the central region may have an upper surface substantially parallel to the substrate under the floating gate.

In another variation, the floating gate has a bottom surface opposite the plane of the substrate below the floating gate, and the floating gate is within a lateral footprint defined by the bottom surface of the floating gate. May be located substantially.

In another variation, the floating gate is formed by a first layer of material formed during a first manufacturing step and a second layer formed on the first layer during a second manufacturing step. Is done. Alternatively, the entire floating gate is formed during a single manufacturing step.

[0013] In a variant of the floating gate, the first outer surface is provided substantially perpendicular to the upper end surface of the end region so that the inner surface is approximately perpendicular to the tangent surface of the upper end surface of the end region. Is also good.

For each of the above floating gates, the floating gate comprises a substrate, a source and drain region located on the substrate, and an insulating layer located on the source and drain regions.
It can be incorporated in a memory cell. The floating gate is located on the insulating layer between the source and drain regions, and the control gate is located on the dielectric layer.

According to the present invention there is also provided a method of manufacturing the floating gate of the present invention. According to one embodiment, a method of making a contoured floating gate for use in a floating gate memory cell is provided, wherein the first and second oxide structures are spaced apart and the first and second oxide structures are spaced apart. Forming a polysilicon layer on the floating gate region between the second oxide structures. The polysilicon layer formed in the floating gate region has a first end region near the first oxide structure and a second end region near the second oxide structure.
An end region and a central region laterally located between the first and second end regions, each of the first and second end regions having a vertical thickness greater than a vertical thickness of the central region. The method further includes removing a portion of the polysilicon layer in the floating gate region such that the thickness of the first and second end regions remains greater than the vertical thickness of the central region.

[0016] In another variation, the method further comprises forming a portion of the first and second oxide structures such that the first end region and the second end region extend beyond an upper surface of the first and second oxide structures. Removing.

In another variation, forming a polysilicon layer over the first and second oxide structures and the floating gate region is such that the end region is substantially between the outer surface and the respective inner surface. And forming it to have a uniform thickness.

In another variation, removing the polysilicon layer over the first and second oxide structures may include removing the first oxide structure, the second oxide structure, the first end region, and the second end region. Including

In another method of fabricating a floating gate according to the present invention, the method includes forming a first polysilicon layer in a floating gate region of a substrate.
The method further includes forming an oxide structure at opposite ends of the floating gate region such that the first and second oxide structures have a vertical thickness greater than a vertical thickness of the first polysilicon layer. . And the second polysilicon layer is the first polysilicon layer.
Formed on a polysilicon layer and an oxide structure. The first and second polysilicon layers combine to form a floating gate in the floating gate region. The floating gate is located at a first end region near the first side end, a second end region near the second side end, and transversely to the first and second end regions toward the center of the floating gate. The first end region and the second end region have a vertical thickness that is greater than the vertical thickness of the central region. The method further includes removing the second polysilicon layer over the first and second oxide structures to form a contoured floating gate.

In one variation, the method further comprises removing portions of the first and second oxide structures such that an end region of the floating gate extends vertically beyond the upper surface of the oxide structure. Including.

In another variation, forming a second polysilicon layer over the first and second oxide structures and the first polysilicon layer includes an outer surface and a top surface near the outer surface. Forming an upper end region of the floating gate, the end region having a substantially uniform thickness between the outer surface and the respective inner surface.

In another variation, forming a second polysilicon layer over the first and second oxide structures and the first polysilicon layer comprises forming the first oxide structure, the second oxide structure, And flattening the first end region and the second end region.

Each of the above methods can be used for forming a floating gate memory cell. The method comprises providing a substrate, forming source and drain regions on the substrate, depositing an insulating layer on the source and drain regions, and defining a contoured floating gate located on the insulating layer between the source and drain regions. Forming

[0024]

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the design of a flash memory cell having a reduced lateral dimension by incorporating a contoured three-dimensional coupling surface into a floating gate. The contoured bonding surface is formed by fabricating the material forming the floating gate such that the thickness varies across the width. The floating gate is formed by a manufacturing process.

As will be described in greater detail below, the use of floating gates according to embodiments of the present invention provides the advantage that smaller memory cells provide comparable performance to conventional flash EPROM memory cells having a larger size. Give a great advantage. In particular, the memory cell of the present invention has the advantages that it can be manufactured at low cost and that leakage of electric charge from the floating gate can be prevented.

FIG. 1 shows a memory array or flash EPR.
FIG. 4 shows memory cells according to the invention aligned in a column to form an OM device. FIG. The memory cells in the column are the semiconductor substrate 10
Share 0. The particular design or configuration of the semiconductor substrate 100 may differ depending on the memory device structure. For example, FIG.
For the source-drain-source configuration shown in
The semiconductor substrate 100 may be a p-type. N on the substrate 100
+ Type source 114 and n + drain region 115 are distributed. Preferably, a plurality of oxide structures 126 are each included on oxide region 127 of substrate 100. The oxide structures 126 are arranged such that the plurality of floating gates 120 are each located on a corresponding floating gate region 125 of the substrate 100.
Formed between them. In one embodiment, floating gate 120 abuts oxide structure 126 at respective first and second side edges 111 and 113. An insulating layer, such as tunnel oxide layer 103, may separate substrate 100, floating gate 120, and oxide layer 126. Preferably, source and drain regions 114 and 1
15 are each substantially below one oxide structure 126.

Floating gate 120 has direction arrow 1
As shown at 35, it extends in the horizontal direction in the word line direction.
Additional floating gates 120 aligned in the bit line direction extending perpendicular to the page are not shown. Each floating gate 120 is formed from a polysilicon body having a vertical thickness in one or more regions that is greater than the vertical thickness of oxide structure 126. As described below, the floating gate of the first embodiment includes a polysilicon body having a contoured or three-dimensional coupling surface including a recessed area and one or more raised edges or plateaus. .

As shown, the floating gate
The memory cell further includes an oxide structure 126 and an interpoly dielectric 10 deposited over the floating gate 120.
8 inclusive. A third layer 150 of polysilicon is deposited on the interpoly dielectric 108 to form a word line control gate. Each floating gate 120
And the shape of the oxide structure 126 results in the formation of a trench over the floating gate as the polysilicon layer is deposited on the interpoly dielectric.

The design of the floating gate used in the present invention will be described in detail. FIG. 2 shows an embodiment of a floating gate according to the present invention. As shown
The floating gate 220 is divided into three regions from left to right. A first end region 201 located near the first side end 211, a second end region 203 located near the second side end 213, and a center direction of the floating gate laterally with respect to the side ends 211 and 213; And a central region 202 located at The thickness of the floating gate 220 varies between different regions to form a bonding surface with contoured topography. In the contoured topography, the first and second end regions form first and second raised edges 218 and 224. Central area 202
The floating gate is thinner in the vertical direction compared to the edge region, thus forming a concave center surface 240. Floating gate 220 is formed from top and bottom polysilicon layers 222 and 223, although additional polysilicon layers can be included in floating gate 120. A bottom polysilicon layer 223 extending between the oxide layers 226;
Then, it comes into contact with tunnel oxide layer 103 on substrate 100.
In one embodiment, the upper polysilicon layer 222,
More specifically, the upper portion of upper polysilicon layer 222 is contoured to provide a mating surface for floating gate 120.

Preferably, the first and second raised ends 218 and 224 are substantially identical, and the discussion of the first raised end 218 applies equally to the second raised end 224. . The vertical thickness of the rising edge 218 is substantially uniform, and the rising edge 218 has an oxide boundary 228 substantially perpendicular to the oxide layer 126 (FIG. 1) and an oxide boundary 2
An upper surface or plateau 236 that is orthogonal to 28 and / or horizontal to substrate 100 and is defined by an inner vertical surface 244 that extends from the upper surface to intermediate surface 240. In a preferred embodiment, the inner vertical surface 244 is
6 and is substantially perpendicular to both the recessed intermediate surface 240. For discussion, oxide boundary 228, top surface 23
6, and the inner surface 244 can be represented by tangent planes A, B, and C, respectively. The tangent planes A, B, and C can be referenced with respect to any linearly shaped portion of the corresponding floating gate surface. In this regard, the angle formed between plane A and oxide structure 226, the angle formed between planes A and B, the angle formed between planes B and C, and the plane C and intermediate The angles formed with the surface 240 are each about 90 degrees. The junction or connection of each of the oxide boundary 228, the top surface 236, and the inner vertical surface 224 may be squared, rounded, or smooth or shaped. The depth of the floating gate in the central region can be varied, as shown by the central surface 240 ', such that the thickness of the central region 202 is greater or less than the height of the oxide structure 226. As shown in FIG. 3C, the thickness of the central region for the oxide structure can be varied by the degree of oxide dipback. Additional raised edges or walls can be formed or integrated into the floating gate to increase the coupling ratio and surface area between the floating gate 220 and the control gate.

One advantage of the present invention is that it provides a floating gate 120 having an increased bonding surface. The contoured bonding surface illustrated in the embodiments described above can be compared to the sum of the lengths of the oxide boundary 228, the top surface 236, the inner vertical surface 224, and the concave center surface 240. The sum of the sum of the contoured bonding surfaces represents an increase relative to the prior art. The increase in coupling surface is directly correlated to the coupling ratio between the floating gate and the control gate, which occupies less area on the substrate 100, thereby reducing the overall size of the memory cell. Further, the operating voltage of the flash EPROM can be reduced and the circuit can be simplified. Another advantage of the reduced size of the floating gate is that the present invention avoids a floating gate structure in which a laterally extending or winged floating gate extends so as to vertically overlap the source / drain diffusion region. It is. In this way, the cell structure of the present invention can reduce drain coupling ratio and drain leakage when the cell is programmed. Similarly, the cell structure of the present invention can reduce the source coupling ratio during the FN erase operation.

Referring to FIG. 2, the first and second end regions 2
The vertical thickness of the floating gate at 01 and 203 optionally ranges from 100 to 10,000 Angstroms, preferably from 1200 to 140
0 Angstrom. The vertical thickness of 202 in the central region of the floating gate is optionally between 0 and 10,
000 Angstroms, preferably 0
Or 3600 angstroms. The vertical thickness of the upper polysilicon layer 222 is optionally between 100 and 2000
It is preferably between 300 and 1000 over the range of Angstroms. The bottom polysilicon layer 223 optionally ranges from 50 to 2000 Angstroms, and is preferably 400 to 1000 Angstroms. Oxide structure 226 preferably has a thickness of 4
000 angstroms or less. Tunnel oxide layer 1
03 is preferably in the range of 50 to 300 angstroms. The lateral length of the first and second end regions 201 and 203 is preferably in the range of 100 to 200 Angstroms, and preferably in the range of 300 to 1000 Angstroms. The lateral length of the central region 202 is preferably in the range of 100-6000 Angstroms, and is preferably 100-5000 Angstroms.

FIGS. 3A-3I show a memory cell according to the invention,
More specifically, a first embodiment for manufacturing an array of floating gates is shown. As shown in FIG. 3A, a relatively thin tunnel oxide layer 303 is grown on the substrate, preferably with a thickness of about 100 Å. In the embodiment as shown in FIG. 7, the substrate comprises a p-type substrate. Next, a conductive layer such as a first polysilicon layer 304 for forming a floating gate is deposited on the tunnel oxide layer 303. Silicon nitride (Si3N4)
An insulating or masking layer 306 made of such a material is sequentially deposited on the first polysilicon layer 304. The masking layer 306 is formed on the tunnel oxide layer 303 by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECV).
D).

As shown in FIG. 3B, the first polysilicon layer 304 and the masking layer 306 are etched to form a pattern of polysilicon-nitride pillars on the substrate 300. Preferably, the pillars are defined by a photomasking process. In this step, the dopant is
It is used to form diffusion regions 314 and 315 between 30. This can be achieved using conventional ion implantation methods, although chemistry or other similar steps can be used. Preferably, the n-type dopant used to form the diffusion region is implanted in the substrate 300.

FIG. 3C shows an oxide structure 326 deposited between individual polysilicon-nitride pillars. Next, the polysilicon-nitride pillars and oxide layer 326 are planarized, preferably by chemical mechanical polishing (CMP). The planarization causes the oxide structure 326 to be flush with the horizontal surface of the pillar masking layer 306. Oxide structure 326 and masking layer 3
Another method of planarizing 06 involves etching the oxide structure flush with the masking layer 306. Oxide structure 326 insulates polysilicon layer 304 from electron leakage while one or more subsequent polysilicon depositions (step 3D).
) To give the alignment structure that determines the height. In this way, the height of oxide structure 326 can be used to determine the overall height of the floating gate. Oxide structure 3
26 can be deposited on substrate 300 by a number of methods, including LPCFD, PECVD, and high density plasma CVD (HDPCVD).

As shown in FIG. 3D, the masking layer 306
Is removed from the polysilicon-nitride pillars by a wet etching method to remove first polysilicon layer 304 between oxide structures 326.
Is exposed. The resulting structure has a step topography that forms an aligned structure for subsequent deposition of an additional polysilicon layer.

Next, FIG. 3E shows the first polysilicon layer 304.
And a second layer 324 of polysilicon deposited over the oxide structure 326. Second polysilicon layer 324 continuously extends over oxide structure 326 and first polysilicon layer 304. As shown, the combination of the first and second polysilicon layers 304 and 324 is thickest near the oxide structure 326. Thus, the oxide structure 326 forms the contour of the floating gate during the polysilicon fabrication process.

A second polysilicon layer 324 can be used to define the floating gate profile. FIG. 3E shows a state in which the second polysilicon layer 324 is deposited to form an acute angle of 90 degrees.
May be deposited to form more rounded corners.

As shown in FIG. 3F, the second polysilicon layer 324 is removed from the top of the oxide layer 326, preferably by a CMP process. Alternatively, if a thin film is used to separate the first polysilicon layer 304 from the second polysilicon layer 324, the second polysilicon layer 324 can be removed by dry etching. The second polysilicon layer 324 has a raised edge 33 having an increased thickness near the oxide structure 326.
4 Preferably, the space defined by oxide structure 326 is a rectangular depression.

As shown in FIG. 3G, the oxide structure 326 is dipped back to provide a new top surface 336 below the rising edge 334 of the second polysilicon layer 324. Preferably, the recessed intermediate surface 3 of the polysilicon structure
40 is above or flush with oxide top surface 336.
The height of oxide structure 326 after dipback is preferably between 100 and 5000 angstroms. Similarly, the height of the vertical layer 330 is preferably between 100 and 10,000 angstroms.

As shown in FIG. 3H, a dielectric layer 316 is deposited over the second polysilicon layer 324 and the oxide structure 326. In a preferred embodiment, dielectric layer 316 has an oxide thickness in the range of 50 to 500 Angstroms.
Including a nitride-oxide layer.

As shown in FIG. 3I, the third polysilicon
Layer 360 is deposited as a word line gate control. In this way, the bonding surface for each floating gate is defined by the rising edge 334 and the recessed intermediate surface 340. Rising edge 334 provides oxide boundary 128, top surface 136, and inner vertical surface 144 shown in FIG. The third polysilicon layer 360 may include a polysilicon layer similar to the first and second layers, or alternatively, may include amorphous polysilicon.

Several other advantages of the present invention can be achieved as a result of the use of a self-aligned structure. In particular, the self-alignment of the second polysilicon layer can prevent the conductive layer from extending over the substrate region including the diffusion region. This reduces drain coupling and therefore increases coupling between the floating gate and the control gate.

Another design of the floating gate used in the present invention will now be described in detail. FIG. 4 shows another embodiment of a floating gate 420 according to the present invention. As shown, the floating gate 420 is divided into three regions from left to right. A first end region 401 located near the first side end 411, a second end region 413 located near the second side end 413, and side ends 411 and 413;
And a central region 402 located laterally to the center of the floating gate. Floating gate 42
The thickness of 0 differs between the different regions to form an upper binding surface with contoured topography. In the contoured topography, the first and second end regions form first and second rising edges 418 and 424. The floating gate in the central region 402 is vertically thinner than the end regions 401, 403, thus forming a concave central surface 440. Floating gate 4
20 includes a single polysilicon layer 423 formed by a single manufacturing process. The polysilicon layer 423 is an oxide layer 4
26 and contacts the tunnel oxide layer 103 on the substrate 100 (as shown in FIG. 1).

Preferably, the first and second rising edges 4
18 and 424 are substantially identical. For this reason, the discussion of the first rising edge 418 is similarly made for the second rising edge 42.
4 is applicable. The rising edge 418 is
6 (FIG. 1) and an oxide boundary 428, which may be substantially perpendicular to the substrate 100 and a horizontal and / or oxide boundary 4
28, and an inner vertical surface 4 extending from the upper surface 436 to the central surface 440.
44, and at least three floating gate surfaces. As in the previous embodiment, the thickness of rising edge 418 is substantially uniform between oxide boundary 428 and inner vertical surface 444. For discussion, oxide boundary 428, top surface 436, and inner surface 444 may be represented by tangent planes A, B, and C, respectively. In this regard, between plane A and oxide structure 426, between planes A and B, between planes B and C, plane C and intermediate surface 4
The joints or connections formed between the 40 are preferably about 90 degrees each. The tangent planes A, B and C are referenced with respect to any linearly shaped portion of the corresponding floating gate surface so that the respective joint can be squared, rounded or otherwise smoothly shaped. As shown at the central surface 440 ', the depth of the floating gate in the central region can be varied such that the thickness of the central region is greater or less than the height of the oxide structure 426. Additional rising edges or walls can be formed or integrated into the floating gate to increase the surface area and coupling ratio between the floating gate 420 and the control gate.

As in the previous embodiment, one advantage of the present invention is that it provides a floating gate 420 with an increased bonding surface. The bonding surface contoured as exemplified in the above-described embodiment has an oxide boundary 4
28, the top surface 436, the inner vertical surface 444, and the concave center surface 440 are equal in length and represent an increase in the bonding surface compared to the prior art.

Referring to FIG. 4, the vertical thickness of the first and second end regions 401 and 403 of the floating gate is optionally in the range of 100 to 10,000 Angstroms, preferably 1200 to 4000 Angstroms. . Central area 40 of floating gate
The vertical thickness of 2 is optionally in the range of 0 to 10,000 angstroms, preferably 0 to 3600 angstroms. Tunnel oxide layer 103 preferably ranges from 40 to 300 angstroms.
The lateral length of first end region 201 and second end region 203 is preferably in the range of 100-2000 Angstroms, and preferably 300-1000 Angstroms. The lateral length of the central surface 202 is preferably in the range of 100-6000 Angstroms, and is preferably 1000-5000 Angstroms.

FIGS. 5A-5I illustrate a method of fabricating a memory cell according to the present invention, and more particularly the fabrication of a contoured floating gate formed of material during a single fabrication process. In one embodiment, as shown in FIG. 6, the substrate comprises a p-type substrate. In this embodiment, a sacrificial oxide layer 501 is formed on a substrate 500. And S
An insulating or masking layer 510 such as i ₃ N ₄ is deposited on the sacrificial oxide layer 501.

As shown in FIG. 5B, the masking layer 510
Are etched on the substrate 500 to form a pattern of spaced masking columns. In this step, dopants are used to form diffusion regions 514 and 515 between the polysilicon nitride pillars. Chemical or other similar methods can be used, but this is achieved using conventional ion implantation methods. Preferably, an n-type dopant is used to form the implanted diffusion region in the substrate 500. A photomasking process can be used to define the source and drain diffusion regions.

FIG. 5C shows oxide structure 520 deposited between masking layer 510 and aligned over source and diffusion regions 514 and 515. Oxide structure 520 is preferably formed from CVD oxide. Once deposited,
Oxide structure 520 and masking layer 510 are planarized to be flush with a horizontal plane. Preferably, oxide structure 520 and masking layer 510 are planarized by CMP. In this case, the masking layer 510 serves as a stop layer for planarization. Alternatively, the oxide structure 5
A method of planarizing 20 and masking layer 510 includes etching oxide structure 520. Oxide structure 520 is used to provide an alignment structure for subsequent formation of the polysilicon layer. This allows the height of the entire floating gate to be determined by the height of the oxide structure 520. Oxide structures can be deposited on substrate 500 in a number of ways, including LPCFD, PECVD, and HPCVD.

FIG. 5D shows that the masking layer 510 has been removed, preferably by a wet etching process. In addition, an oxidation dip is performed to remove the sacrificial oxide layer 501. The resulting structure has a step topography that forms an alignment structure for additional polysilicon layers that are subsequently deposited.

FIG. 5E shows a tunnel oxide layer 503 grown on the substrate 500 between the diffusion regions 514 and 515. Then, a first layer 530 of polysilicon is deposited on the substrate 500 and the oxide structure 520. As shown in FIG. 5E, the polysilicon layer 530 aligns on the substrate 500 according to the step topography provided by the oxide structure 520. As shown, the polysilicon layer 530 is thickest on the oxide structure 520 side. Thus, the oxide structure 520 allows a contoured floating gate to be formed during the polysilicon fabrication process.

As shown in FIG. 5F, a polysilicon layer 53 is formed.
Zero is removed from the upper surface 555 of the oxide structure 520.
Preferably, the polysilicon layer 530 is removed by CMP.

As shown in FIG. 5G, the oxide structure is dipped back to form a new top surface 555 '. The polysilicon layer 530 forms a vertical layer 535 in regions corresponding to the first and second end regions 401 and 403 of the floating gate in FIG. Similarly, the center surface 540 is recessed with respect to the vertical layer 535 according to the center surface 440 of FIG.

FIG. 5H shows a dielectric layer 506 and a second layer 560 of polysilicon deposited as word line gate controls. In this way, the bonding surface of each floating gate is defined by the vertical layer 535 and the concave center surface 540. Here, the vertical layer 535 of each polysilicon structure is used.
Provides the oxide boundary 428, top surface 436, and inner vertical surface 444 shown in FIG. Second polysilicon layer 56
The 0 may include polysilicon similar to the first polysilicon layer, or alternatively may include amorphous polysilicon. The resulting floating gate manufactured by this preferred method can increase the bonding surface by more than twice as much as that obtained by the prior art.

FIG. 6 shows a flash EPRO according to the present invention.
4 shows a drain-source-drain structure of an M circuit. The circuit includes a first local bit line 610 and a second local bit line 611. First and second local bit lines 61
0 and 611 are realized by embedded diffusion as described later. Also included is a local virtual ground line 612 implemented by embedded diffusion. A plurality of floating gates, drains and sources are connected to the local bit line 61.
0, 611 and local virtual ground line 612. The sources of the plurality of transistors are coupled 612 to a local virtual ground line. The drain of the first column of transistors, generally indicated at 613, is connected to the first local bit line 61
0, and the drain of the second column of transistors, generally indicated at 614, is connected to a second local bit line 611
Is combined with The gate of the floating gate transistors to no word line WL ₀ is coupled to WL _N. Here, each word line (eg, WL1) is coupled to the gate of a transistor (eg, transistor 616) in the second column 614. Therefore, transistors 615 and 616
Can be considered as one two-transistor cell with shared source diffusion.

As shown in FIG. 6, a first global bit line 617 and a second global bit line 618 are associated with each drain / source / drain block. First global bit line 617 is coupled to the source of upper block select transistor 619 via metal-to-diffusion contact 620. Similarly, the second bit line 618 is connected to the metal-diffusion contact 62.
2 is coupled to the source of the upper block select transistor 621. Upper block select transistors 619, 6
The drain of 21 is coupled to first and second local bit lines 610 and 611, respectively. The gates of the upper block select transistors 619, 621 are controlled by the upper block select signal TBSEL on line 623.

The local virtual ground line 612 is connected to the virtual ground terminal crossing conductor 6 through the bottom block selection transistor 625.
24. The drain of bottom block select transistor 625 is coupled to local virtual ground line 612. The source of bottom block select transistor 625 is coupled to conductor 624. The gate of the bottom block select transistor 625 is connected to the bottom block select signal BBSEL that
Is controlled by In a preferred system, conductor 6
24 is an embedded diffusion conductor that extends to the metal-diffusion contact in a horizontally displaced position in the array, providing a contact to the vertical metal virtual ground bus.

Global bit lines extend vertically through the array to respective column select transistors 627, 628 via which the selected global bit line is coupled to a sense amplifier and a program data circuit (not shown). You. Thus, the source of column select transistor 627 is coupled to global bit line 617, the gate of column select transistor 627 is coupled to column decode signal Y1, and column select transistor 627
Are coupled to conductor 629.

The present invention can be used in alternative memory array configurations. For example, U.S. Patent No. 5,696,019 to Chang discloses a memory device configuration suitable for the present invention that includes multiple columns of memory cells sharing one or more bit lines. This configuration is based on a source-drain cell structure where each column of cells has a single buried diffused local source line. An isolation structure, such as a trench oxide, is located between each column of cells.

Memory cell operation can be achieved in one of several ways. In this embodiment, a first positive voltage value is applied to the control gate and a second positive voltage value is applied to the buried drain diffusion and the buried n
The memory cell is programmed by setting the type source diffusion to 0 volts. Under these conditions, electrons tunnel from the valence band to the conduction band, leaving holes in the valence band. The voltage on the control gate draws electrons toward the floating gate. Electrons are accelerated by a strong vertical electric field between the drain diffusion and the control gate. Some of the electrons then become "hot" electrons with sufficient energy and are injected into the floating gate 120 (FIG. 1) through the tunnel dielectric layer 106 (shown in FIG. 1).

Erasing is accomplished by FN tunneling from the floating gate to the buried n-type source diffusion. During erase, a negative voltage is applied to the control gate, a positive voltage is applied to the source region, and the drain is floated. As a result, FN tunneling erasure of electrons from the floating gate to the source side occurs.

In another variation, FN tunneling programming (electron tunneling from the floating gate to the drain side via FN tunneling) and channel erasing (from channel via FN tunneling). Electron to the floating gate) can be used. Further, the memory cells are FN tunneling
Programming (electrons from channel to floating gate by FN tunneling) and FN channel erasing (electrons from floating gate to channel by FN tunneling) can be used.

The read is performed by applying a positive voltage to the drain diffusion and applying a positive voltage to the control gate to bring the source to zero.
This can be achieved by bolting. When the floating gate is charged, the threshold voltage for conducting the n-channel transistor is reduced below the voltage applied to the control gate during reading. Thus, a charged transistor will not conduct during a read operation, and an uncharged transistor will conduct. The non-conductive state of the cell is
It can be interpreted as a binary 1 or 0 depending on the polarity of the detection circuit.

The voltages required for programming, erasing, and / or reading operations depend in part on the coupling ratio between the floating gate and the control gate of the memory cell. The voltage across the floating gate can be expressed as:

V _FG = V _CG [C _CR / (C _CR + C _K )] In the above equation, C _CR is a capacitive coupling ratio between the floating gate and the control gate. Factor CK represents the capacitive coupling of the floating gate across tunnel oxide layer 206 for programming, erasing, or reading. As shown in the above equation, the higher the coupling ratio between the floating gate and the control gate, the more equal the voltage across the floating gate will be compared to the voltage across the control gate. Thus, as the coupling ratio between the floating gate and the control gate increases, the voltage required to achieve programming, erasing, or reading decreases.

Some prior art memory devices provide a floating gate with a larger coupling surface to increase the coupling ratio between the floating gate and the control gate. This was conventionally achieved by increasing the lateral size of the floating gate on the substrate. Thus, prior art floating gates occupy a significant percentage of the area allocated to the memory array. In contrast, the present invention provides a floating gate with reduced lateral size but comparable. More specifically, the present invention provides a floating gate having a reduced lateral dimension but maintaining or increasing the coupling ratio between the floating gate and the control gate.

The preferred embodiments of the invention described above have been made for purposes of illustration. There is no intention to limit the invention to the exact shape disclosed. Many variations and modifications will be apparent to those skilled in the art. It is intended that the scope of the invention be defined by the following claims and their equivalents:

[Brief description of the drawings]

FIG. 1 is a diagram showing a memory cell according to the present invention.

FIG. 2 is a diagram showing an embodiment of the memory cell of the present invention, in which the deformation of the upper surface of the floating gate is indicated by a virtual line.

3A to 3I show an embodiment of a method of manufacturing a memory cell according to the present invention, and FIG. 3A shows a masking layer, a polysilicon layer, and a tunnel oxide used for manufacturing a memory cell. FIG.

FIG. 3B is a diagram showing a state in which a polysilicon layer and a masking layer are etched to form a pattern.

FIG. 3C illustrates an oxide structure deposited between pillars such that each pillar abuts on the oxide structure.

FIG. 3D shows the masking layer removed to create a step topography between the polysilicon layer and the oxide structure.

FIG. 3E illustrates a second polysilicon layer deposited over a step topography including pillars and oxide structures.

FIG. 3F illustrates a state in which a second polysilicon layer has been etched to selectively remove all polysilicon layers on the oxide structure.

FIG. 3G shows the oxide structure dipped back and removed to form a bonding surface or contoured top on the upper portion of the bonded polysilicon layer with the upper surface shortened. FIG.

FIG. 3H shows an oxide structure and an inter-dielectric layer deposited on a polysilicon layer.

FIG. 3I illustrates the completion of a memory cell with another polysilicon layer deposited on a dielectric layer.

FIG. 4 is a diagram showing another embodiment of the memory cell according to the present invention, in which the deformation of the upper surface of the floating gate is indicated by a virtual line.

5A-5I illustrate one embodiment of a method of manufacturing a memory cell according to the present invention, and FIG. 5A illustrates a tunnel oxide layer, a masking layer, a poly-silicon layer used to manufacture a memory cell. FIG. 4 shows a masking layer grown on a sacrificial oxide layer, showing a combination of silicon layers.

FIG. 5B is a view showing a state in which a masking layer is etched to form a pillar pattern.

FIG. 5C is a view showing a state in which an oxide structure is deposited between columns so that each column comes into contact with the oxide structure.

FIG. 5D illustrates the masking layer removed to form a step topography between the oxide structures.

FIG. 5E illustrates a polysilicon layer deposited on a step topography including an oxide structure.

FIG. 5F shows a polysilicon layer etched to selectively remove all polysilicon layers on the oxide structure.

FIG. 5G illustrates the oxide structure dipped back to shorten the top surface of the oxide structure to form a bonding or contoured top surface on the top portion of the polysilicon layer.

FIG. 5H illustrates an oxide structure and an inter-dielectric layer deposited on a polysilicon layer.

FIG. 6 is a circuit diagram of a nonvolatile memory device that can use the present invention.

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[Procedure amendment]

[Submission date] February 1, 2001 (2001.2.1)

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] All figures

[Correction method] Change

[Correction contents]

FIG. 2

FIG. 3A

FIG. 3B

FIG.

FIG. 3C

FIG. 3D

FIG. 3E

FIG. 3F

FIG. 3H

FIG. 5A

FIG. 3G

FIG. 3I

FIG. 4

FIG. 5B

FIG. 5C

FIG. 5D

FIG. 5E

FIG. 5G

FIG. 5F

FIG. 5H

FIG. 6

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Chi-Yan Huan Taiwan Sinchu County Fu Qian Street Lane 6-1 Number 7 (72) Inventor Yun Chang Taiwan Sinchu County Ankan Street Lane 7 Number 2 4F (72) Inventor James Sue United States of America 95070 Saratoga Tricia Way 20409 (72) Inventor Samuel Seapan Taiwan Xinchu Da Sue Road Lane 20 Number 50 20F-3 F-term (reference) 5F001 AA31 AB02 AC02 5F083 EP03 EP22 EP77 ER03 ER16 ER19 ER22 GA09 JA33 KA06 KA12 NA08 PR40 5F101 BA13 BB02 BC02

Claims (50)

[Claims] 1. A method of forming a contoured floating gate for use in a floating gate memory cell, the method comprising: first and second oxide structures spaced apart from each other; Forming a polysilicon layer over and between the floating gate region such that the polysilicon layer formed within the floating gate region is near the first end region near the first oxide structure and near the second oxide structure; Having a second end region and a central region located laterally between the first and second end regions, wherein the first and second end regions each have a vertical thickness greater than a vertical thickness of the central region. And removing a portion of the polysilicon layer within the floating gate region such that the vertical thickness of the first and second end regions remains greater than the vertical thickness of the central region. 2. The method according to claim 1, wherein the first end region and the second end region are first and second.
The method of claim 1, further comprising removing a portion of the first and second oxide structures to extend vertically over the oxide structure. 3. The method of claim 1, wherein forming a polysilicon layer on the first and second oxide structures spaced apart and the floating gate region includes forming an outer surface and an upper surface near the outer surface. The method of claim 1, comprising forming an end region, and comprising having the end region have a substantially uniform thickness between an outer surface and a respective inner surface. 4. The method of claim 1, wherein removing a portion of the polysilicon layer comprises removing the first oxide structure, the second oxide structure, the first end region,
The method of claim 1, comprising planarizing the second end region. 5. The method of claim 1, wherein the top surfaces of the first end region and the second end region are substantially parallel to the substrate under the floating gate. 6. The method of claim 1, wherein the floating gate is formed from a single polysilicon layer. 7. The method of claim 1, wherein forming a second polysilicon layer on the first polysilicon layer comprises forming a second polysilicon layer over the central region of the floating gate.
The method of claim 1, comprising forming a polysilicon layer. 8. The method of claim 1, wherein forming a second polysilicon layer on the first polysilicon layer comprises forming a second polysilicon layer on the central region of the floating gate at about 300 to 1000 Angstroms.
The method of claim 1, comprising forming a polysilicon layer. 9. The method of claim 1, wherein forming a first polysilicon layer near the substrate in the floating gate region comprises forming a first polysilicon layer of about 50 to 2000 Angstroms. 10. The method of claim 9, wherein forming a first polysilicon layer on the substrate comprises forming a first polysilicon layer of about 400 to 1000 Angstroms. 11. The step of forming a polysilicon layer on the spaced first and second oxide structures and the floating gate region comprises forming a polysilicon layer on the oxide structure of about 100 to 2000 Angstroms. The method of claim 1, comprising: 12. The step of forming a polysilicon layer on the spaced first and second oxide structures and the floating gate region comprises forming a polysilicon layer of about 300 to 1000 Å on the oxide structure. The method of claim 11, comprising: 13. The step of forming a polysilicon layer over the first and second oxide structures and the floating gate region, wherein the first end has a vertical thickness in the range of about 100 to 10,000 Angstroms. The method of claim 1, comprising forming a region and a second end region. 14. A method of forming a polysilicon layer over the first and second oxide structures and the floating gate region, comprising: a first end region having a vertical thickness in a range of about 1200 to 4000 Angstroms; 14. The method according to claim 13, comprising forming a second end region. 15. The step of forming a polysilicon layer on the first and second oxide structures and the floating gate region, wherein the central region has a vertical thickness in the range of about 0 to 10,000 Angstroms. The method of claim 1, comprising forming. 16. The step of forming a polysilicon layer over the first and second spaced apart oxide structures and the floating gate region forms a central region having a vertical thickness in the range of about 0 to 3600 angstroms. 16. The method of claim 15, comprising: 17. The step of forming a polysilicon layer over the spaced first and second oxide structures and the floating gate region forms a central region having a lateral length in the range of about 100 to 6000 angstroms. The method of claim 1, comprising: 18. The step of forming a polysilicon layer over the spaced first and second oxide structures and the floating gate region forms a central region having a lateral length in the range of about 1000 to 5000 Angstroms. 18. The method of claim 17, comprising: 19. The step of forming a polysilicon layer on the first and second oxide structures and the floating gate region, wherein the first and second oxide structures have a lateral length in the range of about 100 to 2000 Angstroms. 2. The method of claim 1, comprising forming a two-end region. 20. A method of forming a polysilicon layer over the first and second oxide structures and the floating gate region, wherein the first and second oxide structures have a lateral length in a range of about 300 to 1000 Angstroms. 20. The method of claim 19, comprising forming a two-end region. 21. A method of forming a contoured floating gate for use in a floating gate memory cell, comprising: forming a first polysilicon layer in a floating gate region of a substrate; Have a vertical thickness greater than the vertical thickness of the first polysilicon layer.
And forming a second oxide structure on the first and second oxide structures and the first polysilicon layer.
Forming a polysilicon layer, wherein the first and second polysilicon layers combine to form a floating gate in the floating gate region, the floating gate being in contact with a first end region near the first oxide structure; A second end region near the oxide structure and a central region located in a central direction of the floating gate transverse to the first and second end regions;
The first end region and the second end region have a vertical thickness greater than the vertical thickness of the central region, and the first and second oxide structures are formed over the first and second oxide structures to form a contoured floating gate. Removing the silicon layer. 22. The method of claim 17, further comprising removing a portion of the first and second oxide structures such that the first and second end regions extend vertically above the first and second oxide structures. The method of claim 21. 23. Forming a polysilicon layer on the first and second oxide structures spaced apart and the floating gate region includes forming an end region of the floating gate including an outer surface and an upper surface near the outer surface. 22. The method of claim 21, including forming, wherein the end regions have a substantially uniform thickness between the outer surface and the respective inner surface. 24. The method of claim 21, wherein removing a portion of the polysilicon layer includes planarizing a first oxide structure, a second oxide structure, a first end region, and a second end region. Item 24. The method according to Item 23. 25. The method of claim 23, wherein the top surfaces of the first end region and the second end region are substantially parallel to the substrate under the floating gate. 26. A method of manufacturing a floating gate memory cell, comprising: providing a substrate; forming source and drain regions on the substrate; depositing an insulating layer on the source and drain regions; Forming a contoured floating gate overlying the insulating layer between the regions, a polysilicon layer over the floating gate region between the first and second oxide structures and the first and second oxide structures; Forming, a polysilicon layer in the floating gate region, a first end region near the first oxide structure, a second end region near the oxide structure, and lateral to the first and second end regions. And a first end region and a second end region each having a vertical thickness greater than a vertical thickness of the central region, wherein the first and second end regions have a vertical thickness that is greater than a vertical thickness of the central region. Forming by removing a portion of the polysilicon layer in the floating gate region such that the vertical thickness of the second end region remains greater than the vertical thickness of the central region. 27. The method of claim 27, further comprising removing a portion of the first and second oxide structures such that the first end region and the second end region extend vertically above the first and second oxide structures. 27. The method of claim 26. 28. Forming a polysilicon layer on the first polysilicon layer between the first and second oxide structures and the first polysilicon layer between the first and second oxide structures may include forming the polysilicon layer on the outer surface and near the outer surface. 27. The method of claim 26, comprising forming an end region of the floating gate including an upper surface, the end region having a substantially uniform thickness between the outer surface and the respective inner surface. 29. The method of claim 29, wherein removing a portion of the polysilicon layer includes planarizing the first oxide structure, the second oxide structure, the first end region, and the second end region. Item 29. The method according to Item 26. 30. The method of claim 26, wherein the top surfaces of the first end region and the second end region are substantially parallel to the substrate under the floating gate. 31. The method according to claim 26, wherein the floating gate is formed by a single polysilicon layer. 32. Forming a second polysilicon layer on the first polysilicon layer includes forming a second polysilicon layer of about 100 to 7000 angstroms on a central region of the floating gate. 27. The method of claim 26. 33. Forming a second polysilicon layer on the first polysilicon layer includes forming a second polysilicon layer of about 300 to 1000 Angstroms on a central region of the floating gate. 27. The method of claim 26. 34. The method of claim 26, wherein forming a first polysilicon layer near the substrate in the floating gate region comprises forming a first polysilicon layer of about 50 to 2000 Angstroms. 35. The method of claim 34, wherein forming a first polysilicon layer on the substrate comprises forming a first polysilicon layer of about 300 to 1000 angstroms. 36. The step of forming a polysilicon layer on the spaced apart first and second oxide structures and the floating gate region comprises forming a polysilicon layer of about 100 to 2000 Angstroms on the oxide structure. 27. The method of claim 26, comprising: 37. The step of forming a polysilicon layer on the spaced first and second oxide structures and the floating gate region comprises forming a polysilicon layer of about 300 to 1000 angstroms on the oxide structure. 37. The method of claim 36, comprising: 38. The step of forming a polysilicon layer on the first and second oxide structures and the floating gate region, wherein the first end has a vertical thickness in the range of about 100 to 10,000 Angstroms. 27. The method of claim 26, comprising forming a region and a second end region. 39. The step of forming a polysilicon layer over the spaced first and second oxide structures and the floating gate region comprises a first end region having a vertical thickness in the range of about 1200 to 4000 Angstroms. 39. The method of claim 38, comprising forming a second end region. 40. The step of forming a polysilicon layer over the spaced first and second oxide structures and the floating gate region comprises forming a central region having a vertical thickness in the range of about 0 to 10,000 Angstroms. 27. The method of claim 26, comprising forming. 41. The step of forming a polysilicon layer over the spaced first and second oxide structures and the floating gate region forms a central region having a vertical thickness in the range of about 0 to 3600 angstroms. 41. The method of claim 40, comprising: 42. The step of forming a polysilicon layer over the spaced first and second oxide structures and the floating gate region forms a central region having a lateral length in the range of about 100 to 6000 angstroms. 37. The method of claim 36, comprising: 43. The step of forming a polysilicon layer over the spaced first and second oxide structures and the floating gate region forms a central region having a lateral length in the range of about 1000 to 5000 Angstroms. 43. The method of claim 42, comprising: 44. The step of forming a polysilicon layer on the first and second oxide structures and the floating gate region, wherein the first and second oxide structures have a lateral length in the range of about 100 to 2000 Angstroms. 27. The method of claim 26, comprising forming a two-end region. 45. The step of forming a polysilicon layer over the spaced first and second oxide structures and the floating gate region, the first and second oxide structures having a lateral length ranging from about 300 to 1000 Angstroms. 45. The method of claim 44, comprising forming a two-end region. 46. A method of forming a floating gate memory cell, comprising: providing a substrate; forming source and drain regions on the substrate; depositing an insulating layer on the source and drain regions; Forming a contoured floating gate located on an insulating layer between the regions, forming a first polysilicon layer in the floating gate region of the substrate, and forming an oxide structure on opposite ends of the floating gate region The first and second oxide structures have a vertical thickness smaller than the vertical thickness of the first polysilicon layer, and the second oxide structure has a second thickness on the first and second oxide structures.
Forming a polysilicon layer, wherein the first and second polysilicon layers are combined to form a floating gate in the floating gate region, the floating gate being oxidized with the first end region near the first oxide structure; Second close to object structure
An end region and a center region located transversely to the first and second end regions in a center direction of the floating gate, and the first end region and the second end region are greater than a vertical thickness of the center region A method comprising forming by removing polysilicon on first and second oxide structures to form a contoured floating gate having a vertical thickness. 47. The method of claim 47, further comprising removing a portion of the first and second oxide structures such that the first end region and the second end region extend vertically above the first and second oxide structures. 46. The method according to 46. 48. Forming a polysilicon layer on the first polysilicon layer between the first and second oxide structures and the first and second oxide structures between the first and second oxide structures may include forming an outer surface and near the outer surface. 47. The method of claim 46, comprising forming an end region of the floating gate including a top surface, the end region having a substantially uniform thickness between the outer surface and the respective inner surface. 49. Removing the portion of the polysilicon layer includes planarizing the first oxide structure, the second oxide structure, the first end region, and the second end region. Item 46. The method according to Item 46. 50. The method of claim 46, wherein the top surfaces of the first end region and the second end region are substantially parallel to the substrate under the floating gate.