JP2002110804A - Semiconductor device - Google Patents

Abstract

(57) [Summary] [Problem] Fusing with a low-power laser is possible,
Provided is a semiconductor device having high SM reliability in an adjacent fuse wiring portion after fusing. SOLUTION: A wiring layer, an insulating film formed on the wiring layer, a connecting via and a dummy via formed on the insulating film for connecting to the wiring layer, and at least one dummy via in a fuse wiring And a fuse electrode having:

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to an improvement in a fuse electrode of a semiconductor device.

[0002]

2. Description of the Related Art As shown in FIG. 4, a fuse used in a semiconductor device is formed of one layer (a layer under the uppermost layer, n-1 layer in the figure) 41a and 41b of a multilayer wiring (n layers). It is formed using a part (41b) of them. However, the wiring thickness of the fuse portion, the pitch between the fuses, and the like are determined in consideration of the multilayer wiring function (current density, wiring capacity, and the like) rather than the requirement of the fuse characteristics. as a result,
Due to recent miniaturization of wiring, high current density, and further reduction in area, the wiring film thickness of a wiring layer in which a fuse portion is formed has been increased, and the fuse pitch has been reduced.

[0003] On the other hand, the fuse portion is generally blown by laser light. In recent years, a high power laser beam has been required due to an increase in the film thickness of wiring. Therefore, it is required to suppress the power of the laser beam so that even the adjacent fuse portion is not blown. For this reason, the design has been performed based on a trade-off between the film thickness of the wiring and the power of the laser beam.

However, in recent years, the introduction of Cu wiring, which is a metal having a higher melting point than Al, makes it more difficult to satisfy both of these characteristics, and urgent measures are required to solve this problem. I have.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device which can be blown by a low-power laser and has a high SM reliability in an adjacent fuse wiring portion after the blow. The purpose is to provide.

[0006]

In order to solve the above-mentioned problems, the present invention provides a wiring layer, an insulating film formed on the wiring layer, and a connection to the wiring layer formed on the insulating film. A connection via, a dummy via deeper than the connection via, and an upper wiring having a fuse electrode wiring having the dummy via in the wiring as a part of the wiring.

[0007] In the semiconductor device of the present invention, it is preferable that the film thickness of the wiring constituent material in the dummy via is 0.75 or less as a ratio to the film thickness of the fuse electrode wiring.

The fuse electrode is preferably made of Al or an Al alloy and formed by sputtering. However, it is also possible that the fuse electrode is made of Cu or Cu alloy and formed by electrolytic plating.

The connection via can be a plug made of a W layer formed by selective CVD.

Hereinafter, a semiconductor device having a fuse electrode structure according to the present invention will be described in more detail.

According to the present invention, it is possible to reduce the blowout portion of a fuse electrode while maintaining the soundness of the fuse electrode by forming a connection via and a dummy via in an interlayer insulating film and then forming a film in the dummy via. It is a feature.

As a method of forming the fuse electrode portion, a film having a high anisotropy is desirable. For this reason, physical vapor deposition such as sputtering is desirable, but there is no problem with a film forming method combining a sputtering method and an electrolytic plating method. For example, in the case of Cu wiring, if Cu is formed as a seed layer for plating by a few hundred nm (solid film conversion) after forming a barrier metal, the dummy vias are deeper than the connection vias. The thickness is thinner, and the film resistance is higher. Thereafter, when electrolytic plating is performed, the supply of electrons is insufficient only in the dummy vias, so that the plating film thickness can be reduced.

In order to increase the reliability of laser fusing, it is desirable to provide a plurality of dummy vias. In addition, when the laser output is high, the temperature of the adjacent wiring increases, deteriorating the SM resistance of the adjacent wiring. Therefore, the film thickness at the bottom of the dummy via is 0.75 or less as compared with the wiring film thickness. Is desirable.

Here, in order to control the thickness of the bottom of the dummy via, the thickness of the wiring in the uppermost layer varies depending on the type of the LSI. By controlling the amount of over-etching and the distance between the substrate and the target at the time of sputtering, the aspect ratio and the degree of embedding of the dummy via are changed, thereby enabling control.

[0015] The above point is that, for the purpose of suppressing the oxidation of the pad portion of the uppermost layer of Cu, when a fuse electrode is provided on the Al layer in the process of providing the Al layer, in the case of ordinary Al multilayer wiring, and further by selective CVD The same applies to the case of Al multilayer wiring using W vias.

In the case of a W via process by selective CVD,
In a dummy via having no lower Al wiring at the bottom, there was no embedding with W, and when an upper Al wiring was formed, a thin film portion could be formed at the bottom of the dummy via.

As described above, according to the present invention, it is possible to provide a fuse wiring having a thin film portion in a part of the thickest uppermost wiring layer in the n-th layer. It is also possible to reduce the chip area by narrowing the pitch between the fuse wirings, which was necessary for the above.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention. In FIG. 1, a lower wiring (not shown) was formed on a Si substrate 1 on which an active area (not shown) was formed, and then a Cu wiring layer 2 below a fuse formation planned area was formed.

Next, after forming the interlayer insulating film 3 to a desired thickness and embedding the Cu wiring layer 2, a via 4a was formed in the interlayer insulating film 3 by lithography and then RIE. At this time, the dummy vias 4b, 4
c was formed. At this time, 50% overetching was performed as RIE. As a result, the dummy vias 4bb, 4bb,
As shown in FIG. 1, the aspect ratio of c
After the film formation, the film was formed such that sin θ = 0.6.

Although the via 4a has a depth to reach the Cu wiring layer 2 because of the presence of the Cu wiring layer 2, the via 4a does not exist in the formation regions of the dummy vias 4b and 4c. 4a, the dummy vias 4b, 4c have an increased aspect ratio.

Next, a surface treatment is performed on the bottom of the via 4a,
After removing the oxide material on the lower wiring surface, the TaN / Ta
A laminated film (not shown) was continuously formed to a thickness of 400 nm / 5 nm. Then, the degree of vacuum is further increased to 1.0 × 10 ^−5.
While maintaining Pa, Al-
A 0.5 wt% Cu film 5 was formed at 250 ° C. to a thickness of 1200 nm.

Thereafter, the Al-0.5 wt% Cu film 5 was patterned by lithography and RIE steps to form the uppermost wiring layer including the fuse wirings 7a and 7b having dummy vias 4b and 4c formed in the wiring.

As a comparative example, a semiconductor device having an Al fuse (1200 nm) formed by an ordinary dual damascene process was prepared.

The semiconductor device thus formed was subjected to a fusing test using a laser fusing apparatus. The fuse used in the test had an L / S of 1 / 2.5 μm
It is.

As a result of the test, the fuse structure of the semiconductor device according to the first embodiment of the present invention could be disconnected with a laser power of 1/10 as compared with the fuse according to the comparative example.
As a result of the evaluation of the electrical characteristics, no abnormality was found in the adjacent fuse wiring portion, and no SM failure was observed even after the standing test at 150 ° C. for 1000 hours.

On the other hand, in the fuse structure according to the comparative material, as described above, in addition to the fact that very large power was required for fusing, 50% of adjacent wirings showed disconnection in electrical characteristics.
As a result of examining the electrical characteristics after the SM acceleration test, the defect rate was 1
A result of 00% was shown.

Embodiment 2 In Embodiment 1, the via 4 is formed in the interlayer insulating film 3 by RIE.
After forming a, 6a, 6b and wiring groove 5, TaN /
A Ta barrier is formed and Cu is formed by anisotropic sputtering.
A film was formed. In this anisotropic sputtering, the bottom of the via, particularly the bottom of the dummy vias 4b and 4c,
A film is formed.

After that, the sputtering Cu
A Cu layer was formed on the film by electrolytic plating. During the electrolytic plating of Cu, as described above, the dummy via 4
At the bottoms of b and 4c, a thin Cu film is formed by anisotropic sputtering. Since the resistivity of such a thin Cu film is high, the connection via 4a is filled 100% by Cu electroplating. In contrast, the thickness of the Cu electroplated film in the dummy vias 4b and 4c was 200 nm.

Then, after performing CMP on the Cu film,
A 0 nm TEOS insulating film and a 600 nm SiN passivation film were formed. As a result, in the uppermost Cu wiring layer in which the fuse was formed, the wiring film thickness of the dummy via portion formed in the fuse wiring was 200 nm with respect to the Cu wiring having a film thickness of 12,000 nm.

In the same manner as in Example 1, as a comparative example, a fuse of ordinary Cu dual damascene wiring having no dummy via and having a thickness of 1200 nm was formed. As in Example 1,
A laser fusing test and a subsequent reliability test were performed and similar results were obtained.

Further, the Cu seed film thickness was changed by controlling the distance between the substrate and the target during Cu sputtering.
After forming Cu fuse wirings changed to 0, 200, 300, 500, 900, and 1000 nm and performing laser fusing, an SM acceleration test of adjacent wirings was performed. As a result, the yield of the wiring having a thickness of 900 nm or less was 100%, whereas the yield of the wiring having a thickness of 1000 nm was deteriorated to 90%. As a result of the analysis of the defective portion, a large number of stress voids were observed, which was due to the influence of heating due to blowing of the adjacent fuse portion.

Embodiment 3 In this embodiment, as shown in FIG. 2, a projection 21 made of, for example, SiN is provided at the bottom of the fuse wiring 14 of the damascene wiring by lithography and RIE. In this state, for example, when Al is sputtered,
The thickness of the Al film 22 at the portion of the protrusion 21 is reduced, and therefore, the Al film 22 can be suitably used as a fuse.

Embodiment 4 FIG. 3 is a diagram showing a cross section of a semiconductor device according to a fourth embodiment of the present invention. After forming the (n-1) layer in which the fuse is to be formed, the TEOS interlayer insulating film was formed to a desired thickness and the connection via 25 and the dummy via 27 were formed by lithography and RIE in the same manner as in Example 1.

Thereafter, when a W plug is formed by selective CVD, a W plug grows in the connection via 25 where a lower wiring exists, but a dummy via where no lower wiring exists does not exist.
The via hole was kept as it was.

Thereafter, a TaN / Ta barrier metal and subsequently an Al-0.5 wt% Cu film were formed to a thickness of 1 μm, and as a result, an Al film having a thickness of 300 nm was formed at the bottom of the dummy via.

On the other hand, as a comparative example, a fuse wiring having no dummy via and a thickness of 1 μm was formed, and a laser fusing test and an SM acceleration test of an adjacent wiring were performed. As a result, the yield was 100% in the present example, whereas the yield was 0% in the comparative example. The laser power at the time of fusing in this example was 1/8 of that in the comparative example.

[0038]

As described above in detail, according to the present invention, by providing a fuse electrode in a dummy via (a fuse wiring has a dummy via), it is possible to blow with a low-power laser. It is possible to obtain a semiconductor device having high SM reliability of the adjacent fuse wiring portion after fusing.

Further, according to the present invention, it is possible to reduce the thickness of the fuse portion without increasing the number of steps even in the case of an upper wiring having a large thickness, and it is also possible to easily achieve a narrow pitch of the fuse. Becomes

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment.

FIG. 2 is a sectional view partially showing a fuse portion of a semiconductor device according to a third embodiment;

FIG. 3 is a sectional view showing a semiconductor device according to a fourth embodiment.

FIG. 4 is a cross-sectional view showing a semiconductor device having a conventional fuse structure.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Si board | substrate 2 ... Cu wiring layer 3 ... Interlayer insulating film 4a ... Via 4b, 4c ... Dummy via 5 ... Al-0.5wt% Cu film 6a, 6b ... Fuse

Continued on the front page F-term (reference) SS04 VV11 WW02 XX03 XX04 XX35 5F038 AV03 AV15 CD18 CD20 EZ14 EZ20 5F064 EE32 FF27 FF32 FF34 FF43

Claims (5)

[Claims] A wiring layer, an insulating film formed on the wiring layer, a connection via formed on the insulating film for connecting to the wiring layer, and a dummy via deeper than the connection via; A semiconductor device, comprising: a fuse electrode wiring having a dummy via in the wiring; and an upper wiring having a fuse electrode wiring as a part of the wiring. 2. The semiconductor device according to claim 1, wherein the thickness of the wiring constituent material in the dummy via is:
2. The semiconductor device according to claim 1, wherein the thickness ratio of the fuse electrode wiring is 0.75 or less. 3. The semiconductor device according to claim 1, wherein said fuse electrode is made of Al or an Al alloy and is formed by sputtering. 4. The semiconductor device according to claim 1, wherein said fuse electrode is made of Cu or Cu alloy, and is formed by sputtering or electrolytic plating. 5. The semiconductor device according to claim 1, wherein said connection via comprises a W layer formed by selective CVD.