JP2002110894A - Circuit package - Google Patents

Abstract

(57) [Problem] To provide a circuit package having a small package module. A conductive strip serving as a base 211 and a parent chip 2 are provided.
2 and the child chip 23, the parent chip 22 is adhered on the base 211 by a flat packaging method, and the child chip 23 having a projection is simultaneously adhered on the parent chip 22 and the base 211 by a flip chip method, The parent chip 22 and the child chip 23 overlap. Therefore, the height of the package composed of the parent chip 22 and the child chip 23 is smaller than the total thickness of the three-layer substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a circuit package.

[0002]

2. Description of the Related Art Integrated circuits (ICs)
Advances in packaging C) generally progress with IC design and manufacturing. With the development of IC technology, the degree of integration has been gradually increased, the number of legs (signal, power supply, ground) at the entrance and exit of the conductor has also increased, and more functions have been integrated into one chip, and the size of the chip has been reduced. It tends to shrink. As a result, traditional electronics packaging technologies are unable to meet the needs of advanced ICs, and manufacturers are successively applying more appropriate packaging technologies, such as flip chip technology, ball grid array (Ball grid array). It employs a Grid Array, BGA), a chip size package (Chip Size / Scale Package, CSP), and a multi-chip module.

Further, in order to increase the processing speed, manufacturers adopt a combination package in actual production, and FIG.
As shown in (1), the parent chip 12 is first adhered on the base 11, for example, the conductor frame 110, and wire bonding is performed by the gold wire 121 to make the parent chip 12 and the conductor frame 110 conductive.
Subsequently, another child chip 13 is covered on the top layer of the parent chip 12 by the flip chip technique, and finally the synthetic resin (Mold
The whole is packaged into one module by the ing compound (14).

[0004]

Although the combination packaging described above can moderately improve the conversion speed of the signal, the overall package module is too large and the gold wire has a loop keying design. However, the volume is too swollen, and the thickness cannot meet the light, thin, short, small and energy-saving needs of portable electronic products.

Accordingly, it is a primary object of the present invention to provide a circuit package having a small package module.

[0006]

According to a first aspect of the present invention, there is provided a circuit package comprising a base, a parent chip, and a child chip, and the base chip includes the parent chip and the child chip. It is placed. The parent chip is attached on the base by a flat packaging method of surface attachment. The child chip having the projection is simultaneously attached to the parent chip and the base by the flip chip method, so that the parent chip and the child chip overlap. Therefore, the signal transmission speed is accelerated, and the size of the packaging, particularly the height, can be effectively reduced.

According to the circuit package of the second aspect of the present invention, the base is formed by a conductor frame. According to the circuit package of the third aspect of the present invention, the base is formed by the substrate of the laminated circuit board.

According to the circuit package of the fourth aspect of the present invention, first, the second layer substrate is overlaid on the lower layer substrate, and the second layer substrate is provided with a through hole for attaching the parent chip. Subsequently, the uppermost layer substrate having a through hole is laid at the same place as the second layer substrate. Each substrate layer is composed of a step-shaped cross section, and the parent chip is attached to a lower layer substrate.
The child chip is attached to the parent chip by flip chip technology, and the child chip is attached to the second layer substrate by a protrusion provided on the outer periphery. The height of the package composed of the lowest layer substrate, the parent chip, and the child chip is lower than the total thickness of the substrate composed of the three layers, so that a multilayer combination substrate is formed.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows a circuit package according to one embodiment of the present invention. It is mainly combined from base, glued chip and flip chip. Base is lead frame 211
Thus, the parent chip 22 is adhered in a flat package (Flat Package) method, which is a basis for receiving each chip. Further, a child chip 23 having a projection is attached on the parent chip 22 by a flip chip method. At the same time, the wire frame 21
1 and is packaged so that the base 21, the parent chip 22, and another child chip 23 of the wire frame 211 are overlapped.

[0010] Further, as shown in FIG. 3, the above-mentioned base 211 can be embodied in another system. The base 31 is in the form of a substrate 311, and generally includes a polyimide (Polyimide film), a laminated circuit board (Caminate), and the like, and serves as a base for receiving chips. Solder balls 25 for electrical connection outside the substrate are implanted at the bottom of the substrate.

The base of this embodiment can also be used for a multilayer substrate 411. As shown in FIG. 4, first, a substrate 4111 of the first layer is laid on the lowest layer, and
Stack 112. A through-hole for attaching the parent chip 42 is left in the second layer substrate 4112 in advance. Next, the uppermost substrate 4113 is laid. In this substrate 4113, a through hole is formed in the same place. Each substrate 4111, 4
112 and 4113 exhibit a class-shaped cross section. The parent chip 42 is attached to the lowest layer, and a filling 44 is applied between the upper side of the parent chip 42 and the substrate 411.
The child chip 42 is attached to the upper layer of the parent chip by flip chip technology, and the child chip 43 is
31 is attached to the second layer substrate 4112. Lowest layer substrate 4111, parent chip 42, child chip 4
The height of the package composed of No. 3 and the thickness of the substrate composed of the three layers are not higher than the height of the tin ball. Planted.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a conventional circuit package.

FIG. 2 is a cross-sectional view illustrating a circuit package according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a circuit package according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a circuit package according to an embodiment of the present invention.

[Explanation of symbols]

 22 Parent chip 23 Child chip 25 Tin ball for electrical connection 31 Base 42 Parent chip 43 Child chip 44 Filling paste 45 Tin ball 211 Conductive band 311 Substrate 411 Multilayer type substrate 431 Projection 4111 First layer substrate 4112 Second layer substrate 4113 Third layer Layer substrate

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Chiang Hua Wen, No.3, No. 57, Changfu Street, Sanmin District, Kaohsiung City, Taiwan ▲ Yo ▼ Fengchang 367-9, Zhongzheng Road, Torimatsu-go, Kaohsiung, Taiwan No. 35, Zhongshan 2nd Road 55, District 72 (72) Inventor 5

Claims (4)

[Claims] 1. A base, a parent chip and a child chip, wherein the base is a base on which the parent chip and the child chip are mounted, and the parent chip is provided on the base by a flat packaging method of surface bonding. The child chip on which the projection is formed is adhered on the parent chip and across the base by a flip chip method, and the base, the parent chip, and the child chip are stacked and packaged. A circuit package comprising: 2. The circuit package according to claim 1, wherein said base is formed by a conductive wire frame. 3. The circuit package according to claim 1, wherein said base is formed by a substrate of a laminated circuit board. 4. The base according to claim 1, wherein the base is composed of a multi-layer combination substrate, and has a bottom layer substrate and a second layer formed on the bottom layer substrate and having a through hole for attaching the parent chip. A substrate, having a top hole substrate formed on the second layer substrate and having a through hole formed at a position corresponding to the through hole of the second layer substrate, the bottom layer substrate; The substrate of the second layer and the substrate of the uppermost layer are laminated stepwise, the parent chip is attached to the substrate of the bottom layer, the child chip is attached above the parent chip by flip chip technology, 2. The circuit package according to claim 1, wherein the child chip is attached to the second layer substrate by the protrusion.