JP2002109890A - Non-volatile semiconductor memory - Google Patents

Abstract

(57) [Problem] To provide a nonvolatile semiconductor memory capable of suppressing variation in write determination due to an increase in a source potential of a nonvolatile memory cell and narrowing a threshold distribution after data write. It is in. SOLUTION: A plurality of memory cells including MOSFETs storing data by changing a threshold value are provided,
The drains of the memory cells are connected to the corresponding bit lines, respectively, while the sources of the plurality of memory cells are connected to a common common source line. In a non-volatile semiconductor memory that repeatedly performs a write determination using a gate as a determination voltage, when the above-described write operation and the write determination are repeatedly performed, from the first write determination to the last write determination, the write operation is performed according to the potential rise of the common source line. Thus, the determination voltage (Vwvmax to Vwvmin) is changed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique which is useful when applied to a nonvolatile semiconductor memory having a nonvolatile storage element for storing data at a high or low threshold value. The present invention relates to a technique for narrowing the distribution of thresholds at the time of data writing in a possible flash memory and a technique for increasing the writing speed.

[0002]

2. Description of the Related Art As shown in FIG. 12, a flash memory has a nonvolatile memory element formed of a MOSFET having a double-layer gate structure having a control gate CG and a floating gate FG as a memory cell MC. A cell is configured.

As a method of writing data to such a memory cell MC, for example, a high voltage (for example, 18 V) write voltage Vww is applied to the control gate CG with the source and the drain kept at 0 V as shown in FIG. Negative charge is injected into the floating gate FG by the FN tunnel phenomenon to
There is a method of increasing the threshold voltage or a method of increasing the threshold value by injecting hot electrons generated by flowing a current between the source and the drain with a high voltage applied to the gate into the floating gate.

In either method, when writing data, as shown in the data write processing flow of FIG. 13A, a write operation for applying a write voltage Vww to the control gate CG and a write operation for a memory cell are performed. The verify reading and the determining operation for determining whether the threshold value has reached the predetermined voltage are repeatedly performed, and as shown by hatching in FIG. 13B showing the threshold distribution of the memory cell, When the threshold value Vth does not exceed, for example, a verify voltage Vwv (for example, 2 to 3 V) corresponding to logic “1”, the write is not completed “fail”, and the verify voltage Vwv
Is exceeded, it is determined that the writing is completed “pass”.

For erasing data, for example, -12 V is applied to the control gate and 4 V is applied to the drain (the source is open) to extract charges from the floating gate to the drain side, and an erase verify voltage Vev. (For example, 1 V), and is performed by repeatedly performing the verify read and the determination operation as in the case of the data write. Thereby, the threshold value of the memory cell is distributed to the threshold value corresponding to logic "0". In erasing, if the threshold value is too low, a current flows even at the non-selection level of the word line. Therefore, the threshold value is set using the write verify voltage Vwv (for example, 1 V) corresponding to logic "0". Data writing (writing back) is performed to make the data slightly higher.

An example of a memory array of a flash memory and
As a result, as shown in FIG.
Each of a plurality of memory cells MC,
A plurality of memory cell columns MCC are arranged in the word line direction.
There is a so-called AND type. Such a method
In the memory array configuration, the memory cell row MCC
The rain side corresponds via the selection MOSFET Qs1 ...
Connected to the bit lines D1 to D8448
Side is a common source line via the selection MOSFET Qs2
Connected to CSL. Furthermore, the common source line CSL
Is the switch SW _SCan be connected to the ground via
You. On the other hand, each memory cell MC in the memory cell column MCC ...
Control gates are connected to corresponding word lines W1 to W128.
Connected respectively. In such a memory array configuration
Therefore, data writing can be performed for a plurality of data connected to one word line.
Is performed in units of sectors composed of the memory cells MC. Erase
Are multiple cells with a common well (or drain)
This is done in block units consisting of

FIG. 15 shows a flow of a current at the time of write verify read in the memory array having the configuration as shown in FIG. 14, and FIG. 16 shows a sector S for performing the write verify operation.
Memory cell MCa corresponding to data "1" in EC
Is a time chart of voltage waveforms VDa and VDb after precharging of bit lines D1 and D2 respectively connected to the memory cell MCb corresponding to data "0", and a discharge signal ST2 for turning on / off the selection MOSFET Qs2. Show.

In the above-described memory array configuration, first, the bit line is precharged to a predetermined voltage (for example, 1 V), then a verify voltage Vwv is applied to the corresponding word line W1, and the drain side is selected. MOSF
After turning on ET Qs1, select MOSF on the source side
This is performed by turning on (discharging) ET Qs2.

As shown in FIGS. 15 and 16, in the memory cell MCb in which writing has not been completed, the source-drain state is turned on by the verify voltage Vwv, and the bit line D2 is connected to the common source line CSL. While a current flows to lower the potential VDa (FIG. 16) of the bit line D2, in the memory cell MCa in which writing has been completed, the source-drain state remains off and the bit line D1
, Almost no current flows to the common source line CSL, and the potential VDb (FIG. 16) of the bit line D1 hardly changes. Then, the potentials VDa and VDb of the bit lines are received by the sense amplifier and compared with the precharge level (0.5 V) of the bit line of the memory array on the opposite side. Level "H"
If "high", it is determined that writing has been completed. Such a writing determination is performed for each memory cell to which data is to be written.
Are repeated until the writing is completed, or until the predetermined number of times is reached. Note that the write operation is not performed from the next time on the memory cell once determined to be completely written.

By the way, the threshold value Vth of the memory cell
Is the logarithm l of the cumulative time T during which the write voltage Vww is applied to the control gate, as shown in FIG.
It is known that it changes with a linear function of og (T).
Therefore, in the conventional flash memory, t0, t0 in FIG.
As shown by t1,..., the time of each write operation is set so that the variation amount ΔVth of the threshold value Vth in one write operation is constant. Thus, the distribution width of the threshold value Vth of the plurality of memory cells MC in which data of the same logical value (for example, “1”) is written becomes the variation Δ
It was thought to fit within Vth.

Because, as shown in FIG. 18 showing a change in the threshold value of two memory cells in a plurality of write operations, among the memory cells MC determined to have been completely written, the threshold value Vth is the largest. As shown by the black dot A in FIG. 18, the threshold value Vth changes so that the threshold value Vth slightly exceeds the verify voltage Vwv in the (n) th write operation, and in this case, the threshold is reached. Value Vth
Has substantially the same value as the verify voltage Vwv. On the other hand, the one having the highest threshold value Vth changes so that the threshold value Vth is slightly lower than the verify voltage Vwv by the (n) th write operation as shown by the white point b in FIG. In this case, the next write operation (n +
In the first time), the threshold value Vth increases the variation amount ΔVth for one time and it is determined that the writing is completed.
Is approximately the verify voltage Vwv and the variation ΔV of the write operation.
and (Vwv + ΔVth). From these facts, the distribution width of the threshold Vth is ΔVwv ~
(Vwv + ΔVth)}, which is considered to be within the variation amount ΔVth of the threshold value for one write operation.

[0012]

However, in the above-described write determination, the distribution width of the threshold value Vth does not fall within the variation ΔVth for one write operation due to the following several factors. It became clear. In other words, as shown in FIG. 19A, at the beginning of data writing, most of the selected memory cells MC... Have not been completely written, so that the current flowing through the common source line CSL increases. Since most of the selected memory cells MC have been written before the end of the data writing, the current flowing through the common source line CSL becomes small.

As a result, at the initial stage of data writing, the source potential of the selected memory cells MC greatly increases due to a voltage drop due to the parasitic resistance Rs of the common source line CSL. The voltage is reduced, and even the memory cells MC having a threshold lower than the determination potential Vwv are turned off. That is, FIG.
As shown in (a) of FIG. 0, in the initial stage of data writing, even in the memory cells MC... In which the threshold value Vth has not reached the verify voltage Vwv, it is determined that the writing is completed (“pass”). On the other hand, as shown in FIG. 20B, only the memory cells MC whose threshold value Vth has actually reached the verify voltage Vwv before the end of data writing are determined to be writing-completed. As a result, once the memory cell determined to be completely written is stored, the distribution of the threshold Vth after data writing varies to a lower level than the verify voltage Vwv, as shown in FIG. I will.

When the source potential of the memory cell MC rises by 0.2 to 0.3 V as shown in FIG. 21 due to the voltage drop of the common source line CSL, current hardly flows from the drain to the source. As shown in VDi,
The waveform VDi when the source potential is high is smaller than the waveform VDf when the source potential is low.
There is also a phenomenon that the potential of the bit line connected to the bit line hardly decreases. In such a case, the control gate C of the memory cell
When the verify voltage Vww close to the threshold value Vth is applied to G and the memory cell is turned on, the potential of the bit line is slowed down and the off state is determined, that is, the write is completed. As a result, the data write is completed. The distribution of the threshold value Vth after the end of the processing varies to the lower side.

The phenomenon that the current flowing to the common source line increases as described above often occurs at the initial stage of programming when there are many uncompleted memory cells, but decreases before the completion of programming when the number of completed memory cells increases. Since the amount of current also changes from the initial stage to the end of programming, it is difficult to make a correct verify determination.

An object of the present invention is to provide a non-volatile semiconductor memory capable of suppressing variation in write determination due to an increase in source potential and narrowing a threshold distribution after data write.

Another object of the present invention is to provide a nonvolatile semiconductor memory capable of improving a writing speed without expanding a distribution of threshold values.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0019]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, a memory array in which a plurality of memory cells each composed of a MOSFET for storing data according to the level of a threshold value is provided in a matrix, and the control gates of the memory cells in the same row are connected to corresponding word lines. Connected, the drains of the memory cells in the same column are connected to the corresponding bit lines, respectively, and the source is made connectable to the common source line. When writing data (including when writing back when erasing data) And a write operation of applying a write voltage to any one of the word lines, and applying a verify voltage to the word line after precharging the bit line and then applying a verify voltage between the bit line and the common source line via the selected memory cell. A write decision operation for detecting a change in the potential of a bit line based on a current flowing to Is repeated a plurality of times in the nonvolatile semiconductor memory, the verify voltage, the conduction time length (for example, discharge time) in which a current flows between the bit line and the common source line, or the resistance value of the common source line is determined for each determination operation. Configure to be changed.

According to such means, at the time of the write verify determination, the source potential of the memory cell rises due to the current flowing through the common source line, and the rise amount gradually increases from the first determination operation to the last determination operation. Even if it changes, the write voltage based on the rise of the source potential is changed by changing the verify voltage in accordance with the change, or by changing the length of time for supplying a current between the bit line and the common source line. Variation in the threshold value determined to be completed can be suppressed. That is, if the verify voltage is increased by the rise of the source potential, a desired threshold value can be determined. Even if the source potential rises and it becomes difficult to draw current from the bit line, the bit line is If the current supply time between the common source lines is long, the threshold value can be determined in the same manner as when the source potential does not increase.

If the resistance value of the common source line changes so that the current flowing through the common source line changes from the first write judgment to the last write judgment, the common source line changes in accordance with the change. When the resistance of the line changes, the change in the amount of increase in the source potential can be suppressed. Therefore, variation in threshold value due to an increase in source potential can be suppressed.

Therefore, the threshold distribution of the memory cell after data writing can be narrowed, and the threshold distribution of the memory cell after writing is completed can be within a narrow range. The reliability of writing can be improved.

More specifically, in the above-mentioned write determination, when the potential of the bit line does not change by a predetermined amount or more, it is determined that the write is completed, and the threshold value is lowered by data erasure to become logic "0". In a flash memory in which the threshold value is increased by data writing and becomes logical "1", the verify voltage is gradually lowered, the conduction time length is gradually shortened, and the resistance value of the common source line is gradually decreased every time a determination operation is performed. It is good to be configured to be large.

On the other hand, in the case of a write determination in which the write is determined to be completed when the potential of the bit line changes by a predetermined amount or more (the threshold value rises by data erasure and becomes logic "1", and the threshold value becomes In the case of a flash memory which becomes a logic "0" when the voltage is lowered, the verify voltage is gradually increased, the conduction time is gradually increased, and the resistance value of the common source line is gradually increased from the first write determination to the last write determination. Is preferably configured to become gradually smaller.

For example, when writing the same logical value to all bits in a sector (for example, at the time of writing back in an erasing process), a change in the current flowing through the common source line is predicted to some extent according to the number of times of writing determination. Therefore, based on the prediction, the verify voltage, the conduction time length, or the resistance value of the common source line may be set to change by a predetermined amount.

According to such a configuration, for example, even if the current flowing through the common source line from the start to the end of the data write cannot be predicted by random data write, the above-described operation is performed according to the potential of the common source line. The verify voltage, the length of the conduction time, or the resistance of the common source line can be changed as appropriate.

More specifically, a monitoring means for monitoring the potential of the common source line is provided. Based on an output from the monitoring means, the verify voltage and the energization time length are changed in a stepwise manner. Can be configured by an inverter circuit that receives the potential of the common source line as an input.

The total application time of the write voltage to the selected word line until the end of each of the (m-1) -th (m is a positive integer), the m-th, and the (m + 1) -th write operation is represented by _{Tm. -1} , _Tm , _{Tm + 1} , log (T
_{m + 1} ) -log ( _Tm ) <log ( _Tm ) -log
The write operation is performed so as to satisfy the relationship of (T _m−1 ).

According to such means, the number of write operations and the number of write determinations until all the memory cells to be written are completely written without expanding the threshold distribution of the memory cells after data write. Can be reduced. Therefore, it is possible to reduce the overall time for writing data.

Because log (T_{m + 1}) -Log
(T_m) = Log (T_m) -Log (T_m-1)As
In the conventional writing method where the writing operation is
As described above, the source potential rises at the initial write decision
Occurs, and the threshold voltage Vth of the memory cell is
Even if the voltage is slightly lower than the voltage Vwv (Vwv-δ).
Threshold, which determines that writing is incomplete
Is the highest threshold value Vth of the voltage (Vwv-δ).
It will be slightly lower. Therefore, as shown in FIG.
As described above, in the next write operation, the amount of change in the threshold
In any case, if the threshold value is (Vwv + ΔVth (ideal
Distribution width)). In other words, the next write operation
The threshold variation is calculated using the ideal threshold distribution width ΔV
The variation amount δ due to an increase in the source potential was added to th.
Value (ΔVth + δ), in which case
However, the threshold of the memory cell is ideal threshold distribution
The higher voltage (Vwv-Vwv + ΔVth) (Vwv
+ ΔVth). Therefore, data writing
The initial write operation time and the threshold distribution
Δ of variation of threshold value (ΔVth + δ) without widening
It is only possible to extend. That is, the above relational expression l
og (T_{m + 1}) -Log (T_m) <Log (T _m)-
log (T_m-1)
Instead of extending the initial write operation time,
The number of operations and write decisions, and as a result,
The total required writing time can be reduced.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described below with reference to FIGS.

[First Embodiment] FIG. 1 is an overall block diagram of a flash memory according to a preferred embodiment of the present invention.

In FIG. 1, reference numeral 11 denotes a memory array having memory cells as nonvolatile memory elements each composed of a MOSFET having a floating gate and a control gate and arranged in a matrix, and having an AND type configuration as shown in FIG.
Is an input register for holding write data input from the outside, and 13 is a write circuit for writing data to the memory array 11 based on the data held in the data input register 12.

The memory array 11 decodes a row address signal fetched from an address bus.
Row address decoder for selecting one of the word lines
5 is a write voltage Vww at the time of a write operation to one word line selected from the word lines W1 to W128 in the memory array 11 based on the output of the row address decoder 14.
Verify voltage Vwv at the time of write determination, and erase voltage Ve or erase verify voltage Vev at the time of erase or erase determination.
, A word decoder 16 for selecting a 1-byte (or 1-word) bit line in the memory array 11, and a sense 17 for amplifying and outputting data read by the memory cell array 11. An amplifier 18 is an output register for holding the amplified read data.

Further, in addition to the above-described circuit blocks, the flash memory of this embodiment includes control signals such as an external clock signal CK, a read / write signal R / W, a chip select signal MS, and an operation mode control signal MOD. And a control circuit 20 for generating a control signal to each circuit of the flash memory based on the voltage Vcc, a write voltage Vww, an erase voltage Ve, Read voltage V
r, an internal power supply circuit that generates voltages such as a write verify voltage Vwv and an erase verify voltage Vev, and a power supply switching circuit that selects a desired voltage from these voltages according to the operation state of the memory and supplies the selected voltage to the word driver 15 And a power supply & switching circuit 25 including the above.

The control circuit 20 has a ROM in which control codes (micro-instructions) necessary for controlling the flash memory are stored, and controls each circuit in the flash memory according to a control signal from the outside and a control code in the ROM. The control signal is sequentially formed and output, and operations such as writing, writing determination, erasing, erasing determination, and reading are performed.

In the flash memory of this embodiment, in the write operation, 0 V is applied to the source / drain of the memory cell corresponding to data "1", and a voltage such as 5 V is applied to the drain of the memory cell corresponding to data "0". It is applied to prevent writing. In the write determination, a verify operation is performed, the bit that has been written once is stored, and in the generation of rewrite data, the bit that has not been written is set to data “1”, while the bit that has been written is data “1”. 0 ".

The generation of such rewrite data is configured so that the CPU receiving the read data performs the software processing. In this embodiment, a means for monitoring the potential of the common source line is provided in the memory array 11, and a monitoring signal S1 from this monitoring means is supplied to the control circuit 20.
And the potential monitor signal S1
The content of the operation is changed at the time of writing determination based on.

FIG. 2 is a circuit diagram showing the configuration of a memory array of a flash memory and a circuit for monitoring the potential of a common source line.

The configuration of the memory array of the flash memory of this embodiment is not particularly limited.
A plurality of AND-type memory cell columns MCC each including a plurality of memory cells MC each having a common drain and source are arranged in the word line direction. The drain side of each memory cell column MCC is coupled to corresponding bit lines D1 to D8448 via selection MOSFETs Qs1,..., While the source side is connected to common source line CSL via selection MOSFET Qs2. Further, the control gates of the respective memory cells MC in the memory cell column MCC are coupled to corresponding word lines W1 to W128, respectively.
In such a memory array configuration, writing and erasing of data are performed in units of sectors composed of a plurality of memory cells MC connected to one word line.

The common source line CSL is connected to an inverter circuit INV 1 (potential monitoring circuit) for monitoring a rise in the potential of the common source line CSL, and outputs a potential monitoring signal S 1 as an output to the control circuit 20. It is provided to be. This inverter circuit INV1 is a CMOS inverter circuit in which a P-channel MOSFET and an N-channel MOSFET are connected in series, and has a high input impedance without affecting the potential of the common source line CSL. Can be monitored. The logical threshold value Vth of the inverter circuit INV1 is a critical level (for example, 0. 1) at which a rise in the potential of the common source line CSL prevents reading of correct data.
2 V to 0.3 V). By providing a plurality of such inverter circuits with different logic thresholds Vth, the potential of the common source line CSL can be finely divided into a plurality of stages.

FIG. 3 is a diagram for explaining a write determination method according to the first embodiment for suppressing variation in write determination due to a rise in the potential of the common source line. In the figure, the horizontal axis represents the time at the time of the write decision from the start to the end of the write processing, the upper part of the vertical axis shows the verify voltage applied to the selected word line in the write decision, and the lower part of the vertical axis. Indicates a shift amount of the memory cell determined to be completed in the write determination toward the lower side of the threshold distribution. Regarding the deviation amount of the threshold distribution, the dotted line shows the conventional one and the solid line shows the one of the writing method of this embodiment.

In the flash memory of this embodiment, as means for suppressing the variation of the write judgment based on the rise in the potential of the common source line CSL, the verify applied to the selected word line when the potential of the common source line CSL is rising. A method is used in which the voltage Vwv is set higher than an ideal verify voltage Vwv0 that does not cause the potential of the common source line CSL to rise. And the common source line CS
When the rise in the potential of L decreases, the voltage is gradually lowered by a predetermined voltage ΔVwv.

When data writing is performed using such a method, as shown in FIG. 3, first, at the start of data writing, a large number of uncompleted memory cells are present, and the current flowing in the common source line at the time of writing determination is determined. Becomes larger, the highest verify voltage Vwvmax is used as the verify voltage in the first write determination.

The flash memory of this embodiment is
The threshold value of each memory cell is logic "0" due to data erasure.
Is set to a low value (for example, 1 V) corresponding to the logic "1", and is set to a high value (for example, 2 V) corresponding to the logic "1" by writing data. Therefore, even in the case of an arbitrary write in which a logical "1" is written only to an arbitrary bit in a sector, instead of an all-bit write, at the time of write determination, a memory cell of a non-written bit in the same sector is turned on and the current is reduced. Therefore, a large current flows to the common source line CLS at the beginning of data writing.

Then, as the number of memory cells that have been determined to be written by performing the write operation and the write determination increases, the current flowing through the common source line CSL decreases, and the rise in the potential of the common source line CSL decreases. When the potential of the common source line CSL is reduced by a predetermined amount during the write determination (n times in FIG. 3), the output of the inverter circuit INV1 is inverted from a low level to a high level, and the potential monitor signal S1 Is output to the control circuit 20.
Thereby, the control circuit 20 detects that the potential of the common source line CLS has dropped by a predetermined voltage.

Then, a control signal is output from the control circuit 20 to the power supply & switching circuit 25, and the verify voltage Vwv applied to the selected word line is lowered by a predetermined voltage ΔVwv. Then, as the verify voltage Vwv decreases, the number of the selected memory cells that are turned on increases, and the output of the inverter circuit INV1 is again inverted from the low level to the high level.

When the control circuit 20 determines again that the potential rise of the common source line CSL is reduced by a predetermined amount and is detected by the control circuit 20 by the output of the inverter INV1 at the time of the write determination (m times in FIG. 3). Under the control of the circuit 20, the verify voltage Vwv is reduced by a predetermined voltage ΔVwv. Then, such processing is repeated, and it is finally determined that writing has been completed for all the write bits in the selected sector, and the data writing processing ends.

In the above-described correction method, the initial verify voltage Vwvmax is applied to all bits in the sector by logic "
Assuming that data of 1 ″ is to be written, a verify voltage Vwvmin when all bits are determined to have been written is completed.
Is set so as to be the ideal verify voltage Vwv0 where the potential of the common source line CSL does not rise. Thus, the threshold distribution of the memory cell after the end of writing can be made closer to an ideal distribution when there is no rise in the potential of the common source.

In the above-described write determination method, for example, a plurality of inverters having different logic thresholds are provided as a potential monitoring circuit so that the potential of the common source line CSL can be detected in a plurality of stages, so that the common source It is also possible to adopt a configuration in which the verify voltage is easily lowered stepwise as the potential of the line CSL changes stepwise.

In the write determination of this embodiment, the verify voltage Vwv is constant until the potential of the common source line drops by a predetermined amount. Act as variations. However, as can be seen by comparing the “before countermeasure” line and the “after countermeasure” line in FIG. 3, the amount of deviation is smaller by the change in the verify voltage Vwv. Also, as shown in FIG. 3, the maximum value of the deviation amount is the verify voltage V
Since wv is almost the same as the variation ΔVwv for one time,
If the amount of variation ΔVwv for one time is made small, the amount of deviation of the threshold distribution of the memory cell can also be made small. However, in order to reduce the amount of variation ΔVwv for one cycle, it is necessary to further reduce the resolution of the potential monitoring of the common source line CSL, and accordingly, the number of potential monitoring circuits increases and the chip area increases. The variation amount ΔVwv may be determined in consideration of both.

FIG. 5 shows a change in the threshold distribution of a memory cell when data of logic "1" is written to all bits in a sector using the write determination method of the first embodiment. FIG.

According to the above-described write determination method, FIG.
As shown in (a), in the initial stage of data writing in which the rise in the potential of the common source line CSL is large, the write determination shift due to the rise in the potential of the common source line CSL is performed by the verify voltage Vwvmax set higher accordingly. Is reduced.

As the writing process proceeds as described above and the rise in the potential of the common source line CSL decreases, the verify voltage Vwv is accordingly increased by a predetermined amount ΔVw.
It is gradually lowered by v.

Thereafter, for example, in a case where data of logic "1" is written to all bits in the sector, FIG.
As shown in (b), most of the memory cells have completed writing before the end of the data writing process, so that the current flowing through the common source line CSL approaches “0”. Correspondingly, the verify voltage Vwvmin also becomes the ideal verify voltage Vwv0 (verify voltage when there is no potential rise of the common source line CSL), and the final write operation and write determination are completed. .

On the other hand, for example, when random data (for example, “1, 0, 1, 0, 1, 0...”) Is written in a sector, in a memory cell whose write data is a logical “0”, A current always flows through the common source line CSL without being turned off at the time of verify reading. Therefore, in the case of writing random data, the current flowing through the common source line CSL does not approach “0” even before the end of the data writing process. Then, the write operation and the write determination are completed before the verify voltage Vwv also decreases to the ideal verify voltage Vwv0.

As a result, as shown in FIG.
The threshold distribution of the memory cell after the end of the writing process includes a slightly lower potential than the ideal threshold distribution which is not affected by the rise of the source potential shown by the dotted line in FIG. An extended threshold distribution is obtained. As described above, while the potential of the common source line continuously changes, the portion slightly spread to the lower side corresponds to the verify voltage Vwv.
Is caused by only changing stepwise, but it can be seen that it is considerably improved as compared with the conventional case (FIG. 20).

FIG. 5 shows an example in which the verify voltage Vwv is further finely changed in accordance with the potential of the common source line in the write determination method of the first embodiment. In the figure, the horizontal axis represents the time of the write decision from the start to the end of the write process, the upper part of the vertical axis shows the verify voltage applied to the selected word line in the write decision, and the lower part of the vertical axis shows the write decision. Indicates the amount of shift of the threshold voltage distribution of the memory cell judged to be completed to the lower side. Regarding the variation amount of the threshold distribution, the dotted line is the conventional one and the solid line is the writing method of this embodiment.

If the potential of the common source line is monitored at a finer stage, and if the verify voltage Vwv is further finely changed based on the monitoring, as shown in FIG. 5C, the lower limit is the ideal verify voltage Vwv and the upper limit is the threshold variation ΔVth of one write operation as shown by the dotted line in FIG. The threshold values of all the written memory cells fall within the high ideal threshold distribution.

[Second Embodiment] FIG. 6 shows a second embodiment of the present invention which suppresses the variation of the write judgment due to the rise in the potential of the common source line.
The write determination method of the embodiment of FIG.
7A is a waveform diagram at the initial stage of data writing of the bit line potential VD and the discharge signal ST2, FIG. 7B is a waveform diagram at the middle stage of data writing, and FIG. 7C is a waveform diagram before the end of data writing.

As shown in FIGS. 6A to 6C, at the stage before the end of the writing in which the potential rise of the common source line CSL is small, a current quickly flows from the drain side to the source side of the memory cell MC. In the initial stage of writing, while the potential VD of the bit line rapidly decreases, the potential of the common source line CSL is large, and in the initial stage of writing, it becomes difficult to draw current from the drain side to the source side of the memory cell MC, and the potential of the bit line decreases It takes time. Therefore, the memory cell M
If the potential of the bit line does not drop below the reference voltage (for example, 0.5 V) due to a delay in the potential drop of the bit line at the start timing of the sense amplifier at which ON or OFF of C is determined, the sense amplifier goes high. Since the signal is amplified and latched as a level signal, even if the threshold value of the memory cell MC is not completely turned off and writing is not completed,
The completion of writing is determined by the above verify voltage.

In the write determination method of the second embodiment, in order to suppress the above-described variation in the write determination, FIG.
As shown in (a) to (c), when the potential of the common source line CSL is rising by changing the pulse width of the discharge signal ST2, a discharge time for drawing a current from the drain side to the source side of the memory cell MC. Is set longer than usual, and the discharge time is reduced stepwise when the potential of the common source line CSL decreases. Adjustment of the discharge time is performed by making the off-timing of the source-side selection MOSFET QS2 stepwise by a sequence process of the control circuit 20 based on the output of the inverter INV1 which is a potential monitoring circuit of the common source line CSL. In this example,
As means for monitoring the potential of the common source line CSL, the same means as that shown in the first embodiment can be used.

FIG. 7 is a diagram showing a shift amount of a memory cell, which is determined to be write-completed, along the time of the write determination to a lower threshold value in the write determination method of the second embodiment. . In the figure, the horizontal axis represents the time at the time of writing determination from the start to the end of data writing, and the vertical axis represents the amount of deviation of the threshold value for writing determination toward the lower side.

As shown in FIG. 6A, in the write decision of this embodiment, the discharge time is made the longest at the time of the first write decision. When the potential of the common source line CSL drops to a predetermined voltage and the output of the potential monitoring inverter INV1 changes from a low level to a high level, the discharge time is increased by a predetermined time as shown in FIGS. Is controlled to be shorter.

The time difference between the longest discharge time at the first time of the write determination and the shortest discharge time when the potential of the common source line CSL is lowered is determined when data of logic "1" is written to all bits in the sector. It is preferable that the discharge time when it is finally determined that all the bits have been written be set to an ideal discharge time when there is no influence of the common source line CSL. Thus, the threshold distribution of the memory cell after the end of writing can be made closer to an ideal distribution when there is no rise in the potential of the common source.

When the discharge time is extended,
To that extent, the time for write determination is increased, and the total time required for data write is cumulatively increased. Therefore, the longest first discharge time may be determined in consideration of a balance between the permissible amount of variation in write determination and the total time of data writing.

In the write judgment of this embodiment, since the discharge time does not change continuously but changes stepwise, the change in the potential of the common source line CSL during the time when the discharge time does not change is the last change of the memory cell. It acts as a shift to the lower one of the typical threshold distribution. However, as can be seen by comparing the dotted line “before countermeasures” and the solid line “after countermeasures” in FIG. 7, the amount of deviation is smaller by the extension of the discharge time. Also, the common source line CS
If the change in the potential of L is monitored more closely and the amount of change in one discharge time is reduced accordingly, the amount of variation in the threshold voltage distribution of the memory cell toward the lower side can be reduced. However, in order to further reduce the resolution for monitoring the potential of the common source line CSL, the number of circuits for monitoring the potential is increased and the chip area is increased. Therefore, the amount of change in the discharge time may be determined in consideration of both.

FIG. 8 shows a change in the threshold distribution of a memory cell when data of logic "1" is written to all bits in a sector using the write determination method of the second embodiment. FIG.

According to the write determination method of the second embodiment,
As shown in FIG. 8A, at the initial stage of data writing when the rise of the potential of the common source line CSL is large, the threshold voltage Vth is completely lower than the verify voltage Vwv due to the rise of the potential of the common source line CSL. A predetermined current is drawn from the drain side to the source side due to the long set discharge time for the memory cell MC that does not change to the ON state (writing is not completed).

As the writing process progresses and the rise in the potential of the common source line CSL decreases, the discharge time is shortened by a predetermined time.

Thereafter, for example, when the same data is written in all the bits in the sector, as shown in FIG. 8B, before the end of the data writing process, the potential rise of the common source line CSL is " 0 ”and correspondingly,
The discharge time becomes an ideal discharge time (which can be accurately determined when there is no rise in the potential of the common source line CSL and is the minimum discharge time), and the final write operation and write determination are completed.

As a result, as shown in FIG. 8C, the threshold distribution of the memory cell after the end of the writing process is ideally free from the influence of the rise of the source potential shown by the dotted line in FIG. Thus, a threshold distribution spread to include a slightly lower potential is obtained. As described above, this slightly lower portion is caused by the fact that the discharge time is changed only stepwise while the potential of the common source line is continuously changed. It can be seen that it is considerably improved as compared to FIG.

[Third Embodiment] FIG. 9 is a circuit diagram showing a memory array according to a third embodiment provided with a correction circuit for keeping the potential of the common source line constant.

In the flash memory according to the third embodiment, a depletion type MOSFET is provided as a variable resistor between the common source line CSL of the memory array and the ground potential.
The drain-source of Qr is connected, and the gate is connected to a common source line CSL.

According to such a configuration, even when many memory cells MC are turned on in the initial write determination and a large amount of current flows through common source line CSL, the potential of common source line CSL is reduced due to the voltage drop. When it is about to increase, the gate voltage of the depletion-mode MOSFET Qr increases, and the resistance value between the drain and source of the MOSFET decreases. Therefore, the common source line CSL
Is suppressed.

On the other hand, when almost all the memory cells MC are turned off in the write determination near the end of data write and a small amount of current flows through the common source line CSL, the potential of the common source line CSL tends to rise. As the gate voltage of the depletion-mode MOSFET Qr decreases, the resistance between the drain and source of the MOSFET Qr increases, and the amount of voltage drop due to the common source line CSL increases during the write determination from the beginning to the end of data writing. Is kept almost constant.

Therefore, by designing the verify voltage and the discharge time in accordance with the voltage drop of the common source line CSL kept constant, the variation in the write decision is suppressed and the desired threshold value of the memory cell is reduced. Value distribution can be obtained.

In the flash memory of this embodiment, the circuit (inverter INV1) for monitoring the potential of the common source line CSL shown in FIG.
Since the potential monitoring signal S1 (FIG. 1) of the common source line CSL input from the control circuit 20 to the control circuit 20 becomes unnecessary, the chip area can be reduced as compared with the flash memories of the first and second embodiments. . Also, there is no need to change the control content of the control circuit 20.

It should be noted that instead of the depletion type MOSFET acting as a variable resistor, an enhancement type M
OSFET is used and the common source line CS is connected to its gate.
It is also possible to apply a voltage obtained by adding an appropriate offset voltage to the potential of L.

[Fourth Embodiment] FIG. 10 is a graph showing a relationship between a bias application time of a write operation and a threshold value Vth of a memory cell in a flash memory according to a fourth embodiment.

In the flash memory according to the fourth embodiment, the threshold voltage Vth of the memory cell determined to be completed in the initial write determination of the data write is reduced by the displacement δ due to the rise in the potential of the common source line CSL. Utilizing the shift to the lower side, the time of the initial write operation of the data write (the write voltage Vw is applied to the gates of the memory cells MC...).
The time for applying w) is set to be longer than an ideal write operation time when there is no rise in the potential of the common source line CSL at the time of write determination.

As shown in FIG. 10, the threshold voltage Vth of the memory cell MC of the flash memory is set such that the write voltage Vw is applied to the control gate of the memory cell MC from the initial stage before writing.
It is known that it becomes a linear function of the logarithm (logT) of the total time T to which w is applied. Therefore, conventionally, as described in the related art, the time of each write operation is set so that the variation amount ΔVth of the threshold value Vth of the memory cell MC is constant in all write operations (FIG. 17). reference).

On the other hand, in the flash memory of this embodiment, the total application time of the write voltage to the selected word line until the end of each of the (m−1) -th, m-th, and (m + 1) -th write operations To T _m−1 , T _m , T
when the _{m + 1, log (T m} + 1) -log (T m) <log (T m) -log (T m-1) ···· ( Equation 1) each time so as to satisfy the relation of the write operation time Is set.

More specifically, the variation amount of the threshold value Vth obtained by the m-th write operation time is ΔVm, and the lower the determination threshold value Vth based on the potential rise of the common source line CSL at the time of the m-th write determination. Δm,
Assuming that the variation amount of the threshold value due to the ideal write operation time without increasing the potential of the common source line CSL is ΔVth, the m-th write operation time (T _m −T _m−1 )
Is preferably set so that the variation amount ΔVm of the threshold value obtained thereby becomes as close as possible to the relationship of ΔVm = ΔVth + δm (Equation 2). Further, it is preferable that the variation ΔVn of the threshold Vth in the last write operation is set to be the same as the ideal variation ΔVth of the threshold.

In order to set each write operation time as described above, the threshold Vt in each write determination is set in advance.
Since it is necessary to know the shift amount δm of h, for example,
This is applicable to the case where the same data is written to all bits in a sector, such as at the time of writing back in an erasing process.

FIG. 11 is a diagram for explaining the distribution width of the threshold value Vth of a memory cell which is determined to be completely written in data writing according to the fourth embodiment.

By setting the write time as described above, the lowest one of the threshold values Vth of the memory cells determined to be write-completed in the m-th to (m + 1) -th write determinations is as shown in FIG. As shown by a black dot A in the figure, a voltage (Vwv-V) that is lower than the verify voltage Vwv by a variation amount δm due to a potential rise of the common source line CSL.
δm). On the other hand, as shown by a white dot b in FIG. 11, the highest threshold value is the threshold value of the memory cell MC which is slightly lower than the voltage (Vwv-δm) and is completed in the next write determination. Becomes

The memory cell MC having the highest threshold value Vth has a voltage (V) whose threshold value before the completion of writing is lower than the verify voltage Vwv by a variation amount δm.
wv−δm), the upper limit (Vwv + ΔVt) of the desired threshold distribution in the next write operation.
h), and to maximize the variation of the threshold value Vth, the writing time must be reduced by the common source line C
The variation (ΔVth + δm) obtained by adding the variation δm to the ideal variation ΔVth which is not affected by the potential rise of SL.
Should be set to the time corresponding to Therefore, by the writing process that satisfies the relational expressions of (Expression 1) and (Expression 2),
As long as the threshold value does not exceed the upper limit of the desired threshold distribution, the time for one write operation is the longest. As a result, the number of write operations and write determinations can be reduced, and the total required time for data write can be reduced.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist of the invention. Needless to say.

For example, in the embodiment, the state where the threshold value of the memory cell is low is set to the erased state in correspondence with the data "0".
Although the memory cell whose write data bit corresponds to "1" has exemplified the configuration in which the threshold voltage is increased by writing,
However, the present invention is not limited to this. Conversely, a state where the memory cell threshold voltage is high is set to an erased state corresponding to data “1”, and
The memory cell corresponding to "0" may be configured to lower the threshold voltage by writing. In such a configuration, the write determination is made when the threshold of the memory cell is turned on below the verify voltage. Since the current is determined to be completed, the current flowing through the common source line increases before the end of data writing, and the threshold distribution fluctuates to a lower side. It is preferable that the resistance value of the common source line be increased or the discharge time is gradually increased.

In the first and second embodiments, the voltage of the common source line CSL is monitored, and the verify voltage Vwv and the discharge time are changed based on the rise of the voltage. In the case where the same data is written to all the bits in the sector, such as at the time of write-back in processing, the relationship between the number of writes and the potential rise of the common source line CSL can be predicted in advance. It can be configured to change the verify voltage Vwv, the discharge time, or the resistance of the common source line CSL accordingly. As a result, a circuit for monitoring the potential of the common source line CSL becomes unnecessary, and the chip area can be reduced.

The flash memory for storing binary data in one memory cell has been described.
A threshold distribution separated into four or more ranges is set, and 1
The present invention can be usefully applied to a multi-valued memory or the like in which data of many bits (for example, 4 bits) can be stored in one memory cell.

Further, a two-layer gate type MOSFE having a control gate and a floating gate as nonvolatile memory cells.
T, but MNOS (Metal Nitride Oxide Semi
The present invention is similarly applicable to a nonvolatile semiconductor memory using a memory cell of a type in which data is stored by retaining electrons at the interface between a nitride film and an oxide film by a transistor having a conductor structure.

In the above description, the invention made by the present inventor has been mainly described with respect to the flash memory which is the field of application as the background, but the present invention is not limited to this, and the current is applied from the bit line to the common source line. Can be widely used for a nonvolatile semiconductor memory that makes a write determination by extracting the data.

[0096]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the present invention, even when the amount of current flowing through the common source line at the time of writing determination greatly changes from the initial stage to the end of the data writing, the memory cell is determined based on the current flowing through the common source line. Variations in the threshold distribution can be suppressed, whereby the threshold distribution of the memory cells can be narrowed, and the reliability of the write data is improved.

Further, according to the present invention, there is an effect that the overall time required for data writing can be reduced without expanding the threshold distribution after data writing.

[Brief description of the drawings]

FIG. 1 is an overall block diagram showing a preferred embodiment of a flash memory to which the present invention is applied.

FIG. 2 is a circuit diagram showing a memory array configuration of a flash memory and a circuit for monitoring a potential of a common source line.

FIG. 3 is a diagram illustrating a write determination method according to a first embodiment that suppresses variation in write determination due to a rise in the potential of a common source line.

FIG. 4 is an explanatory diagram of another example of the write determination method according to the first embodiment.

FIG. 5 is a diagram illustrating a change in a threshold value of a memory cell when data is written using the write determination method according to the first embodiment;

FIG. 6 is a waveform diagram illustrating a write determination method according to a second embodiment that suppresses variation in write determination due to a rise in the potential of a common source line.

FIG. 7 is a diagram illustrating an operation due to a rise in the potential of a source line in a write determination method according to a second embodiment.

FIG. 8 is a diagram illustrating a change in a threshold value of a memory cell when data writing is performed using the write determination method according to the second embodiment.

FIG. 9 is a circuit diagram showing a memory cell according to a third embodiment provided with a correction circuit for making the potential of the common source line constant.

FIG. 10 shows a bias application time and a threshold value V of a memory cell in a write operation in a flash memory according to a fourth embodiment.
13 is a graph showing a relationship of th.

FIG. 11 is a diagram illustrating a distribution width of threshold voltages of memory cells that are determined to have been completely written in a write operation according to a fourth embodiment;

FIG. 12 is a configuration diagram showing a memory cell having a control gate and a floating gate.

FIG. 13 is a diagram showing a processing flow (a) of data writing in a conventional flash memory and a change (b) of a threshold value Vth of a memory cell.

FIG. 14 is a circuit diagram showing an example of an array configuration of a conventional flash memory.

FIG. 15 is a configuration diagram of a memory array for explaining a state at the time of writing determination in a conventional flash memory.

FIG. 16 is a waveform diagram illustrating a state at the time of writing determination in a conventional flash memory.

FIG. 17 is a diagram illustrating a relationship between the number of times of writing and a writing operation time in a conventional flash memory.

18 is a diagram illustrating a distribution width of a threshold value of a memory cell that is determined to be completely written in data writing according to a writing operation time in FIG. 17;

FIG. 19 is a configuration diagram of a conventional memory array showing a state (a) at the time of a write decision at an early stage of data write and a state (b) at a time of a write decision at a later stage of data write.

FIG. 20 is a diagram showing a change in a threshold value of a memory cell when data is written using a conventional write determination.

FIG. 21 is a schematic diagram illustrating a state of a memory cell when a potential rise of a common source line occurs.

FIG. 22 is a waveform diagram illustrating a decrease in a voltage drop of a bit line at the time of writing determination due to a rise in the potential of a common source line.

[Explanation of symbols]

 11 Memory Array 20 Control Circuit 25 Power Supply & Switching Circuit MC Memory Cell CG Control Gate FG Floating Gate Qs2 Source Side Selection MOSFET CSL Common Source Line D1 to D8448 Bit Line W1 to W128 Word Line INV1 Inverter Circuit (Potential Monitoring Circuit) Vth Threshold value Vww Write voltage Vww Verify voltage

Claims (5)

[Claims] 1. A memory array in which a plurality of memory cells each comprising a MOSFET for storing data according to a threshold value is arranged in a matrix, and a control gate of a memory cell in the same row is connected to a corresponding word line. Connected, the drains of the memory cells in the same column are connected to the corresponding bit lines, respectively, and the source is made connectable to the common source line. When writing data, a write voltage is applied to one of the word lines. A change in the potential of the bit line based on the current flowing between the bit line and the common source line via the selected memory cell when the verify operation is applied to the word line after pre-charging the bit line and the word line is detected. A write determination operation of determining whether write is incomplete or complete by performing a write determination operation a plurality of times in a nonvolatile semiconductor memory. A nonvolatile semiconductor memory, wherein the verify voltage is configured to gradually decrease or increase with each determination operation. 2. A memory array comprising a plurality of memory cells each comprising a MOSFET for storing data in accordance with the level of a threshold value, the control gates of memory cells in the same row being connected to corresponding word lines. Connected, the drains of the memory cells in the same column are connected to the corresponding bit lines, respectively, and the source is made connectable to the common source line. When writing data, a write voltage is applied to one of the word lines. A change in the potential of the bit line based on the current flowing between the bit line and the common source line via the selected memory cell when the verify operation is applied to the word line after pre-charging the bit line and the word line is detected. A write determination operation of determining whether write is incomplete or complete by performing a write determination operation a plurality of times in a nonvolatile semiconductor memory. A nonvolatile semiconductor memory, characterized in that the length of time for which a current flows between the bit line and the common source line is gradually shortened or lengthened for each determination operation. 3. A memory array in which a plurality of memory cells each comprising a MOSFET for storing data according to a threshold value is arranged in a matrix, and a control gate of a memory cell in the same row is connected to a corresponding word line. Connected, the drains of the memory cells in the same column are connected to the corresponding bit lines, respectively, and the source is made connectable to the common source line. When writing data, a write voltage is applied to one of the word lines. A change in the potential of the bit line based on the current flowing between the bit line and the common source line via the selected memory cell when the verify operation is applied to the word line after pre-charging the bit line and the word line is detected. A write determination operation of determining whether write is incomplete or complete by performing a write determination operation a plurality of times in a nonvolatile semiconductor memory. A nonvolatile semiconductor memory, wherein the resistance value of the common source line is gradually increased or decreased for each determination operation. 4. A monitoring means for monitoring the potential of the common source line, wherein the verify voltage or the length of the energization time is changed stepwise based on an output from the monitoring means. The nonvolatile semiconductor memory according to claim 1. 5. A memory array in which a plurality of memory cells each comprising a MOSFET for storing data in accordance with the level of a threshold value are arranged in a matrix, and control gates of memory cells in the same row are connected to corresponding word lines. Connected, the drains of the memory cells in the same column are connected to the corresponding bit lines, and the source is made connectable to the common source line. When writing data, a write voltage is applied to one of the word lines And a change in the potential of the bit line based on the current flowing between the bit line and the common source line via the selected memory cell when a verify voltage is applied to the word line after precharging the bit line. And a write determination operation of determining whether write is incomplete or complete by performing a write operation multiple times. The (m-1) th (m is a positive integer), the mth and (m + 1)
The total application time of the write voltage to the selected word line up to the end of each of the write operations is represented by T _{m− 1} ,
Assuming that T _m and T _{m + 1} , log (T _{m + 1} ) −log (T _m ) <log (T _m )
A nonvolatile semiconductor memory configured to perform the write operation so as to satisfy a relationship of −log (T _m−1 ).