JP2002100770A - Insulated gate type semiconductor device - Google Patents

Abstract

(57) [Problem] To provide an insulated gate semiconductor device in which the maximum breaking current density is increased to maintain the resistance of the element in the event of a short circuit and the ON resistance is as low as a thyristor. An insulated gate semiconductor device of the present invention, N ^-
Base layer 1, P-type base layer 2, and P-type base layer 2
Through the N ^- base layer 1 and a depth D
And a gate electrode 4 embedded in the trench 3 via a gate insulating film. A plurality of N-type emitter layers 5 are formed in a well shape along the longitudinal direction of the P-type base layer 2 separated into stripes by the trenches 3, and are formed on the surface of the P-type base layer 2 and the surface of the N-type emitter layer 5. A cathode electrode is formed so as to be electrically connected together. With this basic configuration, the ON resistance can be reduced and the maximum breaking current density can be increased by increasing the depth D of the trench 3 and increasing the conductivity modulation of the N ⁻ base layer 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate semiconductor device and, more particularly, to a high voltage power insulated gate semiconductor device.

[0002]

2. Description of the Related Art Conventionally, as one of power semiconductor devices,
There is an IGBT (Insulated Gate Bipolar Transistor). FIG. 24 is a sectional perspective view of a trench gate type IGBT.

A conventional trench gate type IG shown in FIG.
The BT has an N ⁻ base layer 1 made of a high resistance N-type layer (hereinafter referred to as an N ⁻ layer) having a low impurity concentration, a P-type base layer 2 made of a P-type layer, and penetrates the P-type base layer 2. Trench 3 formed in the depth direction to reach N ^- base layer 1
And a gate electrode 4 formed so as to be embedded in the trench 3 via a gate insulating film.

Further, an N-type emitter layer 5 composed of N-type diffusion layers formed on both sides of the opening along the longitudinal direction of the opening of the trench 3, a surface of these P-type base layers and an N-type A first main electrode (not shown) is formed so as to be electrically connected to the surface of the emitter layer 5 together.
Further, N ^- the lower portion of the base layer 1, a high impurity concentration N
An N ⁺ buffer layer 7 comprising a mold layer (hereinafter referred to as an N ⁺ layer);
A P-type emitter layer 8 made of a P-type layer and a second main electrode (not shown) are provided below the P-type emitter layer 8 so as to be electrically connected.

In order to clarify the structural comparison between the insulated gate semiconductor device of the present invention and the conventional IGBT later, FIG. 25 shows an AA cross section of the IGBT of FIG. The AA cross section in FIG. 24 is a cross section along the XZ plane shown in the upper left of the drawing.

The cross section of the conventional IGBT shown in FIG.
N ⁻ base layer 1, P-type base layer 2, first main electrode 6
, An N ⁺ buffer layer 7, a P-type emitter layer 8, and a second main electrode 9 are shown. Note that the N-type emitter layer 5 of FIG. 20 does not appear in the cross section of the IGBT of FIG.

[0007] As described above, the IGBT is composed of P
Type emitter layer (P-type emitter layer 8), N ^- base layer (N ^-
Base layer 1 and N ⁺ buffer layer 7), P-type base layer (P
Base layer 2), N-type emitter layer (N-type emitter layer 5)
Thyristor structure composed of a four-layer PNPN structure.

However, in the IGBT shown in FIG. 24, the N-type emitter layer 5 and the P-type base layer 2 are electrically connected by the first main electrode 6, and the N-type emitter layer 5 is connected to the N ⁻ base layer. Since the injection of electrons into 1 is performed through N-channels induced on both side surfaces of the trench 3 by the gate electrode 4 embedded in the trench 3 via the gate insulating film, in the ON state of the thyristor structure, The configuration is such that a phenomenon called latch-up in which the voltage between the first and second main electrodes sharply decreases does not occur.

For this reason, the IGBT is a GTO (Gate Turn-O
ff thyristor), the N-type emitter 5 is a source, the N ⁻ base layer 1 is a drain, and the electrode 4 embedded in the trench 3 via a gate insulating film is a gate. The maximum blocking current density is large to utilize the current saturation characteristics peculiar to the insulated gate field effect transistor, and no latch-up occurs.
It is possible to protect the IGBT element from destruction due to a short circuit accident.

On the other hand, the thyristor has an extremely low on-voltage (on-resistance) because the PNPN structure is latched up in the on-state as described above, but has a disadvantage that the maximum breaking current density is small. Further, if the thyristor latches up, it becomes impossible to control the thyristor, so that the thyristor itself cannot be expected to have a protective effect against destruction due to a short circuit accident.

[0011]

As described above, the conventional thyristor has a problem that the thyristor has a low on-resistance but a small maximum breaking current, and is liable to be broken by a short-circuit accident since latch-up occurs. Further, the conventional trench IGBT has a problem that the maximum breaking current density is large but the on-resistance is high.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has a large maximum breaking current density equivalent to that of a trench type IGBT, thereby maintaining the resistance of the element in the event of a short circuit and reducing the on-resistance of the thyristor. It is an object of the present invention to provide an insulated gate semiconductor device having a relatively low value.

[0013]

Means for Solving the Problems] insulated gate semiconductor Symbol location of the present invention, N ^- a first conductivity type base layer comprising a layer, P
A second conductivity type base layer formed of a mold layer, and formed so as to reach a depth D from an interface between the P-type layer and the N ⁻ layer after penetrating the P-type layer from the surface of the P-type layer. The semiconductor device includes a trench (groove) and a gate electrode 4 embedded in the trench via a gate insulating film. A first conductivity type emitter layer including a plurality of N type layers at least one end of which is in contact with the groove along a longitudinal direction of a second conductivity type base layer formed of the P type layer separated by the groove in a stripe shape. Are formed in a well shape, and the surface of the second conductive type base layer and the first conductive type base layer are formed.
A first main electrode serving as a cathode is formed so as to be electrically connected to the surface of the conductive type emitter layer.

According to the basic structure, the on-resistance is reduced by increasing the depth D of the groove from the interface to increase the conductivity modulation of the base layer of the first conductivity type. By using the emitter layer of the first conductivity type as a source for electron injection, the maximum cut-off current density can be increased.

Specifically, the insulated gate semiconductor device of the present invention comprises a high-resistance first conductivity type base layer, a second conductivity type base layer formed on the surface of the first conductivity type base layer, A plurality of first conductive type emitter layers selectively formed on a surface of the second conductive type base layer; and a first conductive type base layer penetrating from the surface of the second conductive type base layer to the second conductive type base layer. A trench formed to reach a certain depth inside the mold base layer, a gate electrode formed to fill the trench through a gate insulating film, a surface of the second conductivity type base layer and the A first main electrode formed so as to be electrically connected to a surface of the one conductivity type emitter layer, a second conductivity type emitter layer formed on a lower surface of the first conductivity type base layer; A second conductive layer formed on the lower surface of the conductive type emitter layer;
The second conductive type base layer forms a stripe-shaped region defined by the two grooves formed in parallel in the longitudinal direction, and the plurality of first conductive type emitter layers Is formed so that both ends thereof are respectively in contact with the two grooves, and a predetermined depth of the groove inside the first conductivity type base layer is D (m), and the stripe-shaped second conductivity type base is The width of the layer is W (m), the repeating unit length of the second conductivity type base layer in a direction perpendicular to the longitudinal direction of the stripe along the surface of the second conductivity type base layer is C (m),
The sheet resistance of the second conductivity type base layer is Rp (Ω / square).
e) When the width in the longitudinal direction of the stripe shape of the first conductivity type emitter layer is d1 (m), (Rp × d1) ²
≦ 2 × 10 ⁻⁷ , W / (C × D) ≦ 1 × 10 ⁵

In the insulated gate semiconductor device, one end of each of the plurality of first conductivity type emitter layers may be two.
The groove is formed so as to be in contact with each of the grooves.

Preferably, the stripe-shaped second conductivity type base layer has a first two grooves formed parallel to a longitudinal direction and a second groove formed parallel to a direction perpendicular to the longitudinal direction. 2 is formed by repeatedly arranging a region whose periphery is defined by the two grooves along the longitudinal direction of the stripe shape, wherein the plurality of first emitter layers are
The two ends are formed so as to be in contact with the first two grooves, respectively, and one end perpendicular to the both ends is formed so as to be in contact with any one of the second two grooves. And

Preferably, the second conductive type base layer has at least one second conductive type base layer adjacent to the second conductive type base layer along a surface of the second conductive type base layer in a direction perpendicular to a longitudinal direction of the stripe shape. The semiconductor device includes the stripe-shaped region including only the conductive base layer, and the repeating unit length C includes a width of the stripe-shaped region including only the at least one second conductive base layer. And More preferably, the second conductivity type base layer includes a first conductivity type barrier layer adjacent to a lower portion thereof.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a sectional perspective view showing the structure of an insulated gate semiconductor device according to a first embodiment of the present invention. The semiconductor device shown in FIG. 1 has an N ⁻ base layer 1, a P-type base layer 2, and a depth D from the interface with the N ⁻ base layer 1 after penetrating the P-type base layer 2. A trench 3 formed in the depth direction, and a gate electrode 4 embedded in the trench 3 via a gate insulating film.
Is provided.

Further, the width W is determined by the trench 3 which is long in the X direction.
A plurality of N-type emitter layers 5 having an interval d and a width d1 along the X direction are formed in a well shape on the P-type base layer 2 separated into stripes. A first main electrode (not shown) is formed so as to be electrically connected to both the surface of P-type base layer 2 and the surface of N-type emitter layer 5.

Here, the N-type emitter layer 5 is the source of the field effect transistor formed along the side surface of the trench 3, the N ^- base layer 1 is the drain, and the gate electrode 4 is the N-channel induced on the side surface of the trench 3. Operates as a gate that controls

The insulated gate semiconductor device shown in FIG. 1 has at least one N-type emitter layer 5 adjacent to a stripe-shaped P-type base layer 2 on which a plurality of N-type emitter layers 5 are formed. A P-type base layer 2 (referred to in claim 4 as a stripe-shaped region consisting of only the second conductivity type base layer) is formed. FIG. 1 shows an example in which three P-type base layers 2 without the N-type emitter layer 5 are formed adjacent to the P-type base layer 2 on which the N-type emitter layer 5 is formed. It is shown.

The three P-type base layers 2 having no N-type emitter layer are separated from each other by a gate electrode 4a embedded in the trench 3a via a trench 3a and a gate insulating film. As described above, the trench 3a and the gate electrode 4a are used merely for element isolation, and are different from the trench 3a and the gate electrode 4 serving as a field effect transistor. Call it a gate.

The insulated gate semiconductor device of the first embodiment includes a stripe-shaped P-type base layer 2 including a plurality of N-type emitter layers 5 and at least one N-type emitter layer adjacent thereto. A structure that is expanded in the Y-direction by using a layer that does not include a layer as a repeating unit is provided. Hereinafter, the repeating unit of the stripe structure is called a cell, and the length of the repeating unit shown in FIG. 1 is called a cell size C.

The first main electrode formed so as to cover the stripe-shaped structure has a structure in which the surface of the N-type emitter layer 5 and the P-type Although formed so as to be electrically connected to the surface of the base layer 2, the surface of the stripe not including the N-type emitter layer 5 is covered with an insulating film, and thus is electrically insulated from these stripes. For other structures,
4, since it is the same as the conventional IGBT described with reference to FIG. 25, the same portions are denoted by the same reference numerals and description thereof will be omitted.

FIG. 2 shows an AA cross section of the insulated gate semiconductor device of FIG. In addition, the AA cross section of FIG. 2 shows a cross section along the XZ plane shown in the upper left of the drawing. The first shown in FIG.
The cross section of the insulated gate type semiconductor device of
^A base layer 1, a P-type base layer 2, and an N-type emitter layer 5
And the first main electrode 6 are shown.

The N-type emitter layer 5 is selectively formed in a well shape from the surface of the P-type base layer 2, and further, is electrically connected to the N-type emitter layer 5 and the P-type base layer 2. Then, a first main electrode 6 is formed. In the insulated gate semiconductor device of the first embodiment shown in FIGS. 1 and 2, the first main electrode 6 in the upper part of the figure is on the cathode side (negative side) and the second main electrode 6 in the lower part of the figure is It operates with the main electrode 9 as the anode side (positive side).

In the cross-sectional structure shown in FIG. 2, an N-channel is induced by a gate electrode 4 buried in the trench 3 via a gate insulating film at a side surface portion in contact with the trench 3, and a plurality of N-type emitter layers 5 N ^- plurality of insulated gate field effect transistor connected in parallel to the base layer 1 and the common drain first main electrode 6 and the N ^- is formed between the base layer 1, through the N-channel N ^- base layer 1 Is performed. Other structures are the same as those of the cross section of the IGBT described with reference to FIG. 25, and thus the same portions are denoted by the same reference numerals and description thereof will be omitted.

The operation of the insulated gate semiconductor device according to the first embodiment thus configured is as follows.
To make the insulated gate semiconductor device conductive (on state), the potential of the gate electrode 4 is made positive with respect to the cathode potential of the first main electrode 6 and the potential of the P-type base layer 2 in contact with the trench 3 is increased. An N channel is induced to inject electrons from the N-type emitter layer 5 into the N ⁻ base layer 1.

At this time, holes corresponding to the amount of injected electrons are injected from the P-type emitter layer 8 into the N ⁻ base layer 1. Such injection of electrons and holes causes conductivity modulation in the N ⁻ base layer 1, lowering the resistance of the N ⁻ base layer and turning on the insulated gate semiconductor device.

In the insulated gate semiconductor device shown in FIG. 1, the depth D of the trench 3 in the N ⁻ base layer 1 is made larger than that of the conventional trench gate IGBT so that the P ⁻ emitter layer 8 and the N ⁻ base layer flow of injected holes to 1, surrounded on both sides by trenches 3 and the gate electrode 4 N ^-
It is configured such that it is narrowed in the region of the base layer 1 and hardly discharged to the P-type base layer. Therefore, holes injected from P-type emitter layer 8 are accumulated in N ⁻ base layer 1.

Electrons corresponding to the accumulated holes are further injected from the N-type emitter layer 5 into the N ^- base layer 1, whereby the conductivity modulation of the N ^- base layer 1 is enhanced, and the insulated gate semiconductor device is formed. Can be effectively reduced. Such an increase in electron injection from the N-type emitter layer 5 due to holes accumulated on the emitter side of the N ⁻ base layer 1 will be referred to as an IE effect (Injection Enhancement Efficient).
ect).

As described above, the striped P-type base layer 2 of the insulated gate semiconductor device shown in FIG. 1 which does not include the N-type emitter layer 5 is the first main electrode 6.
The holes cannot be discharged to the main electrode 6 because they are not electrically connected to the main electrode 6. Therefore, the P-type base layer 2 separated by the dummy trenches 3a and the dummy gates 4a has the N ⁻ base layer 1 surrounded on both sides by the trenches 3 and the gate electrodes 4.
Contributes to the IE effect as in the case of the region, and reduces the on-resistance of the element.

On the other hand, in order to turn off the insulated gate semiconductor device of the present invention (off state), 0 V or a negative voltage is applied to the gate electrode 4 with respect to the first main electrode (cathode electrode) 6. Thus, the N channel formed on the P-type base layer 2 is extinguished. Thus, the N-type emitter layer 5
Since the injection of electrons from the (source) to the N ⁻ base layer 1 (drain) is stopped, the injection of holes from the P-type emitter layer 8 to the N ⁻ base layer 1 is also stopped. As a result, N ^- disappears conductivity modulation in the base layer, N ^- insulated gate semiconductor device of the present invention the resistive base layer 1 becomes high is turned off.

As described above, in the insulated gate semiconductor device according to the first embodiment, the on-current is controlled by the gate of the field effect transistor exhibiting the current saturation characteristic, and the element is controlled by using the conductivity modulation based on the IE effect. By minimizing the resistance of the N ⁻ base layer 1 forming the series resistance of the above and connecting the N-type emitter layer 5 and the P-type base layer with the first main electrode 6 to avoid latch-up, the conventional GTO and It is possible to provide an insulated gate semiconductor device that has a higher maximum breaking current density than a thyristor, has a low on-resistance as low as a GTO or a thyristor, and has an excellent short-circuit withstand capability at a high voltage.

The characteristics of the insulated gate semiconductor device according to the first embodiment have been qualitatively described above.
The basic principle and design method of the insulated gate semiconductor device of the present invention will be described in more detail with reference to FIG. 3A and FIG. Note that the operation principle and the design method described here form the basis of not only the first embodiment but also all the following embodiments.

The basic structure of the insulated gate semiconductor device of the present invention is shown on the right side of FIG. In order to facilitate comparison with a conventional IGBT, an N-type emitter layer shown in FIG.
The structure corresponding to the mold emitter layer 5 is shown. For the dummy gate, only dummy trenches that are important for operation are shown,
The P base separated by the dummy trench is omitted.

The carrier distribution in the Z direction in the N ⁻ base layer is shown on the left side of FIG. As shown in FIG. 1, in the insulated gate semiconductor device of the present invention,
The ratio of the connection surface between the N-type emitter layer and the P base layer to the cathode electrode is designed so that the connection surface of the P base layer is larger and the connection surface of the N-type emitter layer is finer than the conventional IGBT. .

As described above, the conventional I shown in FIG.
In the GBT, the N-type emitter layer 5 and the P-type base layer 2
The hole current, which is electrically connected to the main electrode 6 and flows through the P-type base layer 2 and is discharged to the first main electrode 6, has a built-in voltage between the N-type emitter layer 5 and the P-type base layer 2. This prevents the occurrence of latch-up by preventing it from flowing into the N-type emitter layer 5. In other words, the effect of suppressing the latch-up is as follows: of the total current flowing through the first main electrode 6, the magnitude of the hole bypass current discharged from the connection surface with the P base layer 2 and the magnitude of the impurity concentration of the P base layer 2. Is determined by

The first feature of the design method in the insulated gate semiconductor device of the present invention is that a fine N layer is formed immediately below the first main electrode (cathode electrode) indicated by an arrow in a region (1) of FIG. Forming a P-type emitter layer, increasing the area ratio of the connection surface of the P base layer to the N-type emitter layer,
By a method such as increasing the impurity concentration of the base layer, the ratio of the hole bypass current is increased to improve the latch-up withstand capability, and the short-circuit withstand capability (short-circuit current Isc = 100 A to protect the insulated gate semiconductor device from breakdown at short-circuit) 300A /
Chip).

As a device parameter directly related to the ratio of the connection surface of the P base layer to the N type emitter layer, FIG. 1, FIG. 6, FIG. 8, FIG. 9, FIG. 16 and 17 show d1 and d.
The practically optimum range of d1 and d is from d1 = 1 μm to
2 μm, d = 1 μm to 10 μm, and preferably, d1 is 2 μm or less, and 1 μm or less if technically possible.

The second feature of the design method in an insulated gate semiconductor device of the present invention, adjacent to the P base layer shown arrows in region (2) in FIG. 3 (a), N, surrounded by a trench gate ^- a base layer, N is surrounded by the dummy gate ^- and the base layer, N successive thereunder ^- in the base layer, N ^- based on the increase of the electron injection from the N-type emitter layer by holes stored in the base layer The goal is to maximize the IE effect.

Since the effect of the IE effect on the conductivity of the N ⁻ base layer to reduce the on-resistance of the insulated gate semiconductor device of the present invention has already been described, here, I
Figure 3 shows a shape of the excess carrier concentration distribution that is desirable to maximize the E effect. The opening of the base layer, if designed to produce a peak of excess carrier concentration distribution, N ^{- -} In FIG. 3 (a), N of the dummy gate and trench gate lower illustrated arrow a region (2) in the base layer ON resistance can be minimized.

In FIG. 3A, a portion indicated by an arrow as a region (1) is an insulated gate semiconductor device when the value of the depth D is optimized while maintaining the conventional IGBT structure (in FIG. The excess carrier concentration distribution (excess electron concentration distribution in the figure) in IEGT) is shown by a solid line on the left side of FIG. γ _e is the effective electron injection efficiency at the peak value of the excess electron concentration distribution, and if it is designed to maximize this, the on-resistance can be minimized.

In FIG. 3B, if D = 0, an excess electron concentration distribution with respect to the conventional IGBT shown by the broken line on the left can be obtained. When D = 0, no peak of the excess electron concentration distribution occurs, so that only an element having a high on-resistance can be obtained. The structure on the right side of FIG. 3B shows a structure obtained by dividing the region surrounded by the trench gate of FIG.

As described above, the design feature of the insulated gate semiconductor device of the present invention is that, as shown in the region (1) and the region (2) in FIG. By optimizing, it is possible to satisfy both the improvement of short-circuit tolerance and the reduction of on-resistance.
Optimization of device performance can be achieved at a higher level than before.

Next, the setting conditions of the structural parameters necessary for realizing such excellent performance will be described more specifically. In the first embodiment, the repeating unit length (cell size) of the element is C, the width of the P-type base layer is W, the depth of the trench 3 in the N ⁻ base layer 1 is D, and the N-type The sheet resistance of the P-type base layer immediately below the emitter layer 5 is Rp (Ω / square).
e), the short-circuit current flowing when the element is short-circuited is Isc (A / m ² )
And Here, the element short-circuit means that the element is connected to a high-voltage power supply with the load resistance set to zero, thereby giving the element withstand capability in the event of a load short-circuit.

The width of the N-type emitter layer 5 in the X direction is d1, N
Assuming that the unit length of the repetition in the X direction of the mold emitter layer 5 is d, the maximum breaking current and short-circuit withstand capability are large, and the structural parameters necessary to keep the short-circuit current Isc flowing during an element short-circuit fault low. The conditional expression was determined from the comparison between the theory and the result of the trial production as follows.

As described above, what is particularly important for increasing the short-circuit withstand capability is that in the conventional GTO and thyristor,
It is an object of the present invention to determine a setting condition of a structural parameter for avoiding a latch-up phenomenon in which a voltage between a cathode and an anode sharply drops in a short circuit accident and an element connected to a high voltage power supply is destroyed.

In the insulated gate semiconductor device of the present invention, the N-type emitter layer 5 and the P-type base layer 2 are
And flows through the P-type base layer 2 to form the first
By preventing the hole current discharged to the main electrode 6 from flowing into the N-type emitter layer 5 due to the built-in voltage between the N-type emitter layer 5 and the P-type base layer 2, the occurrence of latch-up is avoided. ing.

However, the current increases during a high-voltage short-circuit fault, and the product of the sheet resistance Rp of the P-type base layer 2 immediately below the N-type emitter layer 5 and the current exceeds the built-in voltage (0.5 V). If this happens, latch-up may occur. As a result of theoretical analysis, it has been clarified that such latch-up does not occur if (Rp × d1) ² is kept within a certain range, and numerical values defining the range were obtained by comparison with the results of trial production.

FIG. 4 is a diagram showing a comparison between the short-circuit current Isc and the sheet resistance Rp of a prototype of the insulated gate semiconductor device of the present invention which does not cause latch-up at a high voltage. Referring to FIG. 4, a conditional expression for preventing the insulated gate semiconductor device of the present invention from causing latch-up is given as follows.

(Rp × d1) ² ≦ 2 × 10 ⁻⁷ (1) On the other hand, in addition to suppressing the latch-up to increase the breakdown voltage of the element,
It is also important to increase the E effect to increase the conductivity modulation of the high resistance N ^- base layer and reduce the on-resistance of the device. If the on-resistance is reduced, thermal destruction of the element due to the short-circuit current Isc can be avoided. As a result of theoretical analysis, it has been clarified that W / (C × D) should be within a certain range in order to enhance the IE effect, and numerical values defining the range were obtained by comparison with the results of trial production.

FIG. 5 is a diagram showing a comparison between the short-circuit current Isc and the cell size C of a prototype of the insulated gate semiconductor device of the present invention which shows a sufficient IE effect while maintaining the value of the short-circuit current Isc. is there. Referring to FIG. 5, a conditional expression for the insulated gate semiconductor device of the present invention to exhibit a sufficient IE effect is given as follows.

W / (D × C) ≦ 1 × 10 ⁵ (2) The insulated gate semiconductor device of the present invention configured as described above has a power supply voltage at the time of short circuit as high as several thousands V, and is normally used. It shows excellent performance as a high withstand voltage power element with a relatively low current density of 10 ⁶ A / m ^2, and maintains a low on-resistance like conventional GTO and thyristor and a maximum breaking current density like conventional IGBT. In addition, it is possible to provide a power semiconductor device having a large resistance during a short circuit accident.

Next, a modification of the insulated gate semiconductor device of the first embodiment will be described with reference to FIGS.
FIG. 7 is a sectional view taken along line AA of FIG. The modification of the first embodiment shown in FIGS. 6 and 7 is different from the first embodiment in that an N-type barrier layer 10 is provided adjacent to a lower portion of the P-type base layer 2. Since other structures are the same as those of the first embodiment, the same portions are denoted by the same reference numerals and detailed description thereof will be omitted.

According to the N-type barrier layer 10 of FIGS. 6 and 7,
A cathode of holes injected from the P-type emitter layer 8 into the N ⁻ base layer 1 corresponding to the electrons injected from the N-type emitter layer 5 into the N ⁻ base layer 1 via the insulated gate transistor formed on the trench side wall. The flow to the side is hindered by a small built-in voltage formed between the N-type barrier layer 10 and the N ⁻ base layer 1, and the effect of making it difficult for these holes to be discharged to the first main electrode 6 is obtained. .

This effect is obtained by increasing the depth D of the trench 3 described above in the first embodiment to make it difficult for holes to flow, or by the N-type emitter separated by the dummy trench 3a and the dummy gate 4a. Since the role of the striped P-type base layer 2 that does not include the layer 5 and cannot discharge holes to the main electrode 6 is the same as that of the N-type barrier layer 10,
It can contribute to the enhancement of the effect. Therefore, by using the modification of the first embodiment shown in FIG. 6, it is possible to provide an insulated gate semiconductor device having a lower on-resistance.

Next, an insulated gate semiconductor device according to a second embodiment will be described with reference to FIG. In the insulated gate semiconductor device according to the second embodiment shown in FIG. 8, the N-type emitter layer 5 is not formed so as to be in contact with only one of the trenches 3 but to be in contact with both of the trenches 3 as shown in FIG. Is different from the first embodiment. Since other structures are the same as those of the first embodiment, the same portions are denoted by the same reference numerals and detailed description is omitted. Note that A in FIG.
2A is similar to FIG. 2 if the N-type emitter layer 5 is formed beyond the center line of the P-type base layer, and is similar to FIG. 25 if it does not reach the center line of the P-type base layer. Become.

The structural feature of the insulated gate semiconductor device of the second embodiment is that the area ratio occupied by the pattern of the N-type emitter layer in the P-type base layer is smaller than that of the first embodiment. The saturation characteristics of the short-circuit current Isc with respect to the voltage are weakened, and an element in which latch-up hardly occurs can be provided.

In the case of a conventional IGBT that does not consider the IE effect, such an N-type emitter layer design significantly increases the on-resistance of the device, and can obtain a realistic current density in the on-state of the device. It becomes difficult. By using an IE effect such as a dummy trench simultaneously with such an emitter structure, an element having a high short-circuit withstand capability and a sufficiently low on-resistance can be obtained for the first time.

FIG. 3 shows the basic principle of the present invention.
In the embodiment, the N-type emitter layer, which is important for the short-circuit withstand capability, has a latch-up withstand capability and the N-type necessary for reducing the on-resistance of the device.
^- it is possible to design the carrier accumulation design of the base layer in a separate parameter, Therefore, the trade-off between short-circuit tolerance or current interruption capability and a low on-resistance properties at a higher level than the conventional Can be realized.

As described above, by changing the pattern shape of the N-type emitter layer in the P-type base layer, it is possible to provide an insulated gate semiconductor device suited for various purposes.

Next, a modification of the insulated gate semiconductor device of the second embodiment will be described with reference to FIG. FIG.
Is different from the second embodiment in that an N-type barrier layer 10 is provided adjacent to a lower portion of the P-type base layer 2. Since other structures are the same as those of the first embodiment, the same portions are denoted by the same reference numerals and detailed description is omitted.

As described above as a modification of the first embodiment, the N-type barrier layer 10 has a hole in the first main electrode 6.
Has the effect of making it difficult to be discharged. If this is used, the second
The reduction of the IE effect in the embodiment can be compensated for, and the on-resistance of the element can be reduced. In the second embodiment and the modifications thereof, the conditional expressions of the structural parameters for obtaining the best result as the power semiconductor element are the same as those previously shown in the expressions (1) and (2). Can be used.

Next, an insulated gate semiconductor device according to a third embodiment will be described with reference to FIGS.
FIG. 11 is a diagram showing an AA cross section of the perspective view shown in FIG. The structural features of the insulated gate semiconductor device of the third embodiment are, as shown in the perspective view of FIG. 10 and the sectional view of FIG. 11, embedded in the trench 3 via the trench 3 and the gate insulating film. The gate electrode 4 is formed in a ladder shape along the X direction (see FIG. 1).

The region composed of the N-type emitter layer 5 and the P-type base layer 2 surrounded by the ladder-type trench 3 so as to be closed is continuously arranged along the X direction, thereby obtaining the third embodiment. A ladder-type stripe pattern including the N-type emitter layer 5 is formed. As in the first and second embodiments, the N-type emitter layer 5 is formed in a well shape on the upper surface of the P-type base layer 2, but as apparent from the cross-sectional view of FIG. In the embodiment, the P-type base layer 2 and the N ⁻ base layer 1 thereunder are also surrounded by the ladder-type trench 3 so as to be closed.

The structure of the striped P-type base layer 2 not including the N-type emitter layer 5 and the structure of the other parts are the same as those of the first and second embodiments, so that they are the same as those of the first and second embodiments. And the detailed description is omitted.

The structure of the insulated gate semiconductor device according to the third embodiment is different from that of the first embodiment in that three sides of the N-type emitter layer 5 are different from those of the first embodiment in that the ladder trench 3
The gate electrode 4 buried in these ladder-type trenches 3 via a gate insulating film in contact with the P-type base layer 2 connected to the lower portions of the three side surfaces of the N-type emitter layer 5 and N That is, a channel is formed.

The difference from the insulated gate semiconductor device of the first embodiment shown in FIG. 1 is that the P-type base layer 2 and the N ⁻ base layer 1 thereunder are also formed in the ladder type trench 3.
Is to be closed.

In the third embodiment, the area ratio occupied by the pattern of the N-type emitter layer 5 in the P-type base layer 2 is large, and the N-type emitter layer 2 is formed on the three side surfaces of the ladder-type trench. N ^- base layer 1 through channel
, The ratio of the channel current of the electrons flowing through the N channels on the three side surfaces of the ladder trench 3 to the bypass current of the holes discharged to the first main electrode 6 is increased. be able to.

In the third embodiment, the P-type base layer 2 and the N ⁻ base layer 1 thereunder are also surrounded by the ladder-type trench 3 so that the P-type emitter layer on the anode side is closed. The first embodiment shows the effect that the flow of holes for discharging holes injected into the N ⁻ base layer 1 from the N ⁻ 8 into the P-type base layer 2 on the cathode side is obstructed by the ladder-type trench 3 having a depth D according to the first embodiment. It can be larger than.

As described above, in the insulated gate semiconductor device according to the third embodiment, since the ratio of the channel current of electrons to the bypass current of holes is large, the short-circuit current Isc
And the flow of holes discharged to the cathode side in the region of the N ⁻ base layer 1 surrounded by the ladder-type trench 3 having a depth D is prevented.
Although the IE effect is enhanced and the on-resistance of the element is reduced,
On the other hand, since the area ratio of the N-type emitter layer is large, latch-up may easily occur. But,
If sufficient measures are taken against latch-up, the insulated gate semiconductor device of the third embodiment exhibits ideal performance as a power semiconductor element.

Next, a modification of the insulated gate semiconductor device of the third embodiment will be described with reference to FIGS. FIG. 13 is a view showing an AA cross section of the perspective view shown in FIG. The modification of the third embodiment shown in FIGS. 12 and 13 is different from the third embodiment in that an N-type barrier layer 10 is provided adjacent to a lower portion of the P-type base layer 2. Since other structures are the same as those of the first embodiment, the same portions are denoted by the same reference numerals and detailed description is omitted.

As described in the modification of the first embodiment, the N-type barrier layer 10 has an effect of making it difficult for holes to be discharged to the first main electrode 6. By using this, the IE effect in the third embodiment can be further enhanced, and the on-resistance of the element can be reduced. In the third embodiment and its modified examples, the conditional expressions of the structural parameters for obtaining the best result as the power semiconductor element are the same as those previously shown in the expressions (1) and (2). Can be used.

Next, an insulated gate semiconductor device according to a fourth embodiment will be described with reference to FIG. As shown in the perspective view of FIG. 14, the structural features of the fourth embodiment are similar to those of the insulated gate semiconductor device of the first embodiment described above with reference to FIGS. are doing.

That is, the gate electrode 4 buried in the trench 3 elongated in the X direction via the gate insulating film causes the width W
A plurality of N-type emitter layers 5 having an interval d and a width d1 along the X direction are formed in a well shape on the P-type base layer 2 separated into stripes. First main electrode 6 is formed so as to be electrically connected to both the surface of P-type base layer and the surface of N-type emitter layer 5.

However, in the insulated gate semiconductor device according to the first embodiment described above with reference to FIG. 1, adjacent to the striped P-type base layer 2 on which a plurality of N-type emitter layers 5 are formed. Thus, at least one P-type base layer 2 having no N-type emitter layer 5 is formed. However, in the fourth embodiment shown in FIG. Without the layer 2 interposed therebetween, the striped P-type base layers 2 on which the plurality of N-type emitter layers 5 are formed are formed adjacent to each other.

As shown on the left side of FIG. 14, the end portion of the aggregate composed of the P-type base layer 2 including the plurality of N-type emitter layers 5 adjacent to each other is simply set to the P-type base layer 2.
Alternatively, as shown on the right side of FIG. 14, the dummy trench 3a and the dummy gate 4a may be used. Note that the first main electrode 6 is not electrically connected to the P-type base layer 2 at the terminal end where the N-type emitter layer 5 does not exist.

The insulated gate semiconductor device of the fourth embodiment thus configured is different from the first embodiment in that the N-type emitter layer 5 is the source and the N ⁻ base layer 1 is the common drain. Insulated gate field effect transistors are arranged at high density in the element pattern. For this reason, the ratio of the channel current of electrons to the bypass current of holes discharged to the first main electrode on the cathode side becomes large, and the short-circuit current I
The saturation characteristics with respect to the voltage of sc are enhanced.

In the fourth embodiment, the N-type emitter layer 5
Since the element pattern is formed without interposing the P-type base layer 2 where no P-type layer exists, the hole current is not blocked by these P-type base layers 2 described in the first embodiment. The reduction of the on-resistance of the device due to the IE effect is slightly inferior to that of the first embodiment, but the ratio of the channel current of electrons becomes large, so that the on-current of the device is supplemented by the channel current. .

Next, a modification of the insulated gate semiconductor device of the fourth embodiment will be described with reference to FIG. The modification of the fourth embodiment shown in FIG. 15 is different from the fourth embodiment in that an N-type barrier layer 10 is provided adjacent to a lower portion of the P-type base layer 2. Since other structures are the same as those of the first embodiment, the same portions are denoted by the same reference numerals and detailed description is omitted.

As described above as a modification of the third embodiment, the N-type barrier layer 10 has a hole in the first main electrode 6.
Has the effect of making it difficult to be discharged. If this is used, the third
The reduction of the IE effect in the embodiment can be compensated for, and the on-resistance of the element can be reduced. In the fourth embodiment and its modification, the conditional expressions of the structural parameters for obtaining the best result as the power semiconductor element are the same as those shown in the expressions (1) and (2) above. Can be used.

Next, an insulated gate semiconductor device according to a fifth embodiment will be described with reference to FIG. As shown in the perspective view of FIG. 16, the structural features of the fifth embodiment are similar to those of the insulated gate semiconductor device of the third embodiment described earlier with reference to FIGS. are doing.
That is, the gate electrode 4 embedded in the trench 3 via the trench 3 and the gate insulating film is formed in a ladder shape along the X direction (see FIG. 1).

The region composed of the N-type emitter layer 5 and the P-type base layer 2 surrounded by the ladder-type trench 3 so as to be closed is continuously arranged along the X direction, thereby obtaining the fifth embodiment. A ladder-type stripe pattern including the N-type emitter layer 5 is formed. As in the third embodiment,
The P-type base layer 2 and the N ⁻ base layer 1 thereunder are also enclosed by the ladder-type trench 3 so as to be closed.

However, in the insulated gate semiconductor device according to the third embodiment described above with reference to FIGS. 10 and 11, a stripe-shaped P-type base layer having a plurality of N-type emitter layers 5 formed thereon. At least one P-type base layer 2 having no N-type emitter layer 5 is formed adjacent to the N-type emitter layer 2, but in the fifth embodiment shown in FIG. 16, the N-type emitter layer 5 does not exist. Without the P-type base layer 2 interposed therebetween, the striped P-type base layers 2 on which the plurality of N-type emitter layers 5 are formed are formed adjacent to each other.

In FIG. 16, these adjacent stripe patterns are d / d in the X direction (see FIG. 1).
However, since it is difficult to form a deep trench crossing in a cross shape in the manufacturing process, the intersection of the trench is formed in a T-shaped structure that is easy to manufacture. is there. There is no change in element performance whether the intersection of the trenches is cross-shaped or T-shaped.

The terminal portion of the pattern composed of the P-type base layer 2 including the plurality of N-type emitter layers 5 adjacent to each other may be simply surrounded by the P-type base layer 2 as shown on the left side of FIG. Then, as shown on the right side of FIG.
It may be surrounded by the trench 3a and the dummy gate 4a. Note that the first main electrode 6 is not electrically connected to the P-type base layer 2 at the terminal end where the N-type emitter layer 5 does not exist.

The insulated gate semiconductor device of the fifth embodiment having the above-described structure is different from that of the third embodiment in that the N-type emitter layer 5 is used as the source and the N ⁻ base layer 1 is used as the common drain. Insulated gate field effect transistors are arranged at high density in the element pattern. For this reason, the ratio of the channel current of the electrons to the bypass current of the holes discharged to the first main electrode on the cathode side becomes large, and the saturation characteristic with respect to the voltage of the short-circuit current Isc is enhanced.

However, in the third embodiment, since the element pattern is formed without interposing the P-type base layer 2 in which the N-type emitter layer 5 does not exist, those described in the first embodiment are used. The hole current is not blocked by the P-type base layer 2 described above, and therefore, the reduction of the on-resistance of the element by the IE effect is slightly inferior to that of the first embodiment.
On the other hand, since the ratio of the channel current of electrons becomes large, the on-current of the element is supplemented by the channel current.

Next, a modification of the insulated gate semiconductor device of the fifth embodiment will be described with reference to FIG. The modification of the fifth embodiment shown in FIG. 17 is different from the fifth embodiment in that an N-type barrier layer 10 is provided adjacent to a lower portion of the P-type base layer 2. Since other structures are the same as those of the first embodiment, the same portions are denoted by the same reference numerals and detailed description is omitted.

As described above as a modification of the third embodiment, the N-type barrier layer 10 has a hole in the first main electrode 6.
Has the effect of making it difficult to be discharged. If this is used, the fifth
The reduction of the IE effect in the embodiment can be compensated for, and the on-resistance of the element can be reduced. In the fifth embodiment and its modifications, the conditional expressions of the structural parameters for obtaining the best result as the power semiconductor element are the same as those previously shown in the expressions (1) and (2). Can be used.

Next, a sixth embodiment will be described with reference to FIGS. In the sixth embodiment, the performance of the insulated gate semiconductor device of the present invention will be described. FIG. 18 shows that the insulated gate type semiconductor device of the present invention was Vge = ± 15 V under the conditions of a junction temperature Tj = 125 ° C. and a load: 4 μH.
FIG. 6 is a diagram showing operation waveforms when the operation is turned on / off in the example. At the power supply voltage Vcc = 2250 V, the peak value of the device current Ic (substantially equal to the short-circuit current Isc) reached 200 A, and the device could be safely operated without destruction.

FIG. 19 shows Tj: room temperature, load: 10 μm.
Under the condition of H, the insulated gate semiconductor device of the present invention is
It is a figure which shows the operation | movement waveform at the time of ON / OFF at ± 15V. When the power supply voltage Vcc = 2700 V, the element current I
The peak value of c reached 200 A, and the device could be safely operated without breaking the device. These figures are record values for this type of power element.

Next, the seventh embodiment of the present invention will be described with reference to FIGS.
An embodiment will be described. In a seventh embodiment, the details of the pattern shape of the insulated gate semiconductor device of the present invention will be described.

FIG. 20 is a diagram showing an example of the pattern shape of the insulated gate semiconductor device described in the first embodiment. 4 or 4a is a pattern showing a gate or a dummy gate embedded in the trench 3 or the dummy trench 3a via the gate insulating film. Since the dummy gate is normally grounded, a space is provided for making the dummy gate 4a slightly shorter than the gate 4 for grounding.

Reference numeral 5 denotes an N-type emitter layer, and reference numeral 2 denotes a P-type base layer. An insulating film is formed on the entire pattern of the insulated gate semiconductor device shown in FIG. 20, and an opening 11 for connecting the N-type emitter layer 5 and the P-type base layer 2 is provided. A metal film 12 made of aluminum or the like is deposited on the entire surface as a first main electrode 6 (cathode), and is heat-treated so that the N-type emitter layer 5 is
Only the mold base layers 2 are electrically connected to each other. The other regions are not connected because they are covered with the insulating film.

FIG. 21 is a diagram showing an example of the pattern shape of the insulated gate semiconductor device described in the second embodiment. Except that only one side of the N-type emitter layer 5 is in contact with the trench, the description is omitted because it is the same as FIG. FIG.
0 and FIG. 21 show an example of the dimension of the pattern shape. In these examples, the N-type emitter layer 5 formed in a well shape on the surface of the P-type base layer 2 has a length of 2 μm in the trench direction, and the trench of the P-type base layer 2 between the adjacent N-type emitter layers 5. Since the length in the direction is 1 μm, the above-described bypass of the hole current discharged to the cathode is set small.

Next, an example of a chip structure including an electrode portion of the insulated gate semiconductor device of the present invention will be described more specifically with reference to FIG. An insulating film made of CVD SiO ₂ is deposited on the entire surface of the cathode-side element, and an opening 11 (see FIGS. 20 and 21) is formed along the X direction.
By depositing a metal film 12 such as aluminum on the upper surface and performing a heat treatment, only the N-type emitter layer and the P-type base layer exposed in the opening 11 are electrically connected to the metal film 12 such as aluminum. Note that the gate electrode is drawn out from the opening of the trench.

With reference to FIGS. 23A and 23B,
An example of the structure of the press-contact package of the insulated gate semiconductor device of the present invention will be described. FIG. 23B shows FIG.
3A illustrates a circuit configuration. A plurality of insulated gate semiconductor device chips 20 shown in FIG. 22 and a buffer layer 2 in which a flywheel diode 30 is made of a soft metal sheet
The electrodes 2 and 23 are pressed using the metal electrodes 24 and 25 for pressing on the cathode side and the anode side.

In the metal electrode 24 for pressure contact on the cathode side, a groove is formed which is used for routing the gate wiring 22 and the like connected from the gate circuit 29 to the gate electrode portion 22 of the chip 20. The other terminal of the gate circuit 28 is connected to the cathode. The flywheel diode 30 plays a role of protecting the element against a surge voltage in the reverse direction.

The present invention is not limited to the above embodiment. For example, in the modified examples of the first to fifth embodiments, the N-type barrier layer 10 does not necessarily need to be provided under all the stripe-shaped P-type base layers 2.
If provided only below the P-type base layer including the N-type emitter layer 5, a certain IE effect can be obtained. In addition, various modifications can be made without departing from the spirit of the present invention.

[0104]

As described above, according to the insulated gate semiconductor device of the present invention, the power supply voltage at the time of short circuit is as high as several thousand volts,
It shows excellent performance as a high withstand voltage power device with a relatively low current density of 10 ⁶ A / m ² , a low on-resistance similar to conventional GTO and thyristor, and a maximum cut-off current density comparable to conventional IGBT. It is possible to provide a power semiconductor device having a large withstand voltage at the time of a short circuit accident while maintaining the above.

[Brief description of the drawings]

FIG. 1 is a perspective view showing the structure of an insulated gate semiconductor device according to a first embodiment.

FIG. 2 is a diagram showing an AA cross section of the insulated gate semiconductor device according to the first embodiment;

3A and 3B are diagrams for explaining the basic principle of the insulated gate semiconductor device of the present invention in comparison with a conventional IGBT, and FIG.
1 is a conceptual diagram showing a basic configuration of a device and a carrier distribution in an operating state. (B) shows the IEGT of the present invention and the conventional IG
The figure which shows the simulation result which compares the carrier accumulation effect of BT.

FIG. 4 is a diagram showing the relationship between the sheet resistance of the P-type base layer and the short-circuit current of the insulated gate semiconductor device of the present invention.

FIG. 5 is a diagram showing the relationship between the cell size and the short-circuit current of the insulated gate semiconductor device of the present invention.

FIG. 6 is a perspective view showing a structure of an insulated gate semiconductor device according to a modification of the first embodiment.

FIG. 7 is a diagram showing an AA cross section of an insulated gate semiconductor device according to a modification of the first embodiment.

FIG. 8 is a perspective view showing the structure of an insulated gate semiconductor device according to a second embodiment.

FIG. 9 is a perspective view showing the structure of an insulated gate semiconductor device according to a modification of the second embodiment.

FIG. 10 is a perspective view showing the structure of an insulated gate semiconductor device according to a third embodiment.

FIG. 11 is a view showing an AA cross section of the insulated gate semiconductor device according to the third embodiment;

FIG. 12 is a perspective view showing the structure of an insulated gate semiconductor device according to a modification of the third embodiment.

FIG. 13 is a diagram showing an AA cross section of an insulated gate semiconductor device according to a modification of the third embodiment.

FIG. 14 is a perspective view showing the structure of an insulated gate semiconductor device according to a fourth embodiment.

FIG. 15 is a perspective view showing the structure of an insulated gate semiconductor device according to a modification of the fourth embodiment.

FIG. 16 is a perspective view showing the structure of an insulated gate semiconductor device according to a fifth embodiment.

FIG. 17 is an exemplary perspective view showing the structure of an insulated gate semiconductor device according to a modification of the fifth embodiment;

FIG. 18 is a diagram showing the performance of the insulated gate semiconductor device according to the sixth embodiment.

FIG. 19 is a view showing another performance of the insulated gate semiconductor device according to the sixth embodiment;

FIG. 20 is a view showing a pattern shape of an insulated gate semiconductor device according to a seventh embodiment;

FIG. 21 is a view showing another pattern shape of the insulated gate semiconductor device according to the seventh embodiment;

FIG. 22 is a perspective view showing an electrode structure of the insulated gate semiconductor device of the present invention.

23A and 23B are diagrams illustrating a structure of a package of an insulated gate semiconductor device of the present invention, and FIG. 23A illustrates an example of a structure of a press-contact electrode type package. (B) is a circuit diagram showing an electrical configuration of a press-contact electrode type package.

FIG. 24 is a perspective view showing the structure of a conventional insulated gate semiconductor device.

FIG. 25 is a diagram showing a cross section AA of a conventional insulated gate semiconductor device.

[Explanation of symbols]

1 ... N ^- base layer 2 ... P-type base layer 3 ... trenches 3a ... dummy trench 4 ... gate electrode 4a ... dummy gate electrode 5 ... N-type emitter layer 6 ... first main electrode 7 ... N ⁺ buffer layer 8 ... P-type Emitter layer 9 Second main electrode 10 N-type barrier layer 11 Opening 12 Aluminum film 20 Chip of insulated gate semiconductor device 21 and 23 Soft metal plate 22 Gate electrode part 24 Cathode electrode 25 Anode electrode for crimping 26 ... Crimping type package

Claims (5)

[Claims] A first conductive type base layer having a high resistance; a second conductive type base layer formed on a surface of the first conductive type base layer; and a second conductive type base layer selectively formed on a surface of the second conductive type base layer. A plurality of formed first conductivity type emitter layers; and a layer penetrating from the surface of the second conductivity type base layer to the second conductivity type base layer to reach a certain depth inside the first conductivity type base layer. A gate electrode formed so as to fill the groove via a gate insulating film; and a surface of the second conductive type base layer and a surface of the first conductive type emitter layer both electrically connected to each other. A first main electrode formed to be connected; a second conductive type emitter layer formed on a lower surface of the first conductive type base layer; and a second conductive layer formed on a lower surface of the second conductive type emitter layer. And a second conductive type base layer in the longitudinal direction. Forming a stripe-shaped region defined by the two grooves formed in a row, wherein the plurality of first conductivity type emitter layers are formed such that both ends thereof respectively contact the two grooves; The constant depth of the groove inside the first conductivity type base layer is D (m), the width of the stripe-shaped second conductivity type base layer is W (m), and the surface of the second conductivity type base layer is Along the direction perpendicular to the longitudinal direction of the stripe, the repeating unit length of the second conductivity type base layer is C (m), and the sheet resistance of the second conductivity type base layer is Rp (Ω / square).
e) When the width in the longitudinal direction of the stripe shape of the first conductivity type emitter layer is d1 (m), (Rp × d1) ²
≦ 2 × 10 ⁻⁷ and W / (C × D) ≦ 1 × 10 ⁵ are satisfied. 2. The insulated gate semiconductor device according to claim 1, wherein said plurality of first conductivity type emitter layers are formed such that one ends thereof respectively contact said two grooves. 3. The stripe-shaped second conductivity type base layer includes a first two grooves formed parallel to a longitudinal direction and a second groove formed parallel to a direction perpendicular to the longitudinal direction.
Are formed by repeatedly arranging a region whose periphery is defined by the two grooves along the longitudinal direction of the stripe shape, and the plurality of first emitter layers have both ends of the first two 2. The insulated gate according to claim 1, wherein each of the first and second grooves is formed so as to be in contact with each of the second grooves, and one end perpendicular to the both ends is each in contact with any one of the second two grooves. 3. Type semiconductor device. 4. The second conductive type base layer having a stripe shape, wherein at least one second conductive type base layer adjacent to the stripe-shaped second conductive type base layer in a direction perpendicular to a longitudinal direction of the stripe shape along a surface of the second conductive type base layer. The semiconductor device according to claim 1, wherein the stripe-shaped region including only the layer is provided, and the repeating unit length C includes a width of the stripe-shaped region including only the at least one second conductivity type base layer. 4. The insulated gate semiconductor device according to any one of 1 to 3. 5. The insulated gate semiconductor device according to claim 1, wherein the second conductivity type base layer includes a first conductivity type barrier layer adjacent to a lower portion thereof.