JP2002100548A - Semiconductor device yield prediction system, yield prediction method, and semiconductor device design method - Google Patents

Abstract

(57) Abstract: A semiconductor memory device having a rescue circuit for relieving a defective portion is practically yielded by using a Monte Carlo method, while considering whether or not the rescue can be performed depending on the type of a defect that occurs. Provided is a yield prediction system capable of prediction. A semiconductor device to be predicted includes a plurality of types of wirings 12, 14, 16 and at least one type of rescue circuit for relieving a defect occurring in the wiring by a method according to the type of the defect. including. A plurality of foreign substances 5015 and the like are virtually dropped on this semiconductor device at random, and the ratio of foreign substances that cause a wiring failure among the foreign substances is calculated for each type of failure. By calculating the yield for each type of defect using the number of foreign substances on the semiconductor device manufacturing line determined in advance and the above ratio, the product of the yield for each type of defect is obtained, thereby obtaining the yield of the semiconductor device. Is calculated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a system and a prediction method for predicting the production yield of semiconductor devices such as semiconductor memories, and a method for designing a semiconductor device using the prediction method.

[0002]

2. Description of the Related Art In recent years, high integration of semiconductor memory devices has progressed, and it has become extremely difficult to secure a high yield of products. Further, while the shortening of the product cycle in the market is progressing rapidly, the manufacturing TAT (turn around time) is lengthening due to the complicated manufacturing process. For this reason, in order to supply products at the time requested by the customer, it is necessary to predict the production yield with high accuracy and to start construction of a required number of products based on the yield.

One of the factors that reduce the yield of memory devices is the generation of foreign matter in the manufacturing process. Foreign matter is generated in larger quantities as the size is smaller, and in combination with miniaturization of devices, the occurrence of defective products due to the foreign matter is inevitable. At present, in order to reduce the overall failure of the memory device, of the multiple memory circuits that make up the memory device, the defective memory portion due to the accumulation of foreign matter is prepared in advance in the memory device. A method of replacing the redundant memory with a redundant memory is used.

[0004] Even in the case of using this method of preparing a redundant memory, it is important to predict how much of the memory circuits constituting the memory device will be defective due to foreign matter and the frequency of occurrence. It is. Because the redundant memory is manufactured in the same manufacturing process as the memory circuit in the memory device, the number of redundant memories to be arranged in one memory device needs to be determined in advance when designing the memory device. At this time, if the number of redundant memories to be arranged is large, the product yield increases, but the space for arranging the redundant memories increases, the chip area also increases, and the number of products to be obtained per wafer decreases, resulting in cost loss. Occurs. Therefore, in order to provide a product at a cost required by a customer, a prediction method for predicting a yield at which a memory circuit in a memory device becomes defective and a design method for determining a circuit size of a redundant memory from the yield are required. Become.

Conventionally, there has been reported a technique of designing a circuit of a memory device having a redundant memory after predicting a yield. Above all, there is a method called critical area analysis that predicts the yield in consideration of the frequency of occurrence of each foreign matter (foreign particle size distribution) and the probability that the foreign matter becomes a fatal defect. This method uses the actual measurement result of the particle size distribution generated in a manufacturing line or a process and the actual design layout to determine the probability of occurrence of a foreign particle at random in a critical area (having an arbitrary shape) in the entire LSI chip. The area ratio is determined as the area ratio of a foreign substance (an area which causes a fatal defect such as a wiring short-circuit when the foreign substance is present at the coordinate center). In this method, the fatal probability is obtained for each size of the foreign matter, and the yield is calculated based on the product of the obtained fatal probability and the frequency of occurrence of the foreign matter.

There are two calculation methods for calculating the critical area. Each calculation method will be described below by assuming a circular conductive foreign substance having a radius r as a foreign substance and taking a yield due to a short circuit between wirings as an example.

(1) Wiring width expansion method (geometry method) This method assumes that wiring on a design layout is expanded by an amount equal to the radius r of a foreign substance, and an overlapped portion of these expanded wirings becomes a critical area. The critical area is obtained by using the equivalent.

(2) Monte Carlo Method In this method, a foreign substance having a radius r is scattered on coordinates on a design layout determined based on random numbers, and the foreign substance shorts with a plurality of types of wirings in the layout. This is a method of calculating the fatal probability by counting the number and calculating the ratio to the total number of dropped foreign substances.

[0009] Even in a memory device having a redundant memory, whether or not a generated defect can be remedied by the redundant memory depends on the type of the defect. For example, a defect between word lines can be remedied by a redundant memory, but a short circuit between a word line and a power supply line may not be relieved due to circuit design. Therefore, when calculating the yield of a memory device having a redundant memory, it is desirable to discriminate the type of wiring that has been short-circuited due to foreign matter, calculate the respective critical areas, and calculate the yield. This method predicts local failure modes,
This is called a micro-yield model. As a conventional example, the critical area analysis for each wiring function by the above-described wiring expansion method is described as “Accurate Estimate”.
ionof Defect-Related Yiel
d Loss in Reconfigurable
VLSI Circuits, IEEE Journa
l of Solid-state Circuit
s, Vol. 28, NO. 2, February, 19
93 ".

[0010]

SUMMARY OF THE INVENTION The above-described wiring expansion method includes:
When calculating a large-scale real layout pattern with high accuracy,
The calculation time becomes enormous. For this reason, it is not practical to obtain the yield of the micro yield model by the wiring width extension method.

According to the present invention, it is possible to practically predict the yield of a semiconductor device having a relief circuit for relieving a defective portion by using the Monte Carlo method while considering whether or not the rescue can be performed depending on the type of a defect that occurs. It is an object of the present invention to provide a reliable yield prediction system.

[0012]

In order to achieve the above object, according to the present invention, the following yield prediction system is provided. That is, a yield prediction system for a semiconductor device including a plurality of types of wirings and one or more types of rescue circuits for relieving defects occurring in the wirings, wherein a virtual device is provided on the semiconductor device to be predicted. A defect occurrence ratio calculating means for randomly dropping a plurality of foreign matters and calculating a ratio of foreign matters that cause a defect in the wiring of the semiconductor device among the foreign matters, and a semiconductor device manufacturing line determined in advance. And a yield calculating means for calculating the yield of the semiconductor device by using the number of foreign substances and the ratio, wherein the defect occurrence ratio calculating means obtains the ratio for each type of the predetermined defect. The yield calculating means calculates the yield for each type of the defect, and then calculates the product of the yield for each type of the defect, thereby obtaining the product of the semiconductor device. A yield prediction system and obtains the stops.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A yield prediction system according to one embodiment of the present invention will be described.

The target of the yield prediction system of the present embodiment is a semiconductor memory device. The semiconductor memory device includes a plurality of memory circuits such as a RAM and a memory circuit when a failure occurs in some of the memory circuits. And a rescue circuit (redundancy circuit) for relieving a defect by replacing the memory circuit. In addition, the cause of the defect is a random defect due to a foreign substance among various defects that occur during the manufacture of the semiconductor memory device, and particularly, only a wiring short-circuit due to the foreign substance. Also, when a semiconductor memory device to be predicted relieves a defective memory circuit, depending on the type of the short-circuited wiring, for example, a short-circuit between a word line and a data line or a short-circuit between a data line and a power supply line is performed. The rescue method, such as whether rescue is possible or the type of rescue circuit used, differs depending on the situation. The yield prediction system according to the present embodiment predicts the yield in consideration of the type of the short-circuited wiring. Hereinafter, the type of short-circuited wiring is referred to as a short mode.

The configuration of the yield prediction system according to the present embodiment will be described with reference to FIG. The yield prediction system includes a storage unit 103 that stores a yield prediction program, and a CPU 105 that reads and executes the yield prediction program.
An input device 100 for receiving data and conditions necessary for executing the yield prediction program from an operator,
Data storage units 102, 104, and 106 for storing data and conditions received by the input device 100, and an output device 10 for outputting calculation results of the CPU 105, intermediate data, and the like.
7 is included. These are connected by a network 101. The CPU 105 stores the layout data of the semiconductor memory device to be predicted among the data and conditions received by the input device 100 in the storage unit 102, stores the foreign matter data of the manufacturing line in the storage unit 106, and stores other data and conditions. Is stored in the storage unit 104. The storage unit 10
As 3, it is also possible to use a reproducing device that reads a yield prediction program from a recording medium in which the program is recorded in advance.

Next, an outline of the operation of the yield prediction system will be described with reference to FIG.

The yield prediction program in the storage unit 103 is as follows:
It is roughly divided into a critical area analysis operation unit 103a that analyzes a critical area by the Monte Carlo method and a yield operation unit 103b. The critical area analysis operation unit 103a randomly drops a sufficient number of virtual foreign substances (that is, drops by the Monte Carlo method) sufficient to satisfy the calculation accuracy on the layout of the semiconductor memory device whose yield is to be predicted. Critical area analysis is performed to determine the ratio of foreign matter that has resulted in a short circuit (fatal defect) between wirings. The ratio obtained by the critical area analysis is called a fatality rate. In the present embodiment, the semiconductor memory device whose yield is to be predicted is divided for each wiring layer, each wiring layer is further divided into regions, and the fatality rate is obtained for each short mode in the region. Critical area analysis operation unit 1
03a uses data and conditions received by the input device 100 from an operator as layout data, foreign particle size distribution parameters, calculation conditions, and the like necessary for analysis.

The yield calculation unit 103b calculates the yield for all the short modes based on the criticality ratio obtained for each short mode by the critical area analysis calculation unit 103a, and multiplies the yield for each short mode to obtain the final yield. And to predict the yield of various semiconductor memory devices. The rescue method, the number of rescue circuits, the number of memory circuits, the number of memory circuits, the foreign matter data of the manufacturing line, etc., required for calculating the yield for each short mode and indicating how to remedy the short circuit for each short mode are input devices. 100
Uses the data received from the operator.

Next, the operation of the yield prediction system will be described in detail with reference to the flowchart of FIG.

The CPU 105 performs a yield prediction process as shown in the flowchart of FIG. 2 by reading and executing the yield prediction program in the storage unit 103. First,
The CPU 105 reads the layout data stored in the storage unit 102 in Step 1. The layout data is data received by the input device 100 from the operator. The layout data includes figure shape information, figure arrangement information, and layer number information indicating the layout of the semiconductor memory device whose yield is to be predicted.

In the present embodiment, the semiconductor memory device shown in FIG. The semiconductor memory device includes a RAM unit 3a including a plurality of RAMs 3,
A and B types of relief circuits 3b and 3c and α and β2 types of peripheral circuits 3d and 3e are included. The RAM 3 includes a word line, a data line, and a power supply line. Relief circuit 3b,
3c is configured by a plurality of RAM circuits having the same configuration as the RAM3. This semiconductor memory device has M
., M2, M3... These M1, M2, M3, etc. are called layer names. The rescue circuits 3b and 3c are arranged so that when a part of the RAM unit 3a becomes defective, the defective part is replaced with an electric circuit. Peripheral circuit 3 other than RAM unit 3a
For d and 3e, no relief circuit is provided because the occupied area is small and the yield influence is low.

The number of relief circuits 3b and 3c is predetermined as design information. The units of the relief circuits 3b and 3c are:
Various designs such as a column unit in which a plurality of RAM circuits are arranged in a line, a row unit in which a plurality of RAM circuits are arranged in a line, and a block unit constituted by the plurality of columns and rows can be designed.
In order to simplify the description, the repair is performed in a virtual unit called a set. The rescue method is predetermined at the initial design stage. In the present embodiment, the rescue method shown in FIG. 9 is defined. That is, when the word line and the data line of the M1 layer are short-circuited, the type A relief circuit 3
b. One set of b is used for rescue. When the data line of the M1 layer and the power supply line are short-circuited, one type B of the rescue circuit 3c is used for rescue. If the word line and the power supply line of the M1 layer are short-circuited, or if the word line, the data line and the power supply line are short-circuited, the circuit configuration cannot be relieved. If a short circuit occurs in the wiring in the peripheral circuits 3d and 3e, the circuit cannot be relieved because no rescue circuit is provided.

The input device 100 includes word lines, M1, M2, M3,...
Data indicating the shapes and arrangements of the data lines and power supply lines and the shapes and arrangements of the wiring of the peripheral circuits 3d and 3e are received. Here, the format of this data is a unique format output from a CAD tool for designing a metal wiring layer of a semiconductor memory device, or a more general stream file format.

However, in the present embodiment, in order to determine the criticality for each short mode in a later step, the word lines, data lines, power supply lines, and wiring of the peripheral circuits 3d and 3e included in the metal wiring layer are provided. Must be distinguished from each other. Therefore, in this embodiment, when the input device 100 receives the layout data, the word line, the data line, the power supply line, and the wiring of the peripheral circuits 3d and 3e are connected to each of the layers M1, M2, M3,. Prompts the operator to add a line number to the format. Specifically, as shown in FIG. 3B, the layout data is such that word lines, data lines, power supply lines, and wirings of the peripheral circuits 3d and 3e in each layer are distinguished by line numbers. In the form shown in FIG. For example, in the M1 layer, FIG.
The word line number is 12 and the data line number is 1
4, the line number of the power supply line is 16, and the line number of the wiring of the peripheral circuits 3b and 3c is 18.

In the next step 2, the CPU 105 stores the values of the particle size distribution parameters D ₀ , n, and X ₀ indicating the particle generation information on the manufacturing line on which the semiconductor memory device whose yield is to be predicted is manufactured. Read from 106. The foreign particle size distribution parameters D ₀ , n, and X ₀ are data received from the operator via the input device. In the present embodiment, as shown in FIG. 4, a conventionally known foreign particle size distribution function f (X) = D ₀ · (n -1) .X ₀
^{Using n−1} · X ⁻ⁿ , the particle size distribution of the foreign matter is determined. However, it is desirable that the minimum foreign matter size X ₀ is set to a value smaller than the minimum inter-wiring dimension (minimum space) in the layout data. The distribution variable n of the particle size of the foreign matter is determined in advance based on the inspection result actually measured by the foreign matter inspection device or the appearance inspection device on the production line. Random foreign matter density D
₀ (unit: pieces / cm ² ) represents a total value of the density of foreign matters having a size equal to or _larger than the minimum foreign matter size X ₀ , and is a predetermined value based on an inspection result actually measured on a production line.

Next, in step 3, the CPU 105
Reads the calculation conditions pmax, Xmax, and the like used for the critical area analysis from the storage unit 104. These calculation conditions are conditions received from the operator via the input device 100. As calculation conditions, the total number of dropped foreign substances pma that defines the maximum number of foreign substances to be dropped on the layout
x, a maximum foreign substance size Xmax that defines the maximum size of the foreign substance to be dropped, a foreign substance size increment dX that defines a step of the size of the foreign substance to be dropped, a foreign substance polygon shape when the foreign substance shape is a regular polygon, and the like. In this embodiment, each layer is divided into regions, and critical area analysis is performed for each region. Here, each area is sequentially numbered with a positive integer starting from 1, and this number is called an analysis level. Therefore, the calculation conditions used for critical area analysis include:
A table as shown in FIG. 5 for associating the coordinates of the area determined by the operator with the serial numbers (analysis levels) assigned to the area is included. This table also
This is received from the operator via the input device 100. In the present embodiment, the analysis level 1 includes the area (coordinates (0, 200) and (4100, 290) including the word lines, data lines, and power supply lines of the line numbers 12, 14, and 16 in the M1 layer.
0) and analysis level 2
Is the area of the peripheral circuit 3d (coordinates (0, 0) and (410
The analysis level 3 is the area of the peripheral circuit 3e (coordinates (4100, 0)).
And (4350, 2900). Analysis levels 4 to 6 are areas of the M2 layer.

Next, in step 4, S = 1 is set as an initial value of the analysis level S in order to perform subsequent critical area analysis in order from the analysis level 1 region.
Then, the minimum foreign matter size X ₀ read in step 2 is set as an initial value of the foreign matter size X to be dropped into the area (step 5). Also, p = 1 is set as the initial value of the foreign substance number p assigned to the foreign substance in order to count the number of foreign substances dropped in step 8 (step 6).

Next, in step 7, the coordinates for dropping the foreign substance of the foreign substance number p are determined in the area of the analysis level S.
Specifically, a random number is generated by a predetermined random number generation function, and the coordinates in the area of the analysis level S are calculated.

Next, in step 10, the coordinates set in step 7, it is assumed to have dropped foreign matter size X = X _0, determines whether the wiring dropped foreign matter can be short (FIG. 6 ( a), (b)). As in the conventional critical area analysis, the determination as to whether or not to short-circuit is based on whether the shape of the dropped foreign matter and the shape of the wiring are taken as a two-dimensional figure, and whether or not a superimposed portion of the foreign matter and the wiring figure is detected is determined. Can be calculated. Then, in the next step 11, it is determined whether or not this overlapping portion exists for a plurality of wirings,
It can be determined whether or not the wires are short-circuited by a foreign substance. In step 10, the shape of the foreign substance to be dropped is higher in calculation accuracy as the shape is closer to a circle, but the calculation time is longer.
An approximate shape such as an octagon is used. In the present embodiment,
The polygon designated by the operator and read in step 3 is used. However, in FIG. 6B, the shape of the foreign material is indicated by a circle for convenience of illustration.

Further, in the present embodiment, when determining in step 10 whether or not a short circuit has occurred, the type of wiring that has short-circuited to foreign matter is determined. As a result, in step 11, the occurrence of a short circuit is counted for each of two or more types of wiring that are short-circuited via a foreign substance, that is, for each short mode. In order to realize this, in step 10, a table as shown in FIG. 6A is created, and the types of wiring obtained from the layout data (word: W, data: D, power supply: P) are defined.
And the occurrence of a short between the foreign matter and the wiring is determined by calculation for each type of wiring, and as a result, the case where the foreign matter and the wiring are short-circuited is 1 (for example, the case where the foreign matter and the word line are short-circuited. , W = 1), otherwise 0 and fill the table of FIG. 6 (a).

In step 11, it is determined whether or not the foreign matter of the foreign matter number in step 6 shorts two or more wires.
Judgment is made from the table of FIG. 6A, and if a short circuit occurs, it is counted as a short foreign object. This determination and counting are performed for each short mode. Specifically, in the table of FIG.
If the data D is 1 and the power supply P is 0, it can be determined that the foreign object is in the short mode in which only the word line and the data line are short-circuited.
Count as _WD . Similarly, in the short mode in which the word line and the power supply line are short-circuited, the short foreign matter count a
_{In the} short mode in which the data line and the power supply line are short-circuited, it is counted as the number of short foreign particles _aDP . In the short mode in which the word line, the data line, and the power supply line are short-circuited, the number is determined as the number of short foreign particles a _WDP .

In steps 7 to 11 described above, the total number of foreign substances dropped is determined by the total number of dropped foreign substances pmax read in step 3.
Is repeated while increasing the foreign substance number one by one until the number of the foreign substances is reached. Thus, the area of the analysis level S that set in step 4, the short number of foreign matters a _WD mode each of the case where a foreign matter size X of the foreign matter was determined in step 5. The total number pmax is number dropped, a _WP, a _DP, a _WDP can be determined.

Next, proceeding to step 14, the fatal probability in the foreign matter size X is calculated for each short mode. The fatal probability can be obtained by dividing the number of short foreign substances counted in step 11 by the total number of dropped foreign substances. More specifically, for the foreign matter size X, the fatal probability G _WD of the short mode in which only the word line and the data line are short-circuited can be obtained by G _WD = a _WD / pmax. Similarly, the critical probability G _WP of the short mode in which only the word line and the power supply line are short-circuited is G _WP = a
_WP / pmax, which can be determined by the short-circuit probability G in which only the data line and the power supply line are short-circuited.
_DP can be obtained by G _DP = a _DP / pmax,
The fatal probability G _WDP of the short mode in which the word line, the data line, and the power supply line are short-circuited is G _WDP = a _WDP / p
max.

The above Steps 6 to 14 are performed according to the foreign matter size X
Are repeated until the foreign substance size X reaches the maximum foreign substance size Xmax while increasing the size by the size increment dX received in step 3 (steps 15 and 16). By plotting the obtained lethal probabilities Gi (where i represents the type of the short mode) as shown in FIG. 7, a lethal probability distribution Gi showing a correlation between the lethal probability Gi and the foreign matter size X is obtained.
(X) is obtained for each short mode.

Next, in steps 17 and 18, the show
The mortality rate KRi is obtained for each mode. The above lethal probability G
i (X) is pmax foreign substances predetermined for each particle size X
The probability of a short circuit occurring when
Fatality rate considering the particle size distribution function f (x) of the production line
Find KRi. The fatality rate has been known
Foreign matter particle size distribution F (X) and lethal probability distribution
It is expressed by the area obtained by integrating the product of the number Gi (X) and X.
You. However, the standardized particle size distribution F (X) is defined as F
(X) = (particle size distribution f (X)) / (total particle size D)₀)
Is a function represented by In the present embodiment, FIG.
As shown in the figure, the fatality rate is calculated for each short mode, and
For example, a short circuit in which only the word line and data line are short-circuited
Mortality rate KR_WDIs F (X) · G_WD(X) to X₀Or
Determined by integrating up to Similarly, word line
And the critical rate K of the short mode where only the power line is shorted
R _WP(X) is F (X) · G_WP(X) to X₀From to
Determined by integration. Only the data and power lines are
Short mode fatality rate KR_DP(X) is F
(X) · G_DP(X) to X₀By integrating from to
Request. Word line, data line and power line show
Critical rate KR for short mode_WDP(X) is F
(X) · G_WDP(X) to X₀By integrating from to
Request. In the present embodiment, the foreign matter size X is
Gi (X) is calculated by increasing the step width dX.
Gi (X) is not continuous for X
Value. Therefore, the standardized foreign particle size distribution F
(X) and the product of the fatal probability distribution Gi (X)
Since integration is not possible, the trapezoidal rule
It is executed by using numerical integration such as or Simpson's rule.

In steps 5 to 18 described above, the mortality rate KRi (where i indicates the type of the short mode) is obtained for the area of the analysis level S = 1 determined in step 4. In steps 19 and 20, steps 5 to 18 are repeated for each analysis level, so that the fatality rate KRi is obtained for each analysis level.

The analysis level S = 2, 3, 5, 6,.
In the areas of the peripheral circuits 3d and 3e, such as..., There is no rescue circuit and the classification of the short mode is unnecessary. Therefore, in steps 10, 11, 14, and 18, the classification of the short mode is not performed. , The number of short foreign substances, the probability of death, and the rate of death.

Next, in steps 21 to 24, the yield is calculated using the mortality rate KRi obtained in steps 5 to 18. At the time of the yield calculation, by reflecting the fatality rate for each short mode and the rescue method shown in FIG. 9, it is possible to accurately predict the rescue yield of the product (= the yield after rescue).

First, in step 21, conditions and parameter values used for the yield calculation after this step are read from the storage units 104 and 106. Specifically, FIG.
And the RA included in the RAM section 3a.
The number N of sets of M3, the number m1 of sets of relief circuits (A) 3b for short-circuit relief of word lines and data lines, the number m2 of sets of relief circuits (B) 3c for short-circuit relief of data lines and power supply lines, and manufacturing lines read random foreign substance density D _0, RAM 3 of a set of area a, the area of the peripheral circuit 3d a _alpha, the area a _beta of the peripheral circuit 3e.

Next, at step 22, the yield Yi (i indicates the short mode) for each analysis mode for each short mode is calculated. For this calculation, the conditions and parameters read in step 21 and the mortality rate KRi for each short mode for each analysis level obtained in steps 1 to 20 are used. Numerical expressions used for the yield calculation are shown in FIG. Yield of repairable short mode, i.e. the yield Y _DP short mode and the yield Y _WD and the data lines and the power supply line of the short mode in which the word lines and data lines are short-circuited is short, the formula (1),
It can be expressed using a binomial distribution as shown in equation (2). In addition, the yield of short mode where relief is impossible,
That is, the yield Y _{WP of the} short mode in which the word line and the power supply line are short-circuited and the yield Y _WDP of the short mode in which the word line, the data line and the power supply line are short-circuited are as shown in Expressions (3) and (4). Can be simply expressed by Poisson's equation. Equations (3) and (4) are equivalent to equations (1) and (2) with the number of relief circuits m1 and m2 = 0. The yields Y _WD , Y _DP , Y _WP , and Y _WDP for each of the short modes obtained by this calculation are _expressed by Equation (5)
Thus, the yield Y _S (where S indicates the analysis level) is obtained for the analysis level region.

The analysis level 2, 3, 5, 6, etc.
Analysis level that does not classify
The yield is calculated using equations (6) and (7) in FIG.
You. That is, the analysis level 2 which is the area of the peripheral circuit 3d
Yield about_TwoIs the analysis record obtained in step 18.
Fatal rate KR about Bell 2_αAnd read in step 21
Area A of embedded peripheral circuit 3d_αAnd random foreign matter density
D₀And can be obtained by Expression (6). As well
The analysis level for the analysis level 3 which is the area of the peripheral circuit 3e
Yield Y_ThreeIs for the analysis level 3 obtained in step 18.
Mortality rate KR _βAnd the surroundings read in step 21
Area A of circuit 3e_βAnd random foreign matter density D₀Using
Can be obtained by the equation (7).

In the next step 23,
Yield Y for all determined analysis levels S_SProduct
Y₁・ Y_Two・ Y_Three... by seeking semiconductor memos
The yield Y of the entire chip of the redevice is calculated. Calculate
The yield Y of the entire semiconductor memory device chip
Is output from the output device 107 in step 24 of FIG. In addition,
In step 23, as shown in FIG. 11, each layer (M1 layer,
Yield Y for each M2 layer, M3 layer ...)_M1, Y_M2, Y_M3
..., and their product Y_M1・ Y_M2・ Y _M3・ ・
· By calculating the chip of the semiconductor memory device
A configuration in which the overall yield Y is calculated may be employed.
In this case, in step 24, if only the overall yield Y is
Yield for each layer_M1, Y_M2, Y_M3Output
The operator can be notified.

As described above, the yield prediction system of the present embodiment obtains the fatality rate for each short mode. Therefore, even if the rescue method differs for each short mode, it is necessary to accurately predict the yield. Can be. In addition, since the Monte Carlo method is used to determine the fatality rate, the versatility is high and the calculation speed is high. Therefore, the yield can be predicted quickly and accurately by classifying each short mode. Therefore, the product yield can be predicted before manufacturing at the stage when the layout is determined in the layout design, so that it is possible to know whether or not a desired yield can be achieved with the layout. Therefore, the manufacturing cost can be specifically calculated from the yield, and it can be determined whether the manufacturing can be performed at the required cost. If the layout does not achieve the required cost, the design of the layout is changed. This will be specifically described below.

When the yield prediction system of the present embodiment is used, the design and manufacturing procedure of a semiconductor memory device can be as shown in FIG. 12, for example. First, a preliminary design such as a device design, a circuit design, a floor plan, and a circuit verification is performed by a conventional design procedure, and then a layout design is performed (steps 121 and 122). After the layout is determined, layout design verification is performed as necessary (step 123). When the layout design is completed, the area of one chip is determined, so that the number of chips obtained per wafer can be calculated (step 124). on the other hand,
When the layout design is completed, the yield of the chip can be calculated by the yield prediction system of the present embodiment described above (step 125). Accordingly, the unit cost per chip can be calculated by dividing the cost per wafer by the product of the number of obtained chips and the yield (step 12).
6). The cost of this chip is compared with the chip cost of the budget in the product plan (step 127), and if the budget is achieved, the production line is actually operated to manufacture the product (step 128). If you haven't reached your budget,
The cause of the rise in cost is extracted. (1) The relief circuits 3b and 3c are added if the relief yield of the RAM unit 3a is low (step 129), and (2) the peripheral circuits 3d and 3e are peripheral if the yield is high. The design rules of the circuits 3d and 3e are changed (step 130). (3) If the yield impact of a part of the RAM unit 3a in the short mode is high, the design of the cell structure itself of the RAM 3 is changed (step 131). Can be improved. By performing steps 123 to 127 again after the layout improvement, the effect of the layout improvement can be quantitatively confirmed.

As described above, by designing a semiconductor memory device using the yield prediction system of the present embodiment, it is possible to determine whether or not design improvement is necessary before the start of manufacturing, and to determine the factors affecting the yield. Can be quantitatively known. Further, by calculating the yield again after the layout improvement, the effect of the layout improvement can be quantitatively known. As a result, it is not necessary to improve the layout for the purpose of improving the yield after once manufacturing, unlike the conventional case, so that the manufacturing cost per chip can be minimized and the semiconductor memory device can be manufactured quickly. .

In the above-described yield prediction system of the present embodiment, a case has been described where one RAM 3 becomes defective due to one foreign substance.
Two RAMs when dropped over AM3
3 may be defective. In this case, the relief circuit 3b,
It is necessary to rescue using two sets of 3c. To calculate the yield accurately taking this into account,
The short mode has a configuration in which a double mode in which two RAMs 3 are defective and a single mode in which only one cell is defective are separated in advance, and the fatalities are calculated respectively. This can be achieved by adding information such as numbers to the layout data so that the individual RAMs 3 can recognize them.

In the present embodiment, the yield is predicted for a memory device including the RAM section 3a as a semiconductor memory device, but the prediction target is not limited to this. For example, a system LS having a RAM
It is also possible to predict the yield of semiconductor memory devices such as I.

In the yield prediction system of the present embodiment, the yield is predicted only when the cause of the defect is a short circuit caused by a foreign substance. However, even when the failure is caused by a disconnection caused by a foreign substance, the present embodiment is also applicable. Yield prediction is possible with almost the same configuration as the prediction system of the embodiment. Further, in the above-described embodiment, in steps 6 to 13 in performing the critical area analysis, the foreign matter is dropped until the predetermined maximum number of dropped foreign substances (pmax) is reached. It can also be configured. For example, every time a foreign object is dropped, the fatal probability of step 14 is obtained,
A change in the value of the fatal probability is examined, and when it is confirmed that the fatal probability has converged to a specific value, the foreign object dropping is terminated, and the fatal probability can be set as the fatal probability of a foreign material of that size. . In this case, since the foreign matter is dropped until the fatal probability converges, the fatal probability can be obtained with high accuracy, and the calculation amount is increased by setting an unnecessarily large value as the maximum number of foreign matter (pmax). There is an advantage that it can be prevented.

In the above-described embodiment, step 2
2 and the peripheral circuit 3 of the RAM 3 used for calculating the yield
d, an area of 3e A _alpha, as A _beta, but using the values received via the input device 100 from the operator, the area A from the layout data received from the operator, A
It is also possible to calculate _α and _Aβ and use the values.

[0050]

As described above, according to the present invention,
Provided is a yield prediction system capable of practically predicting the yield by using the Monte Carlo method for a semiconductor memory device having a relief circuit for relieving a defective portion while considering whether or not the rescue can be performed depending on the type of a defect that occurs. can do.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a rough processing flow of a yield prediction system according to an embodiment of the present invention;

FIG. 2 is a flowchart showing a flow of a yield prediction process of the yield prediction system according to the embodiment of the present invention;

FIG. 3A shows a semiconductor memory device to be predicted by a yield prediction system according to an embodiment of the present invention;
FIG. 5B is a top view of the M1 layer, and FIG. 6B is an explanatory diagram showing layout data received from an operator.

FIG. 4 is a graph showing a particle size distribution function f (X) used in the yield prediction system according to the embodiment of the present invention.

FIG. 5 is an explanatory diagram showing a relationship between an analysis level received from an operator and its coordinates in the yield prediction system according to the embodiment of the present invention;

6A and 6B are explanatory diagrams illustrating (a) data of foreign substances dropped by critical area analysis by Monte Carlo method, coordinates thereof, and presence / absence of short-circuit with wiring in the yield prediction system according to the embodiment of the present invention; (B) Explanatory drawing which shows the foreign substance dropped by the critical area analysis by the Monte Carlo method, and a layout.

FIG. 7 is a diagram illustrating a yield prediction system according to an embodiment of the present invention.
9 is a graph showing the relationship between (X) and the foreign matter size X for each short mode.

FIG. 8 is an explanatory diagram showing a method of calculating a fatality rate KRi from a fatality probability Gi (X) and a normalized foreign particle size distribution function F (X) in the yield prediction system according to one embodiment of the present invention.

FIG. 9 is an explanatory diagram showing a rescue method received from an operator in the yield prediction system according to the embodiment of the present invention.

FIG. 10 is a diagram illustrating a yield prediction system according to an embodiment of the present invention.
Explanatory view showing a formula for determining the yield Y _S from Ri.

[11] In the yield prediction system of an embodiment of the present invention, explanatory view showing formulas and a formula for obtaining the chip yield Y from each layer of the yield determined the yield of each layer from the yield Y _S per analysis level.

FIG. 12 is a flowchart showing a method for designing and manufacturing a semiconductor memory device using prediction results of the yield prediction system according to one embodiment of the present invention.

FIG. 13 is a block diagram showing a configuration of a yield prediction system according to one embodiment of the present invention.

[Explanation of symbols]

100: input device, 101: network, 1
02, 104, 106 ... data storage unit, 103 ...
· Program storage unit, 105 ··· CPU, 107 · · ·
-Output device.

Claims (10)

[Claims] 1. A yield prediction system for a semiconductor device, comprising: a plurality of types of wiring; and at least one type of rescue circuit for relieving a defect generated in the wiring, wherein the system predicts a yield of the semiconductor device to be predicted. A defect occurrence ratio calculating means for randomly dropping a plurality of foreign objects at random and calculating a ratio of foreign objects which cause a defect in the wiring of the semiconductor device among the foreign objects; and And a yield calculating means for calculating a yield of the semiconductor device by using the number of foreign substances in the manufacturing line and the ratio, wherein the defect occurrence ratio calculating means comprises: Finding the ratio, the yield calculation means,
A yield prediction system, wherein after calculating the yield for each type of defect, the yield of the semiconductor device is determined by calculating the product of the yield for each type of defect. 2. The yield predicting system according to claim 1, wherein said ratio determined by said defect occurrence ratio calculating means is:
The ratio at which two or more of the wirings are short-circuited by the foreign matter, and the type of the predetermined defect is
A yield prediction system, which is a combination of the short-circuited wirings. 3. A yield predicting system according to claim 1, wherein said yield calculating means is predetermined when calculating the yield for the types of defects that can be rescued by the rescue circuit among the types of defects. Using a first type of mathematical expression and calculating the yield for the type of a defect that cannot be remedied by the rescue circuit, using a predetermined second type of mathematical expression. system. 4. The yield predicting system according to claim 1, wherein said first type of mathematical expression used by said yield calculating means includes, for each type of said defect, said relief circuit used for relieving said defect. A yield prediction system comprising a number of circuits. 5. The yield prediction system according to claim 1, wherein data indicating a layout of the wiring of the semiconductor device to be predicted and data of the number of foreign particles on the manufacturing line are received from outside. Means for outputting the yield calculated by the yield calculation means to the outside. 6. A method for predicting the yield of a semiconductor device including a plurality of types of wirings and one or more types of rescue circuits for relieving defects occurring in the wirings, the method comprising: A first step of randomly dropping a plurality of foreign substances at random and calculating a ratio of foreign substances that cause a defect in the wiring among the foreign substances by calculation;
And a second step of calculating the yield of the semiconductor device by using the number of foreign substances in the manufacturing line of the semiconductor device previously determined and the ratio. Calculating the yield for each of the types of defects, calculating the yield for each type of the defects, and then calculating the product of the yield for each type of the defects, thereby obtaining the yield of the semiconductor device. A yield prediction method characterized by determining the following. 7. The yield predicting method according to claim 6, wherein in the first step, the ratio is obtained by including the wiring of the relief circuit in the wiring. 8. A method for designing a semiconductor device, comprising: a plurality of types of wiring; and one or more types of rescue circuits for relieving a defect generated in the wiring, wherein: a layout of the wiring of the semiconductor device; A first step of designing the type and the number of circuits of the relief circuit; and using data indicating the layout, randomly dropping a plurality of foreign substances on the semiconductor device at random,
A second step of calculating, by calculation, a percentage of foreign matter that causes a defect in the wiring among the foreign matters, for each of the predetermined types of the defect; Calculating the yield for each type of the defect using the ratio, the type and the number of the relief circuits, and then calculating the product of the yield for each type of the defect, thereby reducing the yield of the semiconductor device. A third step of calculating; a fourth step of calculating a manufacturing cost of the semiconductor device using the yield obtained in the third step; and a manufacturing method in which the manufacturing cost obtained in the fourth step is determined in advance. A fifth step of redesigning at least one of the wiring layout and the number of relief circuits if the cost is larger than the cost. Design method of a semiconductor device according to claim. 9. A recording medium on which is recorded a semiconductor device yield prediction program including a plurality of types of wiring and one or more types of rescue circuits for relieving a defect generated in the wiring, wherein the program is A first step of randomly dropping a plurality of foreign particles on the semiconductor device to be predicted and randomly calculating a ratio of foreign particles that cause a defect in the wiring among the foreign particles;
And a second step of calculating a yield of the semiconductor device using the number of foreign substances in the semiconductor device manufacturing line obtained in advance and the ratio, the first step being: In the above, the ratio is determined for each type of the predetermined defect, and the second step calculates the yield for each type of the defect, and then obtains the product of the yield for each type of the defect. A recording medium on which a yield prediction program for determining a yield of a semiconductor device is recorded. 10. A yield prediction program for a semiconductor device including a plurality of types of wiring and one or more types of rescue circuits for relieving a defect generated in the wiring, wherein the program predicts the yield of the semiconductor device. A first step of randomly dropping a plurality of foreign substances at random and calculating a ratio of foreign substances that cause a defect in the wiring among the foreign substances by calculation;
And a second step of calculating the yield of the semiconductor device by using the number of foreign substances in the semiconductor device manufacturing line determined in advance and the ratio, wherein the first step includes a predetermined step. Determining the ratio for each type of the defect, calculating the yield for each type of the defect, and then calculating the product of the yield for each type of the defect, thereby reducing the yield of the semiconductor device. A yield prediction program characterized by what you want.