JP2002199281A - Image processing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processing apparatus that is suitably used by an electronic camera utilizing a CMOS array for the reduction of the cost and for downsizing the circuit scale. SOLUTION: The CMOS array 14 is logically divided in a row direction so that the number of elements is the same in a direction of rows of each of division areas DE0-DE7. The image processing unit is provided with line memories LM1-LM9 that have a storage capacity depending on number of the elements in the row direction of the division areas DE0-DE7 and are electrically in cascade connection, and a line memory controller 24 that stores photographed image data detected by an image sensor 16 to the line memories LM1-LM9. The line memory controller 24 allows the image sensor 16 to detect image data in the row direction from the CMOS array 14 by each of the division areas DE0-DE7 and sequentially stores the detected image data to the line memories LM1-LM9 according to the first-in first-out method.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for processing image data detected from a photoelectric conversion element array, and more particularly to an electronic camera such as a digital camera.
S-device-based photoelectric conversion element array (hereinafter, CM
It is called an OS array. The present invention relates to an image processing apparatus for processing image data detected from the above. More specifically, the present invention relates to an image processing apparatus suitable for reducing the cost and reducing the circuit size of an electronic camera using a CMOS array.

[0002]

2. Description of the Related Art In recent years, digital recording type electronic cameras such as digital cameras and digital video cameras have become widespread. The electronic camera includes, for example, a release switch for inputting a shooting timing and a CCD (Charge C).
Oupled Device), an image capturing unit having a photoelectric conversion element array (hereinafter, referred to as a CCD array), an image processing unit for processing image data captured by the image capturing unit, and an LCD (LCD) for displaying a captured image. Liquid Crystal Displ
ay) and an image memory for storing the image data processed by the image processing unit. The captured image from the image processing unit is displayed on the LCD, and the image data from the image processing unit is input at the input timing of the release switch. Capture
The captured image data is compressed in a JPEG format or the like and stored in an image memory.

[0003] The image capture unit includes a sensor array in which a plurality of sensors that output electric signals corresponding to the amount of incident light are two-dimensionally arranged in a row direction and a column direction, and detects image data in the row direction from the sensor array. And a CCD array. The image processing unit includes a plurality of line memories that have a storage capacity of the number of bits corresponding to the number of elements in the row direction of the CCD array and are electrically cascaded, a line memory controller that controls the line memories, and a line memory controller. And an image processing circuit for processing image data.

Next, a line memory, a line memory controller,
The configuration of the roller and the image processing circuit will be described with reference to FIG.
This will be described in detail. FIG. 6 shows a line memory and a line memory.
To explain the configuration of the controller and image processing circuit
FIG. Each line memory LM₁~ LM₉Is a CCD camera
When the number of elements in the row direction of a ray is 1800, for example,
Has a storage capacity of 1800 × predetermined bits.
As shown in FIG.
ing. Each line memory LM ₁~ LM₉Is at its end (b
_n: Indicates the n-th storage area from the head. ) To enter data
And the opposite end (b₀) Is the data output side,
The data output side of the former stage and the data input side of the latter stage are electrically connected.
It is connected. Therefore, the line memory controller
When the camera has shifted the image data,
Memory LM_TwoB_nIs stored in the line memory L
M_TwoB_n-1And the line memory LM₁B₀Image of
The data is then stored in the line memory LM_TwoB_nIs stored in

[0005] The line memory control is performed by moving the image data of the line memories LM _{1 to} LM ₉ from the first stage to the second stage.
One shift, store the image data detected by the image sensor to b _n of the line memory LM _1, has such a series of operations to perform until scanning all CCD image sensor. To detect image data from a CCD array, the CCD array must be moved in a row direction (eg, from left to right).
, And scanning to the next lower row after scanning to the right end of the row is repeated up to the rightmost CCD of the lowermost row.

[0006] The image processing circuit 26 includes a line memory LM
Specific area of ₁ to L m ₉ (e.g., b ₀ ~b ₈₎ to form a window 26a captures image data of, based on the image data in the window 26a, the processing target image data positioned at the center of the window 26a It is supposed to. The processing by the image processing circuit 26 includes a two-dimensional low-pass filter processing for removing a noise component in the image, and a high-pass filter processing for enhancing the edge of the image so as to sharpen the image. For example, an example of image processing using LM ₁ , LM ₂ , and LM ₃ as shown in FIG. 7 will be described.

In the window 26a, the image data P₀₀~ P₀₆
Is the image data P on the first line._Ten~ P ₁₆Is on the second line
Image data P₂₀~ P₂₆Is on the third line and the target image data
Is the center of P₁₃Each image data
Weight for the image data P₀₀~ P₀₆about
Are "0", "1", "2", "2", "2",
“1” and “0”, and the image data P_Ten~ P₁₆about
"1", "2", "3", "4", "3",
“2” and “1”, and the image data P₀₀~ P₀₆about
"0", "1", "2", "2", "2",
If “1” and “0” are set, the target image data P₁₃Phil
The data output is calculated by the following equation (1). In the following equation (1)
Here, each image data P₀₀~ P₂₆Is for each RGB component
The magnitude of the luminance is represented by a numerical value. P₁₃= ｛P₀₁+ P₀₅+ P_Ten+ P₁₆+ P_{twenty one}+ P_{twenty five} + 2 × (P₀₂+ P₀₃+ P₀₄+ P₁₁+ P₁₅+ P_{twenty two}+ P_{twenty three}+ P_{twenty four}+) + 3 × (P₁₂+ P₁₄) + 4 × P₁₃｝ / 32… (1)

[0008]

As described above, in the conventional image processing section, in order for the image processing circuit 26 to process the target image data, not only the target image data but also the peripheral image data is processed. requires a, the image data held by providing the line memories LM ₁ to L m _9, and one by one processing image data with a window 26a.

In order to detect image data from the CCD array due to the nature of the CCD, the CCD array is scanned in the row direction from the left end, and once the right end of the row is scanned, the line is shifted to the next lower row. Scan the rightmost CCD in the bottom row.
Need to repeat until: That is, the image data cannot be detected by any method other than the above-described scanning procedure, and scanning for detection is limited to a certain procedure. Therefore, to form and window 26a in accordance with the above scan procedure, as the storage capacity of the line memories LM ₁ ~LM _9, C
At a minimum, a storage capacity of the number of bits corresponding to the number of elements in the row direction of the CD array is required. Line memories LM _{1 to} LM ₉
This is because if the storage capacity is smaller than this, the window 26a cannot be formed by the above scanning procedure.

[0010] However, recent electronic cameras are CC
D has a very high resolution of 3 million to 4 million pixels, so the line memory LM
The storage capacity of _{1 to} LM ₉ must also be increased. For example, in the case of an electronic camera with 2 million pixels, the number of elements in the row direction of the CCD array is about 1800, so that the storage capacity of each of the line memories LM _{1 to} LM ₉ is 1800 × predetermined bit storage. A minimum capacity is required. As the storage capacity of the line memories LM _{1 to} LM ₉ increases, not only does the price increase according to the storage capacity, causing an increase in cost, but also the occupied area of the substrate increases, making it difficult to reduce the size.

Recently, the use of CMOS arrays has been reviewed, and attempts have been made to adopt them in electronic cameras. The CMOS array is inferior in image quality as compared with the CCD array, but is superior in that image data can be detected in an arbitrary scanning direction from the CMOS array. Although CMOS arrays are a technology that is as old as CCD arrays, CCD arrays are mainly used because the cost was not so great in product development aimed at improving image quality. As a result, adoption of a CMOS array has decreased. However, the image quality, which was disadvantageous to the CMOS array, has been increased due to the recent increase in resolution.
This is now being reviewed, as it is almost inferior to the array.

Accordingly, the present invention has been made in view of such unresolved problems of the prior art, and aims to reduce the cost and reduce the circuit size of an electronic camera using a CMOS array. It is an object of the present invention to provide an image processing device suitable for downsizing.

[0013]

According to a first aspect of the present invention, there is provided an image processing apparatus comprising: a plurality of photoelectric conversion elements for outputting an electric signal corresponding to an amount of incident light; An apparatus to be applied to an image capturing apparatus including a photoelectric conversion element array two-dimensionally arranged in a column direction and image data detecting means capable of detecting image data from the photoelectric conversion element array in an arbitrary scanning direction. The photoelectric conversion element array is logically divided in the column direction so that the number of photoelectric conversion elements in the row direction in each of the divided areas is the same, and the photoelectric conversion elements in the row direction in the divided areas are divided. A plurality of line memories having a storage capacity according to the number and electrically cascaded, and image data processing means for processing image data detected by the image data detection means,
The image data processing means detects image data in the row direction from the photoelectric conversion element array by the image data detection means for each of the divided areas, and sequentially stores the detected image data in the line memory in a first-in first-out manner. It is supposed to.

With such a configuration, image data is detected in the row direction from the photoelectric conversion element array by the image data detecting means for each of the divided areas by the image data processing means, and the detected image data is first-in first-out. Are sequentially stored in the line memory. Here, the cascade connection of the line memories means that, for example, when the end of each line memory is the data input side and the opposite end is the data output side, the data output side of the preceding stage and the data input side of the subsequent stage are connected. Refers to electrical connection.

The first-in first-out method refers to a storage method in which image data stored first in the line memory is taken out or deleted from the line memory earlier than image data stored later. The image data of the connected line memory may be shifted from the previous stage to the subsequent stage, and the image data may be stored at the end of the foremost line memory.

The image processing apparatus according to a second aspect of the present invention is the image processing apparatus according to the first aspect, further comprising a boundary detecting means for detecting a boundary in the column direction of the divided area, When the boundary is detected by the boundary detection unit, the processing unit saves the boundary image data corresponding to the boundary among the image data detected by the image data detection unit, and saves the boundary image saved in the adjacent divided area. Based on the data, of the image data detected by the image data detecting means, boundary image data corresponding to the boundary is processed.

With such a configuration, when the boundary is detected by the boundary detection means, the image data processing means
Among the image data detected by the image data detecting means, boundary image data corresponding to the boundary is saved. Further, when the boundary is detected by the boundary detecting means, if there is boundary image data evacuated for the adjacent segmented area, the boundary of the image data detected by the image data detecting means is determined based on the boundary image data. The corresponding boundary image data is processed.

Here, the image data processing means, based on the border image data evacuated for the adjacent divided areas,
It is only necessary to process boundary image data corresponding to the boundary among the image data detected by the image data detecting means.For example, when processing is performed on the current segmented area, the saved boundary image data is The image data detected by the image data detecting means may be added to the corresponding portion of the image data and stored in the line memory, or when performing image processing using a window based on the image data of the line memory, The saved boundary image data may be used.

According to a third aspect of the present invention, in the image processing apparatus according to any one of the first and second aspects, the photoelectric conversion element array is a CMO.
This uses an S device. With such a configuration, the image data detection unit performs, for each of the divided areas,
Image data can be detected from a photoelectric conversion element array using a CMOS device.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.
This will be described with reference to FIG. 1 to 4 illustrate the present invention.
It is a figure showing an embodiment of such an image processing device. This implementation
In the embodiment, an image processing apparatus according to the present invention is shown in FIG.
Thus, in an electronic camera using a CMOS array,
The CMOS array 12 is connected to each of the divided areas DE. ₀~ DE₇Whereabouts
Logical in the column direction so that the number of elements in each direction is the same
(In the example of FIG. 1, divided into eight equal parts).
, Each section area DE₀~ DE₇CMOS array
It is suitable for detecting and processing image data from
It was used.

First, an electronic camera 100 to which the present invention is applied
Will be described with reference to FIG. FIG. 2 is a block diagram showing the internal configuration of the electronic camera 100. As shown in FIG. 2, the electronic camera 100 includes an image capturing unit 10 for capturing a captured image as captured image data, and an image capturing unit 1
Image processing unit 2 that processes captured image data captured at 0
0 and the high resolution image from the image processing unit 20
Image but a conversion unit 30 that performs processing such as conversion into a displayable low resolution image, and a display unit 50 for displaying the low resolution image converted by the converting unit 30, corresponding to the boundary of the segmented region DE ₀ ~DE ₇ An external memory 60 temporarily stores boundary image data as data.

The image capturing unit 10 includes an optical lens 12 and a C
MOS array 14 and image sensor 1 capable of detecting photographed image data from CMOS array 14 in an arbitrary scanning direction
6. The CMOS array 14 is configured by two-dimensionally arranging a plurality of CMOS devices that output electric signals in accordance with the amount of incident light in the row direction and the column direction, and is connected to each pixel via the optical lens 12 disposed at the preceding stage. An optical image of a subject to be imaged is photoelectrically converted into an image signal (electric signal).

Although not shown, the image sensor 16 has a C
It has a MOS drive circuit and an A / D conversion circuit. The CMOS drive circuit supplies vertical and horizontal drive pulses to the CMOS array 14 and outputs an image signal photoelectrically converted by the CMOS array 14 to the A / D conversion circuit. The A / D conversion circuit samples the signal obtained by amplifying the image signal to a predetermined level at a predetermined timing, and outputs the sampled digital image data to the image processing unit 20.

The image processing unit 20 includes a plurality of line memories L
M₁~ LM₉A line memory group 22 composed of
The captured image data detected by the sensor 16 is stored in a line memory LM.
₁~ LM₉Line memory controller 24 to be stored in
And the line memory LM₁~ LM ₉Process captured image data
Image processing circuit 26 and line memory controller 2
4 that controls access to the external memory 60
An arbiter 28 is provided.

The line memory group 22 stores each of the divided areas DE.₀
~ DE₇Having a storage capacity corresponding to the number of elements in the row direction.
Number of line memories LM₁~ LM₉Consists of each line memo
Re-LM ₁~ LM₉Are electrically connected as shown in FIG.
Are cascaded. Each line memory LM₁~
LM₉Is at its end (b_n: The nth storage area from the top
Show. ) Is the data input side and the opposite end (b₀) Data
When the output side is set, the data output side of the previous stage and the data
Data input side. Therefore, la
In-memory controller 24 shifts captured image data
When the operation is performed, for example, the line memory LM_TwoB_nShooting
The image data is then stored in the line memory LM_TwoB_n-1Stored in
And the line memory LM₁B₀The captured image data of
Line memory LM_TwoB_nIs stored in

Next, the configuration of the line memory controller 24 will be described in detail with reference to FIG. FIG. 3 is a block diagram showing a configuration of the line memory controller 24. As shown in FIG. 3, the line memory controller 24 controls the detection data acquisition control signal 2 to the image sensor 16.
And right boundary detection circuit 24a for detecting the right boundary of the segmented region DE ₀ ~DE ₇ based on 4g, right boundary detection circuit 24
a boundary image data writing circuit 24b for writing boundary image data corresponding to the right boundary of the captured image data detected by the image sensor 16 based on the detection signal from the external memory 60 into the external memory 60; a left boundary detection circuit 24c that detects the left boundary of the segmented region DE ₀ ~DE ₇ based on the write control signal 24 g, boundaries retracted in divided areas of the left side based on the detection signal from the left boundary detection circuit 24c A boundary image data reading circuit 24d for reading image data from the external memory 60;
e, and a timing control circuit 24f that outputs a timing signal indicating an operation timing to the boundary image data reading circuit 24d and the control circuit 24e.

The control circuit 24e includes a timing control circuit 2
4f operates according to the timing signal from
And each segmented area DE₀~ DE₇For each area
In the CMOS array 14 in the row direction from the left end.
Scan, scan to the right end of the line and move to the line below
Scanning to the right end of the bottom line
In order to detect the photographed image data of the divided area more,
The image sensor 16 is controlled by the line memory LM.₁~ L
M₉Shifts the captured image data of
The captured image data detected by the image sensor 16.
Line memory LM ₁B_nIn a series of these operations
Until the image sensor 16 scans all the elements.
It has become.

Further, the control circuit 24e can store the boundary image data read by the boundary image data reading circuit 24d, in addition to the corresponding portion of the captured image data detected by the image sensor 16 to the line memory LM ₁ to L m ₉ It is made to let. That is, in the image processing circuit 26,
To properly process a predetermined number of photographed image data from the left end of the segment regions DE ₁ ~DE _7, as shown in FIG. 4, the left side partitioned area DE ₀ ~DE ₆ from the right end of the predetermined number since the captured image data is required, the right boundary detection circuit 24a and the boundary image data writing circuit 24b, the outside a predetermined number of photographed image data from the right end of the left side partition areas DE ₀ ~DE ₆ as the boundary image data Saved in the memory 60,
When reading the photographed image data at the left ends of the divided areas DE _{1 to} DE ₇ from the image sensor 16, the saved boundary image data is added to the read photographed image data and stored in the line memories LM _{1 to} LM ₉ . FIG. 4 is a diagram for explaining the significance of saving the boundary image data in the external memory 60.

The image processing circuit 26, as shown in FIG.
Specific region of the line memories LM ₁ ~LM ₉ (e.g., b ₀
To b ₈ ) to form the window 26 a, and based on the captured image data in the window 26 a, the window 26 a is formed.
Is processed at the center of the image data. The processing by the image processing circuit 60 includes, for example, a two-dimensional low-pass filter processing for removing a noise component in the image, and a high-pass filter processing for enhancing the edge portion of the image to make the image sharp.

On the other hand, returning to FIG.
A timing generation circuit 54 generates a timing signal indicating the timing of displaying an image on the display 52, and an LCD 52 displays an image in synchronization with the timing signal generated by the timing generation circuit 54. The conversion unit 30
A resolution conversion circuit 32 that converts captured image data, which is a high-resolution image processed by the image processing unit 20, to display image data, which is a low-resolution image that can be displayed by the LCD 52, and performs calculations and controls the entire system based on a control program. CPU 34, main memory 36 for storing image data, and image data writing circuit 3 for writing display image data converted by resolution conversion circuit 32 to main memory 36
8, an image data writing circuit 40 for writing the captured image data processed by the image processing unit 20 to the main memory 36, and an LCD 52 based on the display image data of the main memory 36.
A display control circuit 42 for controlling the display of an image on the LCD, and an access control circuit 44 for controlling access to the main memory 36. In addition, although not shown, a predetermined area has a ROM in which a control program of the CPU 34 is stored in advance, and the CPU 34 activates a predetermined program stored in the predetermined area of the ROM and operates according to the program. It has become.

The main memory 36 is composed of a RAM for storing data read from a ROM or the like and a calculation result required in a calculation process of the CPU 34. The RAM is used as a specific area for storing display image data. VRA
M37. The VRAM 37 includes a CPU 34,
The image data writing circuit 38 and the display control circuit 42 can access each independently.

The image data writing circuit 38 writes the display image data converted by the resolution conversion circuit 32 into the VRAM 43 in order to display the photographed image on the LCD 52 at a low resolution. When the release switch (not shown) is pressed, the image data writing circuit 40
34, the captured image data processed by the image processing unit 20 is stored in the main memory 36 in order to store the captured image at a high resolution in a predetermined area (an area other than the VRAM 37) of the main memory 36. The data is stored in the predetermined area.

The display control circuit 42 synchronizes with the timing signal generated by the timing generation circuit 54,
The display image data stored in the memory 7 is sequentially read from the head address, and the read display image data is converted into an image signal and output to the LCD 52. The access control circuit 48 is connected to the main memory 3 by the CPU 34, the image data writing circuits 38 and 40, or the display control circuit 42.
When there are a plurality of accesses to 6 at the same time, one of those accesses is permitted, and the other is waited until the permitted access is completed.
Only one access to the main memory 36 is always permitted. The same operation is performed not only when a plurality of accesses are made at the same time, but also when another access is made while accessing the main memory 36.

Next, the operation of the above embodiment will be described.
When a release switch (not shown) in the electronic camera 100 is pressed, a capture request is output to the image data writing circuit 40 by the CPU 34. When there is a capture request, the captured image is captured as captured image data from the CMOS array 14 by the image capturing unit 10, the captured image data is processed by the image processing unit 20, and the image data writing circuit 40 Thus, the processed captured image data is written to a predetermined area of the main memory 36. The captured image data written in the main memory 36 is further described in JP
It is compressed in the EG format or the like.

In the image processing section 20, the control circuit 24e controls the image sensor 16 for each of the divided areas DE _{0 to} DE ₇ so as to detect the photographed image data of the divided area. As a result, by the image sensor 16, for each partitioned region DE ₀ ~DE _7, C in the segmented region
The scanning in which the MOS array 14 is scanned in the row direction from the left end, and then scans to the right end of the row and shifts to the next lower row is repeated up to the right end of the lowermost row, and each divided area DE
Photographed image data of _{0 to} DE ₇ is detected.

On the other hand, the right boundary detection circuit 24a, the right boundary of the segmented region DE ₀ ~DE ₇ is detected, the boundary image data writing circuit 24b, an image sensor 16
The boundary image data corresponding to the right boundary among the photographed image data detected in step (1) is written to the external memory 60. Also,
The control circuit 24e, photographed image data of the line memory LM ₁ to L m ₉ is one shift toward the front to the rear stage,
Photographed image data detected by the image sensor 16 is stored in the b _n of the line memory LM _1. At this time, the left boundary detection circuit 24c, the left boundary of the segmented region DE ₀ ~DE ₇ is detected, the boundary image data reading circuit 24d, the boundary image data is retracted in the divided region to the left external The boundary image data read from the memory 60 and read by the boundary image data reading circuit 24d by the control circuit 24e is added to a corresponding portion of the photographed image data detected by the image sensor 16, and the line memory L
Stored in M _{1 to} LM ₉ .

The image processing circuit 26 takes in the photographic image data of a specific area of each of the line memories LM _{1 to} LM ₉ to form a window 26 a, and forms the window 26 a based on the photographic image data in the window 26 a. The target image data located at the center is processed. When a release switch (not shown) is not depressed and non-photographing is being performed, the following operation is performed to display a photographed image on the LCD 52 at a low resolution.

First, the image capturing section 10 captures a captured image as captured image data, the image processing section 20 processes the captured captured image data, and sends the processed captured image data to the resolution conversion circuit 32. Is output.
In the resolution conversion circuit 32, when the captured image data is input, the captured image data processed by the image processing unit 20 is converted into display image data that can be displayed on the LCD 52 at a predetermined conversion rate, and the image data writing circuit 38.

In the image data writing circuit 38, when display image data is input, the input display image data
It is written to AM37. Display image data is VRAM3
7, the display control circuit 42 synchronizes with the timing signal from the timing generation circuit 54 to
The display image data in the RAM 37 is sequentially read from the head address, and the read display image data is converted into an image signal and output to the LCD 52. With this, LCD
At 52, the captured image data captured by the image capturing unit 10 is converted into a displayable low-resolution image and displayed.

As described above, in the present embodiment, the CM
The OS array 14 is stored in each partitioned area DE. ₀~ DE₇In the row direction
Logically partition in the column direction so that the number of elements is the same.
Divided into each section area DE₀~ DE₇According to the number of elements in the row direction
With multiple storage capacity and electrically cascaded
Line memory LM₁~ LM₉And the image sensor 16
The detected photographed image data is stored in a line memory LM.₁~ LM₉To
A line memory controller 24 for storing the
The in-memory controller 24 controls each partitioned area DE₀~ D
E₇CMOS array by the image sensor 16
14, the image data is detected in the row direction, and the detected image data is detected.
Data on a first-in first-out basis in line memory LM₁~ LM₉To
They are stored sequentially.

As a result, even if the number of elements in the electronic camera 100 is increased and the resolution is increased, if the number of divided areas is increased accordingly, the line memories LM _{1 to} LM _{1 to} L
Without increasing the storage capacity of the M ₉ live. Therefore,
Compared with the related art, in the electronic camera 100 using the CMOS array 14, the cost can be reduced and the circuit size can be reduced.

Further, in the present embodiment, each divided area D
E₀~ DE₇Detection circuit 24 for detecting the boundary in the column direction of
a, 24c, and the line memory controller 24 includes:
Each of the divided areas DE is determined by the right boundary detection circuit 24a.₀~ DE₇of
When the right boundary is detected, the image sensor 16 detects the right boundary.
The boundary image data corresponding to the boundary
Data to the external memory 60, and the left boundary detection circuit 24c
By each section area DE ₀~ DE₇Detected left border of
When the boundary read by the boundary image data reading circuit 24d
Image data obtained by detecting the world image data with the image sensor 16
A line memory LM is added to a corresponding portion of the image data.₁
~ LM₉Is to be stored.

As a result, it is possible to appropriately process the photographed image data located near the boundary between the divided areas DE _{0 to} DE _7. Quality can be maintained. In the above embodiment, the CMOS array 14
Corresponding to the photoelectric conversion element array according to claim 1 or 3,
The image sensor 16 corresponds to the image data detecting means according to claim 1, and the line memory controller 24.
Corresponds to the image data processing means according to claim 1 or 2, and includes a right boundary detection circuit 24a and a left boundary detection circuit 24c.
Corresponds to the boundary detecting means described in claim 2.

[0044] In the above embodiment, a line memory controller 24, when detecting the left boundary of the segmented region DE ₀ ~DE ₇ by the left boundary detection circuit 24c is read by the boundary image data reading circuit 24d The boundary image data is added to the corresponding portion of the photographed image data detected by the image sensor 16 and the line memories LM _{1 to} LM
Was configured to store the M _9, not limited to this, the image processing circuit 26, upon detection of the left boundary of the segmented region DE ₀ ~DE _7, using the boundary image data in the external memory 60 Alternatively, it may be configured to process captured image data detected by the image sensor 16.

In the above embodiment, the external memory 60 is provided as the memory for storing the boundary image data. However, the present invention is not limited to this. The external memory 60 is not provided, and the memory for storing the boundary image data is used. The configuration may be such that the main memory 36 is also used. Further, in the above-described embodiment, as shown in FIG. 2, the image processing unit 20 converts the line image data detected by the image sensor 16 into a line memory group 22 including a plurality of line memories LM _{1 to} LM _9. A line memory controller 24 for storing the data in the memories LM _{1 to} LM ₉ and a line memory LM _{1 to} L
An image processing circuit 26 for processing the captured image data of the M _9,
The line memory controller 24 is configured with the memory arbiter 28 that controls access to the external memory 60. However, the present invention is not limited to this. In the case of a single-chip electronic camera, since color filters are used, color interpolation is not necessary. , And may be configured as shown in FIG. FIG. 5 is a diagram illustrating another embodiment of the image processing unit 20.

As shown in FIG. 5, the image processing unit 20 includes a line memory group 22 composed of a plurality of line memories LM _{1 to} LM ₉ and a line memory LM _{1 to} LM _{9 which} stores the image data detected by the image sensor 16. a line memory controller 24 to be stored in the line memory LM ₁ and an image processing circuit 26 for processing the captured image data to L m _9, line memory group 23 composed of a plurality of line memories LM ₁₀ to L m ₁₈
When a line memory controller 25 to store the captured image data processed by the image processing circuit 26 to the line memory LM ₁₀ to L m _18, an image processing circuit 27 for processing the captured image data of the line memory LM ₁₀ to L m _18, line The memory arbiter 28 controls access to the external memory 60 by the memory controller 24.

The image processing circuit 26 has a line memory LM ₁
Forming a window 26a fetches the captured image data to L m _9, on the basis of the photographic image data in the window 26a, the window 26a
Of the target image data located at the center of the image data. The image processing circuit 27 forms a window 26a fetches the captured image data of the line memory LM ₁₀ to L m _18, on the basis of the photographic image data in the window 26a, with respect to the target image data in the center of the window 26a Processing for removing noise is performed.

In the above-described embodiment, the line memory controller 24 scans the CMOS array 14 from the left end in the row direction in each of the partition areas DE _{0 to} DE ₇ , and scans the row. The image sensor 16 is configured to control the image sensor 16 so as to detect the captured image data of the segmented area by repeating the scanning of shifting to the next lower row after scanning to the right end, to the right end of the lowermost row. However, the present invention is not limited to this, and the image sensor 16 may be configured to perform such a detection operation independently without receiving control from others.

In the above embodiment, the line memory controller 24 includes the right boundary detection circuit 24a, the boundary image data writing circuit 24b, the left boundary detection circuit 24c,
The boundary image data reading circuit 24d, the control circuit 24e, and the timing control circuit 24f are used, but the present invention is not limited to this.
It may be configured to be realized by the processing executed by.
In this case, a program for realizing the function of the line memory controller 24 is stored in the ROM,
The U34 activates a predetermined program stored in a predetermined area of the ROM, and executes these processes according to the program. The present invention is not limited to this, and when executing processing for realizing the functions of the line memory controller 24, the program is read from a recording medium on which a program indicating these procedures is recorded, and is read into the main memory 36 and executed. It may be.

Here, the recording medium is a semiconductor storage medium such as a RAM or a ROM, a magnetic storage type storage medium such as an FD or HD, an optical reading type storage medium such as a CD, CDV, LD, or DVD, or a storage medium such as an MO. It is a magnetic storage type / optical readout type storage medium, and includes any storage medium that can be read by a computer irrespective of an electronic, magnetic, optical or other reading method.

Further, in the above embodiment, the image processing apparatus according to the present invention, the image processing apparatus according to the present invention,
As shown in FIG. 1, in the electronic camera using the CMOS array, the CMOS array 12 is divided into the respective divided areas DE _0.
ＤＥDE ₇ are logically divided in the column direction (equally eight in the example of FIG. 1) so that the numbers of elements in the row direction are all the same, and are divided by the image sensor 16 into each of the divided areas DE _{0 to} DE _7. Although the present invention has been applied to the case where image data is detected and processed from the CMOS array 12, the present invention is not limited to this, and can be applied to other cases without departing from the gist of the present invention.

[0052]

As described above, according to the image processing apparatus of the first to third aspects of the present invention, even if the number of elements in the electronic camera is increased and the resolution is increased, the division area is adjusted accordingly. If the number is increased, the storage capacity of the line memory does not need to be increased. Therefore, compared with the conventional case, it is possible to reduce the cost and reduce the circuit size of an electronic camera using a CMOS array. The effect that it can be obtained is obtained.

Further, according to the image processing apparatus of the second aspect of the present invention, since the image data located near the boundary of each divided area can be appropriately processed, the photoelectric conversion element array can be divided and divided. Even if the processing is performed in the unit of section, the effect that the quality of the image can be maintained to some extent can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining an outline of the present invention.

FIG. 2 is a block diagram showing an internal configuration of the electronic camera 100.

FIG. 3 is a block diagram showing a configuration of a line memory controller 24.

FIG. 4 is a diagram for explaining the significance of saving boundary image data in an external memory 60;

FIG. 5 is a diagram showing another embodiment of the image processing unit 20.

FIG. 6 is a diagram illustrating a configuration of a line memory, a line memory controller, and an image processing circuit.

FIG. 7 is a diagram for explaining an example of processing in the image processing circuit 24.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 electronic camera 10 image capture unit 14 CMOS array 16 image sensor 20 image processing unit 22, 23 line memory group 24, 25 line memory controller 24a right boundary detection circuit 24b boundary image data writing circuit 24c left boundary detection circuit 24d boundary image Data reading circuit 24e Control circuit 24f Timing control circuit 26,27 Image processing circuit 28 Memory arbiter 30 Conversion unit 32 Resolution conversion circuit 34 CPU 36 Main memory 38,40 Image data writing circuit 42 Display control circuit 50 Display unit 52 LCD LM line Memory DE area

Claims (3)

[Claims] 1. A photoelectric conversion element array in which a plurality of photoelectric conversion elements for outputting an electric signal corresponding to the amount of incident light are two-dimensionally arranged in a row direction and a column direction, and an arbitrary scanning direction from the photoelectric conversion element array. An image data detection device capable of detecting image data, wherein the device is applied to an image capturing device, wherein the photoelectric conversion element array has the same number of photoelectric conversion elements in the row direction in each of the divided areas. A plurality of line memories having a storage capacity corresponding to the number of photoelectric conversion elements in the row direction of the divided area and electrically cascade-connected, and the image data detection; Image data processing means for processing the image data detected by the means, wherein the image data processing means determines whether the photoelectric conversion element array is provided by the image data detection means for each of the divided areas. An image processing apparatus for detecting image data in the row direction, and sequentially storing the detected image data in the line memory in a first-in first-out manner. 2. The image processing apparatus according to claim 1, further comprising: a boundary detecting unit configured to detect a boundary of the divided area in the column direction, wherein the image data processing unit is configured to output the image data when the boundary is detected by the boundary detecting unit. Boundary image data corresponding to the boundary of the image data detected by the detection means is saved, and the boundary data of the image data detected by the image data detection means is saved based on the saved boundary image data of the adjacent divided area. An image processing apparatus configured to process boundary image data corresponding to the image data. 3. The photoelectric conversion element array according to claim 1, wherein the photoelectric conversion element array is a CMOS (Complementary).
An image processing apparatus using a Mental-Oxide Semiconductor device.