JP2002199164A - Semiconductor integrated circuit device and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit which quickly amplifies the output signal of a photodetector with low noise. SOLUTION: Since a switched capacitor circuit is used to perform subtraction and amplification of a reset voltage from an optical signal by several clock cycles, they are performed quickly. A circuit constitution which simultaneously samples the optical signal and the reset voltage is provided to realize a read circuit which is scarcely affected by the noise inputted mainly from a power supply system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plurality of light receiving elements for converting an optical signal into electric charges, a reset circuit for resetting the light receiving elements to a constant potential, and a reset level for reading out the voltage of each light receiving element after reset. A readout circuit;
After resetting the plurality of light receiving elements, read out the voltage of the light receiving elements after accumulating the optical signal charges for a certain period of time, and read out the voltage of the light signal reading circuits, and a scanning circuit that sequentially reads the reset level and the optical signals. The present invention relates to an integrated circuit device, and more particularly to an integrated circuit device in which the reading speed of optical signals after a scanning circuit is improved.

[0002]

2. Description of the Related Art Conventionally, a contact type image sensor chip used for reading an original in a facsimile or a scanner, etc., outputs read image information, that is, an optical signal, to the outside of the chip by a configuration as shown in FIG. I have. That is, circuit blocks 1-1 to 1-n including a photodiode, a reset level readout circuit, and an optical signal readout circuit.
Are arranged in a line on the contact-type image sensor chip, and the scanning circuit 2 scans and reads out the reset potential of the photodiode after reset and the optical signal after the photodiode has been irradiated with light for a certain period. Since the read optical signal includes a potential and a reset potential that are proportional to the intensity of the irradiated light, the optical signal scanned and read by the gain amplifier and the clamp circuit 3
The reset potential is subtracted and amplified, and output to the outside of the chip through the buffer amplifier 10.

FIG. 3A shows a circuit example of a conventional gain amplifier, clamp circuit 3 and buffer amplifier 10. In the conventional example, subtraction and amplification of the reset potential from the optical signal
This is performed by a non-inverting amplifier using a capacitor and a switch connected in series to the input of an operational amplifier and a switch, and two feedback resistors. Hereinafter, the subtraction of the reset potential from the optical signal and the signal amplification by the clamp and the non-inverting amplifier will be described with reference to the analog switch 40 shown in FIG.
A brief description will be given with reference to FIG. Note that the timing chart in FIG.
In (b), when the signal waveform is “H”, the analog switch is on, and when the signal waveform is “L”, the analog switch is off.

First, an optical signal Vin from a scanning circuit is generated as shown in FIG.
Is applied to the input terminal 30 of FIG.
At time t1 in (b), the analog switch 4, the analog switch 41, the analog switch 42, and the analog switch 4
3. The analog switch 44 is closed. Operational amplifier 2
0, a resistor 60 and a resistor 61,
And the potential at both ends of the capacitor 50 is Vin and the offset voltage Vof1 of the operational amplifier 20.
The gain G1 of the non-inverting amplifier is multiplied by 1, but the non-inverting input terminal 70 of the operational amplifier 21 is connected to the AGND terminal 32 by the analog switch 42 and is maintained at this potential. Similarly, the potential at both ends of the capacitor 51 is determined by the offset voltage Vof2 of the operational amplifier 21, the operational amplifier 21, the resistor 6
2, the gain G2 of the non-inverting amplifier composed of the resistor 63 is doubled, but the non-inverting input terminal 71 of the operational amplifier 22
It is kept at the D potential.

Next, at time t2 in the timing chart of FIG.
Input reset voltage from
When the analog switch 40, the analog switch 41, and the analog switch 43 are closed at the time t3 in (b), the non-inverting amplifier of the operational amplifier 20 amplifies and outputs the reset voltage. Terminal 7
Since 0 is once held at the AGND potential, a change in the output obtained by amplifying the reset voltage, that is, a gain G1 times the voltage obtained by subtracting the reset voltage from the optical signal is applied to the input terminal 70 to the non-inverting amplifier of the operational amplifier 21. It was done. Similarly, since the change from the AGND potential is input to the non-inverting input terminal 71 of the buffer amplifier of the operational amplifier 22, the voltage obtained by subtracting the reset voltage from the optical signal is multiplied by the gain G1 and the gain G2. The voltage is output from the buffer amplifier of the operational amplifier 22.

[0006]

In the conventional gain amplifier and clamp circuit described above, when the reset signal is subtracted from the optical signal and only the optical signal component is output from the buffer amplifier, the two positive and negative signals of the conventional example are used. Since the amplification operations of the amplifiers are performed at the same time and output from the buffer amplifier during the amplification operation, there is a limit in improving the speed of the analog signal processing circuit from the amplification circuit to the buffer amplifier.

In the conventional optical signal reading, since the optical signal and the reset voltage are sequentially input to the gain amplifier and the clamp circuit in a time-series manner, the input which mainly enters the power supply system irregularly. However, since the noise is amplified and output as it is, there is a disadvantage that there is much noise.

[0008]

According to the present invention, subtraction and amplification of a reset voltage from an optical signal are performed in several clock cycles by using a switched capacitor circuit, so that the reset voltage can be performed at high speed. Was made possible. In addition, by proposing a circuit that simultaneously samples an optical signal and a reset voltage, a reading circuit that is hardly affected by noise mainly input from a power supply system can be realized.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing an example of an embodiment of a semiconductor integrated circuit device according to the present invention. In FIG. 1, circuit blocks 1-1 to 1-n including a light receiving element such as a photodiode, a reset level readout circuit, and an optical signal readout circuit are arranged in a line, and the scanning circuit 2 resets the reset potential of the photodiode after reset. And the light signal after the photodiode has been irradiated with light for a certain period of time,
Scanned and read. The read optical signal is connected to the switched capacitor circuit block 4 and the switched capacitor circuit block 5, where the reset signal is subtracted from the optical signal and the subtraction result signal is amplified. The outputs of the switched capacitor circuit block 4 and the switched capacitor circuit block 5 are input to an analog multiplexer 6, and the output is
0 is output outside the chip.

The switched capacitor circuit constituting the switched capacitor circuit block 4 and the switched capacitor circuit block 5 shown in FIG. 1 repeats sampling and amplification of an input signal in accordance with a control clock, but the switched capacitor circuit block shown in FIG. By controlling as follows, the reset level can be subtracted from the optical signal, the result can be amplified, and the output speed of the optical signal from the buffer amplifier 10 can be made higher than before.

That is, a switched capacitor circuit constituting the switched capacitor circuit block 4 of FIG.
The switched capacitor circuits of the switched capacitor circuit 5 constituting the switched capacitor circuit 5 block of FIG. While the circuit is in the sampling operation state, the switched capacitor circuits of the switched capacitor circuits constituting the switched capacitor circuit block 5 at positions opposite to each other are in the amplification operation state, while the switched capacitor circuits constituting the switched capacitor circuit block 4 are in the amplification operation state. While the circuit is in the amplifying operation state, the switched capacitor circuits of the switched capacitor circuits constituting the switched capacitor circuit block 5 at positions opposite to each other are in the sampling operation state. In addition, each of the switched capacitor circuits forming the switched capacitor circuit block 4 and each of the switched capacitor circuits forming the switched capacitor circuit block 5 do not enter the same sampling operation state or amplification state between the adjacent switched capacitor circuits. Control.

When the semiconductor integrated circuit of FIG. 1 of the present invention is controlled as described above, when one of the switched capacitor circuits of the switched capacitor circuit block is in the amplification state, the next stage of the switched capacitor circuit is in the sampling state. Has become. When the output of the preceding switched-capacitor circuit has been set by multiplying one clock cycle, the next-stage switched-capacitor circuit in the sampling state terminates sampling, and amplifies the sampled input, that is, the amplification of the preceding-stage amplification result. Since the operation is started, in the present invention, the amplification operation can be divided into the number of steps of the switched capacitor circuit, and one step can be performed by multiplying one clock cycle. Therefore, the amplification can be performed at high speed, whereas the conventional circuit had to end the amplification operation within one clock cycle. FIG. 4 is an output waveform diagram comparing output waveforms of the second-stage gain amplifier when a signal is amplified by two stages of gain amplifiers having the same gain and frequency characteristics. The input voltage is 1 mV and the gain of one stage is 10
An output of 1 V was obtained with a gain of 100 times in the two-stage amplification. 10 clock cycles per clock cycle
It can be seen that the output waveform 101 of the present invention is set to the final voltage 1 V faster than the output waveform 102 in the case of performing the 0-fold amplification.

Further, the semiconductor integrated circuit of FIG. 1 of the present invention is controlled as described above, and the output of each of the switched capacitor circuit blocks 4 and the output of the switched capacitor circuit block 5 are selected when they are in an amplification state. If the analog multiplexer 6 is switched, a signal obtained by subtracting the reset signal from the optical signal and amplifying the subtraction result signal is always input to the buffer amplifier 10 without interruption. For this reason, the optical signal received by the light receiving element can be continuously output from the output of the buffer amplifier 10 without any break, so that the optical signal output speed can be maximized.

FIG. 5 shows a second embodiment of the semiconductor integrated circuit according to the present invention. In FIG. 5, circuit blocks 1-1 to 1-n including a light receiving element such as a photodiode, a reset level readout circuit, and an optical signal readout circuit are arranged in a line, and the scanning circuit 2 resets the reset potential of the photodiode after reset. Then, the optical signal after the photodiode is irradiated with light for a certain period is scanned and read. The read optical signal is connected to the switched capacitor circuit block 4 and the switched capacitor circuit block 5,
This block subtracts the reset signal from the optical signal,
Amplification of the subtraction result signal is performed. Switched capacitor circuit block 4 and switched capacitor circuit block 5
Are connected to a sample-and-hold circuit 7 and a sample-and-hold circuit 8, respectively, and their outputs are further input to an analog multiplexer 6, the output of which is output outside the chip through a buffer amplifier 10.

By controlling the semiconductor integrated circuit device of FIG. 5 as follows, the output speed from the buffer amplifier 10 can be further increased. That is, the switched capacitor circuit forming the switched capacitor circuit block 4 of FIG. 5 and the switched capacitor circuit forming the switched capacitor circuit 5 block of FIG.
The switched capacitor circuits at positions opposite to each other are driven by clocks having the same frequency and opposite phases to each other, and constitute the switched capacitor circuit block 5 while the switched capacitor circuits constituting the switched capacitor circuit block 4 are in the sampling operation state. The switched-capacitor circuits located at positions opposite to each other in the switched-capacitor circuit are in the amplification operation state, while the switched-capacitor circuits constituting the switched-capacitor circuit block 4 are in the amplification operation state while the switched-capacitor circuit block 5 is being configured. The switched-capacitor circuits of the switched-capacitor circuits that are in opposition to each other are in a sampling operation state, and each of the switched-capacitor circuits forming the switched-capacitor circuit block 4 Each of the switched capacitor circuit constituting a capacitor circuit, a switched capacitor circuit block 5 is a switched capacitor circuit adjacent to each other is controlled so as not to the same sampling operation state or amplification conditions.

The sample-and-hold circuit 7 and the sample-and-hold circuit 8 shown in FIG. 5 sample the output of the preceding switched capacitor circuit block 4 and the output immediately before the output of the switched capacitor circuit block 5 changes from the amplification state to the sampling state, When the output of the switched capacitor circuit block 4 and the output of the switched capacitor circuit block 5 are each in the sampling state, the output is held. If the analog multiplexer 6 of FIG. 5 selects and switches when the outputs of the sample-and-hold circuits 7 and 8 are in the hold state, the buffer amplifier 10 always outputs the signal from the optical signal. Of the reset signal and amplification of the subtraction result signal are performed, and the sampled and held signal is input without a break.

In the embodiment of FIG. 5, in addition to the high speed of the amplifier circuit, a signal obtained by subtracting the reset signal from the optical signal and amplifying the subtraction result signal is always supplied to the input of the buffer amplifier 10. , And at the same time, a signal that has been held and settled by the sample and hold circuit 7 and the sample and hold circuit 8 is input. For this reason, the settling time of the buffer amplifier 10 is further reduced, and the optical signal output speed can be further increased.

Next, a specific circuit example of the switched capacitor amplifier circuit constituting the switched capacitor circuit block will be described. FIG. 6 is a specific example of a switched capacitor amplifier circuit, and FIG. 7 is a timing chart of a control clock.

The switched capacitor amplifier circuit of FIG.
As shown, the operational amplifier 120 and the analog switch 14
0 to 144, the capacity 151 having the capacity 151 times the capacity 151
0, and an input signal V1 is input to the input terminal 130.
An input signal V2 is input to the input terminal 131, and a signal obtained by multiplying the difference between V1 and V2 by n times is output from the output terminal 133.

The operation of the circuit will be described in detail with reference to the timing chart of FIG.
When φ2 is “L”, the analog switches 140 and 14 of the switched capacitor amplifier circuit of FIG.
2. The analog switch 144 is on, the analog switches 141 and 143 are off, and the circuit is in a sampling operation state. In this state, the input voltage V
1 is sampled by the capacitor 150, but the operational amplifier 1
Since the inversion input terminal 170 and the output terminal 133 are connected by the analog switch 142, the output voltage of the operational amplifier becomes a voltage level obtained by adding the AGND level and the offset voltage of the operational amplifier as shown in FIG. FIG.
In the above, the offset voltage of the operational amplifier is usually not less than 10 mV, so that it is not specified. One end of the other capacitor 151 is connected to the inverting input terminal 170 of the operational amplifier 120, and the other end is connected to the analog ground level through the analog switch 144. Therefore, the offset level of the operational amplifier 120 is stored at both ends of the capacitor 151. .

Next, when φ1 becomes “L” and φ2 becomes “H”, the analog switch 140 of the switched capacitor amplifier circuit shown in FIG. 6 is turned off, the analog switch 141 is turned on, and one end of the capacitor 150 is connected to the input terminal 130. Is connected to the input terminal 131, and the V2 level is input. On the other hand, one end of the capacitor 151 connected to the analog ground level by the analog switch 144 is connected to the output terminal 133 of the operational amplifier 120 because the analog switch 143 is turned on and the analog switch 144 is turned off. Since the analog switch 142 is turned off and the feedback circuit connecting the inverting input terminal 170 and the output terminal 133 of the operational amplifier 120 has only the capacitance 151, if the gain of the operational amplifier is sufficiently large, the output terminal 1 is determined by the charge conservation law.
As shown in FIG. 7, a level 33 times the difference between the two input levels is output to 33. During the sampling operation, since the offset voltage of the operational amplifier is stored in the capacitors 150 and 151, the offset level of the operational amplifier is not output. That is, the output voltage is n (V1−V2). In other words, the circuit of the specific embodiment in FIG. 6 amplifies the difference between two input voltages by two capacitance ratios, n times, and operates as a gain amplifier in which the offset voltage of the operational amplifier does not appear at the output.

FIG. 8 shows a specific circuit example of the semiconductor integrated circuit device of the present invention using the switched capacitor amplifier circuit of FIG. 6, and FIG. 8 shows a timing chart of control clocks f1 and f2 and waveforms of respective parts of the circuit. It is shown in FIG.

The semiconductor integrated circuit device according to the specific embodiment of the present invention shown in FIG. 8 has operational amplifiers 220 and 22 as shown in FIG.
1, analog switch 240-249, capacity 250-2
53, two switched capacitor amplifier circuits 21
0 and 211 are configured, and the two switched capacitor amplifier circuits 210 and 211 are connected in series to configure a first switched capacitor circuit block. Further, operational amplifiers 320 to 321 and an analog switch 34
0 to 349 and the capacities 350 to 353 are connected in series.
Two switched capacitor amplifier circuits 310 and 311 are configured to form a second switched capacitor circuit block. Switched capacitor amplifier circuits 210, 211,
Since the capacitance ratio between 310 and 311 is n, the gain of each switched capacitor amplifier circuit is n.

Now, input terminals 230 and 231 in FIG.
The input signals SIGNAL1 and RESE of the input waveform 1 in FIG.
T1 is input, and the input signals SIGNAL2 and RESET of the input waveform 2 in FIG. 9 are input to the input terminals 330 and 331 in FIG.
2 has been entered. As shown in FIG. 8, the switched capacitor amplifier circuit 210 is in a sampling operation state when the control clock f1 is “H”, and is in an amplification operation state when the control clock f2 is “H”. As shown in FIG.
Switched capacitor amplifier circuit 210 at time t1
The signal level of the SIGNAL1 signal sampled at time t1 is S1, and the voltage level of the RESET1 signal at time t2 is R1.
Assuming that 1, the switched capacitor amplifier circuit 21 of FIG.
As shown by the waveform at the point A 232 in FIG. 9, the output of 0 and the point A 232 amplify while the control clock f2 between t1 and t2 is “H”, and the final output voltage is n ( S1-R1).

Similarly, the switched capacitor amplifier circuit 310 of FIG. 8 is in a sampling operation state when the control clock f2 is "H", and when the control clock f1 is "H",
Since the amplifying operation state is set, the SIG sampled by the switched capacitor amplifier circuit 310 at time t2
The NAL2 signal voltage level is S2, and RES at time t3.
Assuming that the voltage level of the ET2 signal is R2, the output of the switched capacitor amplifier circuit 310 in FIG. 8 and the waveform at the point B 332 are, as shown by the waveform at the point B in FIG.
2).

Next, the switched capacitor amplifier 211 shown in FIG. 8 performs a sampling operation when the control clock f2 is "H", and performs an amplification operation when the control clock f1 is "H". Clock f1
Is "H", a sampling operation is performed, and when the control clock f2 is "H", an amplifying operation state is performed, and the output signal of the preceding stage is sampled and amplified. Therefore, the output of the switched capacitor amplifier circuit 211 in FIG. As shown by the waveform at point C in FIG. 9, the amplifying operation is performed while the control clock f1 between t2 and t3 is 'H', and the final output voltage is n ² (S1-R1). . Similarly, the output of the switched capacitor amplifier circuit 311 in FIG.
As shown by the waveform at the point D in FIG.
, The amplifying operation is performed while the control clock f2 is “H”, and the final output voltage is n ² (S2−R2).

The switched capacitor amplifier circuit 21 shown in FIG.
1 and the output of the switched-capacitor amplifier circuit 311 are selected by an analog multiplexer composed of an analog switch 440 and an analog switch 441 and input to a buffer amplifier by an operational amplifier 420 and output. The output of the switched capacitor amplifier 211 of FIG. 8 is selected when the control clock f1 is “H”, and the output of the switched capacitor amplifier 311 is the control clock f2.
Is "H", the output waveform of the output terminal 433 is SIGNAL as shown in the output waveform of FIG.
1 and RESET1, and SIGNAL2 and RESET
The result of two-stage amplification of the input signal of No. 2 by n times is obtained.

As described above, according to the present invention, two adjacent amplifier circuits connected in a series are not simultaneously set in the amplifying operation state, and while the first-stage switched-capacitor amplifying circuit is performing the amplifying operation, The switched-capacitor amplifier circuit is set in the sampling operation state, so that the amplification operation is performed in several clock cycles, so that it can be operated at high speed.

In FIG. 8, two differential inputs of normal rotation and inversion are provided;
A specific embodiment in which a switched-capacitor amplifier circuit is configured using a normal operational amplifier having one output has been described, but has two differential inputs of normal and inverted and two differential outputs of normal and inverted. If a switched-capacitor amplifier circuit is configured using a fully differential operational amplifier, the effect is greater.
FIG. 10 shows a specific embodiment thereof.

The semiconductor integrated circuit device according to the specific embodiment of the present invention shown in FIG.
0,521, analog switches 540-551, capacity 5
70 to 577 form two switched-capacitor amplifier circuits 510 and 511. Further, in order to convert the two differential outputs of the switched-capacitor amplifier circuit 511 into a single output, an operational amplifier 522, analog switches 552 to 561, and a capacitor 578 581 constitute a switched capacitor amplifier circuit 512. These three switched-capacitor amplifier circuits 510 to 512 are connected in series to form a first switched-capacitor circuit block. Further, the fully differential operational amplifier 62
0,621, analog switches 640 to 651, capacity 6
70 to 677 constitute two switched-capacitor amplifier circuits 610 and 611 connected in series,
22, analog switches 652 to 661, capacity 678 to
681 constitutes a switched capacitor amplifier circuit 612 and a second switched capacitor circuit block. Switched capacitor amplifier circuits 510-5
Since the capacity ratio of 12,610 to 612 is n, the gain of each switched capacitor amplifier circuit is n. Outputs of the first switched capacitor circuit block and the second switched capacitor circuit block are respectively supplied to a sample-and-hold circuit 513.
Is sampled and held by a sample-and-hold circuit 613, and is input to and output from a buffer amplifier by an operational amplifier 720 through an analog multiplexer including an analog switch 740 and an analog switch 741.

The circuit of the specific embodiment of FIG. 10 will be briefly described with reference to the timing chart of FIG. The input terminals 530 and 531 of FIG.
The input signals SIGNAL2 and RESET2 of the input waveform 2 of FIG. 1 are input to the input terminals 630 and 631 of FIG. The switched capacitor amplifier circuit 510 operates at time t1 in FIG.
Sample the two input signals simultaneously. Assuming that the sampled signal levels are S1 and R1, the waveforms at the two output terminals A1 and A2 of the switched capacitor amplifier circuit 510 at time t2 in FIG. 11 are A1 and A2 in FIG.
The waveform is vertically symmetrical as shown by the waveforms at two points, and the amplitude is n times the gain of the difference between S1 and R1. Similarly, regarding the output of the switched capacitor amplifier circuit 610, FIG.
The signal level sampled at time t2 of S1 is S
Assuming that R2 is 2, R2, the amplitude is a vertically symmetric waveform whose amplitude is n times the gain of the difference between S1 and R1 as shown by the waveforms at points B1 and B2 in FIG.

The great effect of this circuit configuration is that two input signals are sampled at the same time and the difference between them is amplified, so that noise entering the signal line in the same phase, such as noise from a power supply line, is obtained. Is that the circuit configuration is hardly affected.

Returning to the description of the circuit operation of FIG. 10, the second-stage switched-capacitor amplifier circuits 511 and 611
Sample the result amplified at the previous stage at times t2 and t3 in FIG. 11, respectively, and amplify it at the next clock cycle. Third-stage switched-capacitor amplifier circuit 512
And 612 sample the results amplified at the previous stage at times t3 and t4 in FIG. 11, respectively, and amplify them in the next clock cycle. Switched capacitor amplifier circuit 51
The output waveforms of 2 and 612 are the waveforms returned from differential to single as shown by the waveform at point E and the waveform at point F in FIG. 11, and the signal amplitude is n by the three-stage amplifier circuit.
³ has a (S1-R1) and n ³ (S2-R2).

Outputs of the switched capacitor amplifier circuits 512 and 612 are supplied to a sample-and-hold circuit 513 and a sample-and-hold circuit 613, respectively.
, And a voltage held by each circuit is selected through an analog multiplexer and input to a buffer amplifier including an operational amplifier 720. The output of the buffer amplifier has a waveform as shown in the output waveform of FIG. In the specific embodiment of FIG. 10, three-stage amplification is used. However, when a gain of several tens or more times is required as a whole, amplification with three or more stages is performed.
An amplifier circuit with the least current consumption can be realized.

[0036]

According to the present invention, as described above, the difference between the signal level from the light receiving element and the reset level can be amplified and output at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of an embodiment of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a block diagram of a conventional image sensor chip.

FIG. 3 is a circuit example of a conventional gain amplifier, clamp circuit, and buffer amplifier.

FIG. 4 is a comparison diagram of settling waveforms of the present invention and a conventional gain amplifier.

FIG. 5 is a block diagram showing an example of a second embodiment of the semiconductor integrated circuit according to the present invention.

FIG. 6 is a specific example of a switched capacitor amplifier circuit.

FIG. 7 is an example of a control clock and input / output signal waveforms in FIG. 6;

FIG. 8 is a circuit diagram showing an example of a semiconductor integrated circuit according to the present invention.

FIG. 9 is an example of a control clock and input / output signal waveforms of FIG. 8;

FIG. 10 is a circuit diagram showing an example of a semiconductor integrated circuit according to the present invention.

11 is an example of a control clock and input / output signal waveforms in FIG.

[Explanation of symbols]

1-1 to 1-n A circuit block including a light receiving element, a reset circuit, a reset level reading circuit, an optical signal reading circuit, etc. 2 Scanning circuit block 3 Gain amplifier and clamp circuit block 4, 5 Switched capacitor circuit block 6 Analog multiplexer 7,8 sample and hold circuit 10 buffer amplifier circuit 20,21,22,120,220,221,320,321,
420,522,622,720 Operational amplifier 520,521,620,621 Fully differential operational amplifier 40 ~ 44,140 ~ 144,240 ~ 249,340 ~
349,440,441,540-561,640-66
1,740,741 Analog switch 50,51,150,151,250-253,350-3
53,570-581,670-681 Capacity

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M118 AA02 AA10 AB01 BA06 BA14 CA02 FA08 5C024 CX03 EX01 GY31 GY38 HX09 HX13 HX17 HX29 5C051 AA01 BA03 DA03 DB01 DB15 DB18 DE17 5J069 AA01 AA21 AA48 CA FA15 HA25 HA29 HA40 HA44 KA01 KA26 KA33 MA08 MA11 SA01 TA01 TA06

Claims (12)

[Claims] 1. A plurality of light receiving elements for converting an optical signal into an electric charge, a reset circuit for resetting the plurality of light receiving elements to a constant potential, and a reset level reading circuit for reading a voltage of each light receiving element after the reset And after resetting the plurality of light receiving elements, read out the voltage of the light receiving elements after accumulating optical signal charges for a certain period of time, and a scanning circuit that sequentially reads out the reset level and the optical signal. A semiconductor integrated circuit device comprising: a first switched capacitor circuit block that amplifies a difference between two signals in response to the sequentially read optical signal and the sequentially read reset level; The first switch that amplifies a difference between two signals in response to the sequentially read optical signal and the sequentially read reset level. A second switched-capacitor circuit block having the same circuit configuration as the switched-capacitor circuit block; an analog multiplexer that switches and outputs at least an output of the first switched-capacitor circuit block and an output of the second switched-capacitor circuit block A semiconductor integrated circuit device, comprising: a circuit; and a buffer amplifier circuit that receives an output of the analog multiplexer circuit and outputs the signal with a gain of about 1. 2. A plurality of light receiving elements for converting an optical signal into an electric charge, a reset circuit for resetting the plurality of light receiving elements to a constant potential, and a reset level reading circuit for reading a voltage of each of the light receiving elements after the reset. And after resetting the plurality of light receiving elements, read out the voltage of the light receiving elements after accumulating optical signal charges for a certain period of time, and a scanning circuit that sequentially reads out the reset level and the optical signal. A semiconductor integrated circuit device comprising: a first switched capacitor circuit block that amplifies a difference between two signals in response to the sequentially read optical signal and the sequentially read reset level; The first switch that amplifies a difference between two signals in response to the sequentially read optical signal and the sequentially read reset level. A second switched-capacitor circuit block having the same circuit configuration as the switched-capacitor circuit block; a first sample-and-hold circuit for sampling and holding an output of the first switched-capacitor circuit block; and the second switched-capacitor circuit A second sample and hold circuit that samples and holds the output of the block; and at least an output of the first sample and hold circuit;
An analog multiplexer circuit that switches and outputs the output of the second sample-and-hold circuit, and a buffer amplifier circuit that receives the output of the analog multiplexer circuit and outputs the signal with a gain of about 1. , Semiconductor integrated circuit device. 3. The first switched capacitor circuit block and the second switched capacitor circuit block according to claim 1, wherein the first switched capacitor circuit block and the second switched capacitor circuit block are configured by a plurality of switched capacitor circuits connected in series. Semiconductor integrated circuit device. 4. A first switched capacitor circuit block and a second switched capacitor circuit block according to claim 2, wherein the first switched capacitor circuit block and the second switched capacitor circuit block are constituted by a plurality of switched capacitor circuits connected in series. Semiconductor integrated circuit device. 5. A switched capacitor circuit excluding the last stage of the plurality of switched capacitor circuits connected in series according to claim 3, having a non-inverting input and an inverting input, and a non-inverting output and an inverting output. A semiconductor integrated circuit device comprising a fully differential operational amplifier. 6. A switched capacitor circuit excluding the last stage of the plurality of switched capacitor circuits connected in series according to claim 4, wherein the switched capacitor circuit has a non-inverting input and an inverting input, and a non-inverting output and an inverting output. A semiconductor integrated circuit device comprising a fully differential operational amplifier. 7. A switched capacitor circuit constituting a first switched capacitor circuit block according to claim 1 and a switched capacitor circuit constituting a second switched capacitor circuit block according to claim 1. The opposing positions of the switched capacitor circuits are driven by clocks having the same frequency and opposite phases to each other, and the second switched capacitance circuit constituting the first switched capacitor circuit block is in a sampling operation state. Of the switched capacitor circuits forming the first circuit block are in the amplification operation state, while the switched capacitor circuits forming the first switched capacitor circuit block are in the amplification operation state. ,
The switched capacitor circuits of the switched capacitor circuits forming the second switched capacitor circuit block are in a sampling operation state, and each of the switched capacitor circuits forming the first switched capacitor circuit block is in a sampling operation state. Wherein each of the switched capacitor circuits constituting the second switched capacitor circuit block is controlled so that adjacent switched capacitor circuits do not enter the same sampling operation state or amplification state. Circuit control method. 8. A switched capacitor circuit forming a first switched capacitor circuit block according to claim 2 and a switched capacitor circuit forming a second switched capacitor circuit block according to claim 2. The opposing positions of the switched capacitor circuits are driven by clocks having the same frequency and opposite phases to each other, and the second switched capacitance circuit constituting the first switched capacitor circuit block is in a sampling operation state. Of the switched capacitor circuits forming the first circuit block are in the amplification operation state, while the switched capacitor circuits forming the first switched capacitor circuit block are in the amplification operation state. ,
The switched capacitor circuits of the switched capacitor circuits forming the second switched capacitor circuit block are in a sampling operation state, and each of the switched capacitor circuits forming the first switched capacitor circuit block is in a sampling operation state. Wherein each of the switched capacitor circuits constituting the second switched capacitor circuit block is controlled so that adjacent switched capacitor circuits do not enter the same sampling operation state or amplification state. Circuit control method. 9. The plurality of series-connected switched capacitor circuits constituting the first and second switched capacitor circuit blocks according to claim 3 to 6, wherein each of the adjacent switched capacitor circuits is adjacent to each other. Are driven by clocks having the same frequency and opposite phases to each other, and while one of the plurality of series-connected switched capacitor circuits is in the sampling operation state, the next-stage switched capacitor circuit is in the amplification operation state, While one of the series-connected switched capacitor circuits is in the amplifying operation state, the next-stage switched capacitor circuit is in the sampling operation state, and is connected in series, forming the first switched capacitor circuit block. The first stage of multiple switched capacitor circuits is in the sampling operation state Meanwhile, while the first stage of the plurality of serially connected switched capacitor circuits constituting the second switched capacitor circuit block is in an amplification operation state, the first stage constituting the first switched capacitor circuit block is connected in series. While the first stage of the plurality of switched capacitor circuits is in the amplifying operation state, the first stage of the plurality of serially connected switched capacitor circuits constituting the second switched capacitor circuit block is controlled to be in the sampling operation state. A method for controlling a semiconductor integrated circuit, comprising: 10. A switched capacitor circuit forming a first switched capacitor circuit block according to claim 1 and a switched capacitor circuit forming a second switched capacitor circuit block according to claim 1. The opposing positions of the switched capacitor circuits are driven by clocks having the same frequency and opposite phases to each other, and the second switched capacitance circuit constituting the first switched capacitor circuit block is in a sampling operation state. The switched capacitor circuits of the switched capacitor circuits forming the first switched capacitor circuit block are in an amplification operation state, while the switched capacitor circuits of the first switched capacitor circuit block are in the amplification operation state. Between,
The switched capacitor circuits of the switched capacitor circuits forming the second switched capacitor circuit block are in a sampling operation state, and each of the switched capacitor circuits forming the first switched capacitor circuit block is in a sampling operation state. The respective switched capacitor circuits constituting the second switched capacitor circuit block are controlled so that the adjacent switched capacitor circuits do not enter the same sampling operation state or amplification state, and 2. A switch to which an input to one switched capacitor circuit block and an input to a second switched capacitor circuit block according to claim 1 are connected to the input to each of said switched capacitor circuit blocks. Capacitor circuit, when each is in a sampling state, the scanning circuit according the first claims, characterized in that the optical signal and the reset level is controlled to enter the same time, the control method of the semiconductor integrated circuit. 11. A switched capacitor circuit forming a first switched capacitor circuit block according to claim 2 and a switched capacitor circuit forming a second switched capacitor circuit block according to claim 2. The opposing positions of the switched capacitor circuits are driven by clocks having the same frequency and opposite phases to each other, and the second switched capacitance circuit constituting the first switched capacitor circuit block is in a sampling operation state. The switched capacitor circuits of the switched capacitor circuits forming the first switched capacitor circuit block are in an amplification operation state, while the switched capacitor circuits of the first switched capacitor circuit block are in the amplification operation state. Between,
The switched capacitor circuits of the switched capacitor circuits constituting the second switched capacitor circuit block are in a sampling operation state, and each of the switched capacitor circuits constituting the first switched capacitor circuit block is in a sampling operation state. Each of the switched capacitor circuits constituting the second switched capacitor circuit block is controlled so that the adjacent switched capacitor circuits do not enter the same sampling operation state or amplification state, and the first switched capacitor circuit block The input to the second switched capacitor circuit block and the input to the second switched capacitor circuit block are respectively supported by the switched capacitor circuits connected to the inputs to the respective switched capacitor circuit blocks. 2. A control method for a semiconductor integrated circuit, characterized in that the scanning circuit according to claim 1 is controlled so that an optical signal and a reset level are input simultaneously when in an sampling state. 12. A plurality of serially connected switched capacitor circuits constituting the first and second switched capacitor circuit blocks according to claim 3 to 6, wherein each of the adjacent switched capacitor circuits is adjacent to each other. Are driven by clocks having the same frequency and opposite phases to each other, and while one of the plurality of series-connected switched capacitor circuits is in the sampling operation state, the next-stage switched capacitor circuit is in the amplification operation state, While one of the series-connected switched capacitor circuits is in the amplifying operation state, the next-stage switched capacitor circuit is in the sampling operation state, and is connected in series, forming the first switched capacitor circuit block. The first stage of multiple switched capacitor circuits is in sampling operation While the first stage of the plurality of serially connected switched capacitor circuits constituting the second switched capacitor circuit block is in the amplification operation state, the first stage is connected in series constituting the first switched capacitor circuit block. While the first stage of the plurality of switched capacitor circuits is in the amplification operation state, the first stage of the plurality of serially connected switched capacitor circuits constituting the second switched capacitor circuit block is controlled to be in the sampling operation state, The input to the first switched-capacitor circuit block and the input to the second switched-capacitor circuit block are provided when the first-stage switched-capacitor circuit of each of the switched-capacitor circuit blocks is in a sampling state. Item 1 From the scanning circuit, and a light signal and the reset level is controlled to enter the same time, the control method of the semiconductor integrated circuit.