JP2002198755A - Variable gain amplifier circuit - Google Patents

Abstract

(57) Abstract: Provided is a variable gain amplifying circuit that can reduce gain fluctuation by a simple circuit. SOLUTION: OTA1 is a replica of OTA3,
By setting the transconductance of OTA1 with high precision, the transconductance of OTA3 is also set with high precision. The MOS type transistor M101 and the MOS type transistor M102 form a current mirror circuit, and are set so that the current i101 and the current i102 become equal.
The drain-source resistance of the OS transistor M102 changes. The drain voltage is fed back to the gain control terminal G, and the transconductance of OTA1 is varied, so that the current i101 and the current i102 are controlled to be equal. At this time, the transconductance of OTA1 is determined by the voltage ratio between gain setting voltages Vd1 and Vd2 and the transconductance of OTA2. Since the voltage ratio can be set by the resistance ratio, the transconductance of OTA1 can be set with high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable gain amplifier circuit for converting an input voltage into an output current with a variable transconductance.

[0002]

2. Description of the Related Art An OTA (Operat) which has a transconductance variable by an external control signal and converts an input differential voltage into a current corresponding to the transconductance.
There is a current output type variable gain amplifier circuit called ional Transconductance Amplifier).

FIG. 2 is a diagram showing a basic configuration of the OTA. The OTA shown in FIG. 2 is a MOS transistor M1
1 to M13, an output unit 11, a constant current circuit I11, and a constant current circuit I12.

The MOS transistor M11 has a gate connected to the terminal V +, and outputs a current i11 flowing from the output section 11 to a constant current circuit I11 from the drain to the source.
And the drain of the MOS transistor M13. The MOS transistor M12 has a gate connected to the terminal V
The current i12 which is connected to
Flows from the drain to the source through the source to the constant current circuit I12 and the source of the MOS transistor M13. M
The OS-type transistor M13 has a gate connected to the gain control terminal G
The drain and the source are connected to the source of the MOS transistor M11 and the source of the MOS transistor M12, respectively.

[0005] The constant current circuit I11 receives a current from the source of the MOS transistor M11 and a current from the drain of the MOS transistor M13 and passes a constant current to the ground potential. The constant current circuit I12 is a MOS
From the source of transistor M12 and MO
Upon receiving a current from the source of the S-type transistor M13,
A constant current is flowing to the ground potential.

The output section 11 is provided with a MOS transistor M1
Output current i + of a magnitude corresponding to the drain current i11
To the terminal I +. Further, an output current i− having a magnitude corresponding to the drain current i12 of the MOS transistor M12 is output to the terminal I−.

When a differential voltage v is applied between the terminal V + and the terminal V-, the drain current i11 and the drain current i12 change according to the voltage, and the terminal I
The magnitude of the current i1 of + and the current i− of the terminal I− change. For example, when the voltage at the terminal V + is higher than the voltage at the terminal V−, the drain current i11 of the MOS transistor M11 becomes larger than the drain current i12 of the MOS transistor M12, and the node N11 to the node N
The current i13 flows toward. If the magnitudes of the currents of the constant current circuit I11 and the constant current circuit I12 are equal, the magnitude of the current i13 is equal to the magnitude of the difference between the drain current i11 and the drain current i12 (differential current). Become. That is, the differential current between the drain current i11 and the drain current i12 changes according to the differential voltage v, and the differential current between the output current i + and the output current i- also changes accordingly.

The drain of the MOS transistor M13
When the resistance between the sources increases, the current i13 decreases, so that the drain current i11 according to the change in the differential voltage v
And the change in the differential current between the drain current i12 and the
The change in the differential current between the output current i + and the output current i- is also small. Conversely, when the resistance between the drain and the source of the MOS transistor M13 decreases, the current i13 increases, so that the drain current i according to the change in the differential voltage v is increased.
11 and the drain current i12 increase, and the differential current between the output current i + and the output current i- also increases.

The change Δid of the differential current between the output current i + and the output current i− with respect to the change Δv of the differential voltage v is expressed by the mutual conductance gm as follows.

[0010]

## EQU1 ## Δid = gm × Δv (1)

Further, the magnitude of the transconductance gm changes according to the drain-source resistance rds of the MOS transistor M13, and the following equation is generally established.

[0012]

Gm = 1 / rds (2)

Therefore, by changing the voltage applied to the gain control terminal G, the transconductance gm of the OTA shown in FIG. 2 can be arbitrarily changed.

An OTA having such characteristics is, for example,
It is applied to a filter circuit that can control the band arbitrarily. FIG. 15 is a diagram illustrating an integral element of a filter circuit configured using OTA. FIG. 15 (a)
FIG. 3 is a circuit diagram showing an integral element using OTA. This integrating element has an OTA and two capacitors 2. FIG. 15B is a block diagram illustrating a transfer function of the integral element shown in FIG.

[0015] As shown in FIG.
The output terminal I + and the output terminal I− are connected to the ground potential via the capacitor 2 respectively. When a very small voltage vi is applied between the input terminal V + and the input terminal V− of the OTA, the voltage vo generated between the output terminal I + and the output terminal I− is, when the capacitor 2 has a capacitance C,
It can be expressed as the following equation.

[0016]

(Equation 3)

When the two sides are subjected to Laplace transform to obtain an input / output transfer function T, the following equation is obtained.

T = (gm / C) / s = ω0 / s (4) ω0 = gm / C

By configuring a filter using the integral element shown in FIGS. 15A and 15B as a basic element of the filter, an arbitrary filter circuit can be configured using an OTA and a capacitor.

FIG. 16 is a diagram showing a first-order low-pass filter formed using OTA. FIG. 16 (a)
FIG. 3 is a circuit diagram illustrating a first-order low-pass filter using OTA. This primary low-pass filter is an OTA30
And OTA 31 and two capacitors 2. FIG. 16B is a block diagram illustrating a transfer function of the first-order low-pass filter illustrated in FIG.

The output terminal I + and the output terminal I- of the OTA 30 are connected to the output terminal I- and the output terminal I + of the OTA 31.
Are connected to the input terminal V + and the input terminal V− of the OTA 31, respectively. Further, each output terminal of the OTA 30 is connected to the ground potential via the capacitor 2. Further, a gain control signal S30 is input to the gain control terminal G.
The output terminal I + and the output terminal I− of the OTA 31 are OT
A30 is connected to the output terminal I− and the output terminal I +, respectively, and is also connected to the input terminal V− and the input terminal V + of the OTA31, respectively. Furthermore, O
Each output terminal of the TA 31 is connected to the ground potential via the capacitor 2. Further, a gain control signal S30 is input to the gain control terminal G.

The output current of the OTA 30 and the output current of the OTA 31 are input to the capacitor 2. The output current of the OTA 31 is obtained by converting the output voltage vo into a current, and is input to the capacitor 2 with a polarity inverted with respect to the polarity of the output voltage vo. When the OTA 30 and the OTA 31 have the same transconductance gm and the capacitor 2 has the capacitance value C, the output voltage vo can be expressed by the following equation.

[0022]

(Equation 5)

When both sides of the equation (5) are subjected to Laplace transform and an input / output transfer function T is obtained, the following equation is obtained.

[0024]

(Equation 6)

The cut-off frequency f0 of the first-order low-pass filter having the transfer function T represented by the equation (6) is f0 = gm
/ (2πC). Therefore, the gain control signal S30
, The cut-off frequency f0 of the low-pass filter can be linearly varied.

FIG. 17 is a diagram showing a sine wave oscillation circuit configured using OTA. FIG. 17A is a circuit diagram showing a sine wave oscillation circuit using OTA. This sine wave oscillation circuit has OTA 32 and OTA 33 and four capacitors 2. FIG. 17 (b) is the same as FIG.
FIG. 4 is a block diagram illustrating a transfer function of the sine wave oscillation circuit shown in FIG.

The output terminal I + and the output terminal I− of the OTA 32 are connected to the input terminal V + and the input terminal V− of the OTA 33, respectively.
And are connected respectively. The input terminal V + and the input terminal V− of the OTA 32 are connected to the output terminal I of the OTA 33.
− And the output terminal I +. The output terminal of each OTA is connected to the ground potential via the capacitor 2.

In the block diagram of FIG.
The voltage vi not shown in FIG. 7A represents a disturbance component with respect to the input of the OTA 32. That is, FIG.
(B) is a block diagram including the disturbance voltage vi mixed into the input of the OTA 32. OTA32 and OTA33
Have the same transconductance gm, and the capacitor 2
Has a capacitance value C, the transfer function of the output voltage vo with respect to the disturbance voltage vi is as follows.

[0029]

(Equation 7)

When the transfer function T represented by the equation (7) is subjected to the inverse Laplace transform, the output voltage vo becomes a sine wave, and the oscillation frequency f0 becomes f0 = gm / (2πC). Therefore,
By varying the gain control signal S30, the oscillation frequency f0 can be varied linearly.

[0031]

As described above, O
If the filter circuit is configured using TA, there is an advantage that the cutoff frequency of the low-pass filter and the oscillation frequency of the sine wave oscillation circuit can be easily controlled by varying the mutual conductance gm. However, the control of the transconductance gm in the OTA has several problems described below.

As shown in the equation (2), the transconductance of the OTA is the same as that of FIG.
-Source resistance rds of the p-type transistor M13
Depends on This drain-source resistance rds
Fluctuates according to the voltage applied between the gate and the source. On the other hand, the signal source of the differential voltage input between the gates of the MOS transistor M11 and the MOS transistor M12 often has a high impedance with respect to the ground potential. Components easily overlap. Therefore, there is a problem that the transconductance of the OTA fluctuates due to the in-phase noise component.

The drain-source resistance rds is
Since the voltage also varies depending on the threshold voltage unique to each MOS transistor, even if the same gate-source voltage is applied, the resistance value differs for each individual transistor. That is, OT
There is a problem that the mutual conductance of A tends to vary from individual to individual. Further, this threshold voltage is liable to fluctuate due to temperature characteristics. Therefore, there is a problem in that the transconductance of the OTA easily varies depending on the temperature.

The transconductance g of such an OTA
Conventionally, the following method is used to compensate for the variation in m.

FIG. 18 is a diagram showing a conventional first circuit for setting mutual conductance. FIG.
The transconductance setting circuit 50 shown in FIG.
4 and OTA 35, four capacitors 2, a waveform shaping unit 31, a phase comparing unit 32, a charge pump unit 33, and a low-pass filter unit 34.

The circuit including the OTA 34, the OTA 35 and the four capacitors 2 has the same configuration as the sine wave oscillation circuit shown in FIG. 17, generates a sine wave differential voltage from the OTA 35, and shapes the waveform. The signal is output to the circuit 31. The OTA 34 and the OTA 35 receive the gain control signal S1 output from the low-pass filter unit 34 at the gain control terminal G and vary the mutual conductance, thereby controlling the oscillation frequency of the sine wave output to the waveform shaping circuit 31. . That is, a circuit including the OTA 34, the OTA 35 and the four capacitors 2 makes one VC
O is configured.

The waveform shaping circuit 31 includes OTA 34, OTA
A sine wave signal of the VCO including the 35 and the four capacitors 2 is received, shaped into a rectangular wave signal, and output to the phase comparison unit 32. The phase comparison unit 32 includes a waveform shaping unit 31
And an external reference clock signal Ref-CLK
And charge or discharge the internal capacitor of the charge pump unit 33 according to the result of the comparison. The charge pump unit 33 charges or discharges the internal capacitor according to the signal from the phase comparison unit 32, and smoothes the voltage waveform of the capacitor in the low-pass filter unit. The low-pass filter unit 34 smoothes the signal output from the charge pump unit 33, outputs the smoothed signal as a gain control signal S1, and feeds it back to the gain control terminals G of the OTA 34 and OTA 35.

The transconductance setting circuit shown in FIG. 18 comprises an OTA 34, an OTA 35 and four capacitors 2
Is a PLL circuit configured to synchronize the frequency of an oscillation circuit composed of an external reference clock signal Ref-CLK. With this PLL circuit, OTA34, OT
The oscillation frequency of the oscillation circuit including A35 and the four capacitors 2 is controlled with high accuracy. The OTA 34 and the OTA 35 are replicas of other OTA circuits, and the mutual conductance fluctuates in the same tendency as other OTAs due to in-phase noise, variation between individuals, variation due to temperature, and the like. Therefore, if the gain control signal S1 of the OTA 34 and the OTA 35 whose transconductance is controlled with high precision is supplied to other OTAs,
A also has a transconductance of OTA34 and OTA3.
It is set with high accuracy as in 5.

However, the first transconductance setting circuit shown in FIG. 18 has a problem that the circuit scale is increased by a plurality of blocks for configuring the PLL circuit. Therefore, other schemes that can simplify the transconductance setting circuit have been devised.

FIG. 19 shows a second conventional circuit for setting mutual conductance. FIG.
The transconductance setting circuit 51 shown in FIG.
6. It has a MOS transistor M1 and a MOS transistor M2, a voltage source V1 and a current source I1.

In the OTA 36, a voltage from a voltage source V1 is supplied to an input terminal V + and an input terminal V-. The output terminal I + is connected to the drain of the MOS transistor M1 and the current source I1, and the output terminal I− is connected to the MOS transistor M1.
It is connected to the drain of the type transistor M2 and the gain control terminal G. In the MOS transistor M1, the drain is connected to the gate, the source is grounded, and a part of the current output from the output terminal I + of the OTA 36 flows from the drain to the source. The gate is connected to the gate of the MOS transistor M2.
The MOS transistor M2 has a drain connected to the output terminal I− and the gain control terminal G of the OTA 36, a source grounded, and a gate connected to the gate of the MOS transistor M1.

The MOS transistor M1 and the MOS transistor M2 constitute a general current mirror circuit. That is, the MOS transistor M1 and the MOS transistor M1 are connected between the drain and source of the MOS transistor M2.
It operates as a constant current source such that the drain current of the S-type transistor M2 becomes equal. MOS transistor M1
Flows from the current i output from the output terminal I + of the OTA 36 to the drain of the MOS transistor M2 because the current has a magnitude of (i-i1) obtained by subtracting the current i1 from the current source I1. The source-to-source resistance changes such that the magnitude of the drain current approaches (i-i1).

Therefore, for example, when the differential current of the OTA 36 increases and the drain current of the MOS transistor M2 becomes smaller than (i-i1), the drain-source resistance decreases and the MOS transistor M
2, the drain voltage drops. As a result, the voltage of the gain control terminal G decreases, and the gate voltage of the MOS transistor M13 decreases, whereby the transconductance decreases, and the differential current output from the OTA 36 decreases. Also, the differential current of the OTA 36 becomes smaller,
When the drain current of the type transistor M2 becomes larger than (i-i1), the resistance between the drain and the source increases, and the drain voltage of the MOS type transistor M2 increases. As a result, the voltage of the gain control terminal G increases, and the gate voltage of the MOS transistor M13 increases, so that the transconductance increases.
The differential current output from the TA 36 increases. Thus, the drain current of the MOS transistor M2 becomes (i)
The voltage supplied to the gain control terminal G is controlled so as to be equal to -i1).

When the drain current of the MOS transistor M2 becomes equal to (i-i1), the differential current of the OTA 36 becomes equal to i1.
The transconductance gm of No. 6 is set to the value of the following equation.

[0045]

Gm = i1 / v1 (8)

As shown in the equation (8), in the second transconductance setting circuit, the mutual conductance gm is controlled by varying the current i1 of the current source I1 or the voltage v1 of the voltage source V1.

As compared with the first transconductance setting circuit using the PLL, the circuit is superior in that the circuit is simplified, but there are other problems. As can be seen from equation (8), the transconductance gm is proportional to the set value.
Is required to vary the current value of the current source I1. However, since the magnitude of the differential current output from the OTA 36 is generally very small, there is a problem that it is difficult to control the current source I1. For example, if the current source I1 is a current output type D / A
In the case of using a converter, in order to obtain a sufficient resolution, it is necessary to control a current of about several hundred nA in a change of 1 LSB. Thus, the current source I
There is a problem that the smaller the current to be set to 1, the lower the accuracy of the mutual conductance.

Although the problem described above relates to the setting accuracy of the mutual conductance, there is another problem related to the variable range of the mutual conductance.

In order to output a differential current proportional to the transconductance in accordance with the differential voltage input to the OTA, the resistance r of the MOS transistor M13 in FIG.
ds must be kept constant regardless of the differential voltage. If the magnitude of the resistance rds changes in accordance with the differential voltage, the differential current also changes in accordance with this change, and the signal waveform of the differential current differs from the signal waveform of the differential voltage. It becomes something. That is,
The signal waveform of the output differential current is distorted.

Generally, the gate of a MOS transistor is
The difference between the source voltage VGS and the threshold voltage VT (VGS-V
In a range where T) is sufficiently larger than the drain-source voltage VDS, the relationship between the drain current ID and the drain-source voltage VDS is proportional. That is, the following equation is established.

[0051]

(Equation 9)

In the equation (9), the proportional constant β is a constant determined by the structure of the gate. As can be seen from equation (9), the relationship between the drain current ID and the drain-source voltage VDS is proportional, and the drain-source resistance rds is varied by the gate-source voltage VGS.

Equation (9) is an equation that is satisfied in a range where the difference (VGS-VT) between the gate-source voltage VGS and the threshold voltage VT is sufficiently larger than the drain-source voltage VDS. When the inter-voltage VDS increases and approaches (VGS-VT), the following equation is established instead of the equation (9).

[0054]

(Equation 10)

As can be seen from equation (10), the drain-
When the source-to-source voltage VDS increases and approaches (VGS-VT), the proportional relationship between the drain current ID and the drain-source voltage VDS is lost. That is, the drain-source resistance rds is equal to the drain-source voltage Vd.
It changes according to DS.

Therefore, in order to output a differential current without distortion, the gate of the MOS transistor M13 must be
It is required that the source-to-source voltage be sufficiently higher than the drain-source voltage VDS. However, under the condition that the amplitude of the differential input voltage is large and the transconductance gm is small, the voltage between the gate and the source of the MOS transistor M13 decreases, and the amplitude of the voltage VDS between the drain and the source increases. Inevitably, the output differential current is distorted.

As described above, in the conventional OTA, when the set value of the transconductance gm is small, there is a problem that the differential output current is distorted with respect to the differential input voltage having a large amplitude. That is, there is a trade-off between the variable range of the transconductance gm and the amplitude range of the differential input voltage, and there is a problem that if one range is widened, the other range must be narrowed.

The present invention has been made in view of the above circumstances, and an object of the present invention is to make it possible to set a mutual conductance with high accuracy by using a simple circuit, and to reduce the mutual conductance without being limited by an input voltage. It is an object of the present invention to provide a variable gain amplifying circuit which can be varied over a wide range.

[0059]

To achieve the above object, a first variable gain amplifying circuit according to the present invention comprises a first and a second transistor having a differential input voltage input to a control terminal; A third transistor connected between the first transistor and the second transistor and having a control terminal to which a gain control signal is input, a current flowing through the first transistor and a current flowing through the second transistor A first amplifier circuit having an output unit for outputting a differential current between a first output current and a second output current corresponding to
Fourth and fifth transistors, the first and second voltages of which are respectively input to control terminals, are connected between the fourth transistor and the fifth transistor, and the gain control signal is connected to the control terminal. A sixth transistor to be input, a first current corresponding to a current flowing through the fourth transistor, and a second current smaller than the first current respectively corresponding to the current flowing through the fifth transistor; A second amplifier circuit having an output section for outputting a differential current; and a seventh amplifier circuit to which the third and fourth voltages are respectively input to the control terminals.
And an eighth transistor, a resistance element connected between the seventh transistor and the eighth transistor, and a current flowing through the seventh transistor and a current flowing through the eighth transistor, respectively. A third amplifier circuit having an output unit for outputting a differential current between a third current to be generated and a fourth current smaller than the third current; And the second current
And a current mirror circuit that generates the gain control signal in accordance with the combined current of the third current and the third current.

The second variable gain amplifying circuit according to the present invention comprises a first variable gain amplifier and a second variable gain amplifier.
Transistor, the first transistor, and the second transistor
And a third transistor connected between the first and second transistors and having a control terminal to which a gain control signal is input, and outputting an output current corresponding to a current flowing through the first transistor and a current flowing through the second transistor. A first amplifying circuit having an output unit for performing the operation, a fourth and a fifth transistor each of which receives the first and second voltages at a control terminal;
A sixth transistor connected between the fourth transistor and the fifth transistor, the control terminal receiving the gain control signal, a current flowing through the fourth transistor and a current flowing through the fifth transistor; A second amplifier circuit having an output section for outputting a first current corresponding to the flowing current, a seventh and an eighth transistor each having a third and a fourth voltage input to a control terminal, A resistance element connected between the seventh transistor and the eighth transistor, and a second element corresponding to a current flowing through the seventh transistor and a current flowing through the eighth transistor.
A third amplifier circuit having an output unit for outputting a current of
A current mirror circuit that generates the gain control signal according to the first current and the second current.

In the first or second variable gain amplifier circuit of the present invention, the first amplifier circuit supplies first and second current sources for supplying current to the first and second transistors, respectively. The second amplifier circuit has third and fourth current sources for supplying currents to the fourth and fifth transistors, respectively, and the third amplifier circuit has the seventh and fourth current sources. There are fifth and sixth current sources for supplying current to the eighth transistor, respectively.

The third variable gain amplifier circuit according to the present invention comprises a first variable gain amplifier circuit and a second variable gain amplifier circuit.
Transistor, the first transistor, and the second transistor
A third transistor connected between the first and second transistors and having a control terminal to which a first gain control signal is input, and corresponding to a current flowing through the first transistor and a current flowing through the second transistor, respectively. The first current and the second
A first amplifying circuit having an output unit for outputting a differential current with respect to the current of the first and second currents; fourth and fifth transistors having the differential input voltage input to a control terminal; A sixth transistor connected between the fifth transistor and a control terminal to which a second gain control signal is input; a current flowing through the fourth transistor;
Corresponding to the currents flowing through the transistors
A second amplifier circuit having an output unit for outputting a differential current between the first current and the fourth current; a gain control circuit generating the first and second gain control signals; A first output terminal for supplying a combined current of the second current and the fourth current; and a second output terminal for supplying a combined current of the second current and the third current. .

The fourth variable gain amplifying circuit of the present invention comprises a first variable gain amplifier and a second variable gain amplifier.
Transistor, the first transistor, and the second transistor
A third transistor connected between the first and second transistors and having a control terminal to which a first gain control signal is input, and corresponding to a current flowing through the first transistor and a current flowing through the second transistor, respectively. The first current and the second
A first amplifying circuit having an output unit for outputting a differential current with respect to the current of the first and second currents; fourth and fifth transistors having the differential input voltage input to a control terminal; A sixth transistor connected between the fifth transistor and a control terminal to which a second gain control signal is input; a current flowing through the fourth transistor;
Corresponding to the currents flowing through the transistors
A second amplifier circuit having an output unit for outputting a differential current between the first current and the fourth current; a combined current of the first current and the fourth current; the second current; A voltage generating circuit for generating a differential voltage according to the combined current with the third current; and a seventh and an eighth, wherein the differential voltage is input to a control terminal.
Transistor, the seventh transistor, and the eighth transistor.
And the control terminal is connected to the first terminal.
And a differential current between a fifth current and a sixth current corresponding to a current flowing through the seventh transistor and a current flowing through the eighth transistor, respectively. A third amplifier circuit having an output unit for outputting the differential voltage, a tenth and an eleventh transistor in which the differential voltage is input to a control terminal, and A twelfth transistor connected to the control terminal and receiving the second gain control signal, a seventh current corresponding to a current flowing through the tenth transistor and a current flowing through the eleventh transistor, respectively. A fourth amplifier circuit having an output unit that outputs a differential current with the eighth current, a gain control circuit that generates the first and second gain control signals,
A first output terminal for supplying a combined current of the fifth current and the eighth current, the sixth current and the seventh output terminal,
And a second output terminal for supplying a combined current with the current.

The fifth variable gain amplifying circuit according to the present invention comprises the first and second variable gain amplifying circuits in which the differential input voltage is input to the control terminal.
Transistor, the first transistor, and the second transistor
A third transistor connected between the first and second transistors and having a control terminal to which a first gain control signal is input; and a third transistor corresponding to a current flowing through the first transistor and a current flowing through the second transistor. A first amplifier circuit having an output unit for outputting a first current, fourth and fifth transistors having the differential input voltage input to a control terminal, the fourth transistor and the fifth transistor And a second transistor connected to the control terminal and receiving a second gain control signal at the control terminal; and a second transistor corresponding to a current flowing through the fourth transistor and a current flowing through the fifth transistor. A second amplifier circuit having an output unit for outputting a current, a gain control circuit for generating the first and second gain control signals, and a combined current of the first current and the second current. Supply And an output terminal for.

The sixth variable gain control circuit according to the present invention comprises a first variable gain control circuit and a second variable gain control circuit.
Transistor, the first transistor, and the second transistor
A third transistor connected between the first and second transistors and having a control terminal to which a first gain control signal is input; and a third transistor corresponding to a current flowing through the first transistor and a current flowing through the second transistor. A first amplifier circuit having an output unit for outputting a first current, fourth and fifth transistors having the differential input voltage input to a control terminal, the fourth transistor and the fifth transistor And a second transistor connected to the control terminal and receiving a second gain control signal at the control terminal; and a second transistor corresponding to a current flowing through the fourth transistor and a current flowing through the fifth transistor. A second amplifier circuit having an output unit for outputting a current; a voltage generating circuit for generating a signal voltage corresponding to a combined current of the first current and the second current; Are connected between the seventh transistor and the eighth transistor respectively input to the control terminal, and the seventh transistor is connected between the seventh transistor and the eighth transistor, and the first gain control signal is input to the control terminal. Ninth transistor, a third amplifier circuit having an output unit for outputting a third current corresponding to the current flowing in the seventh transistor and the current flowing in the eighth transistor, the signal voltage and the reference voltage. Tenth and eleventh transistors each having a voltage input to the control terminal, and connected between the tenth transistor and the eleventh transistor;
A twelfth control signal to which the second gain control signal is input;
A fourth amplifier circuit having a transistor that outputs a fourth current corresponding to the current flowing through the tenth transistor and the current flowing through the eleventh transistor; and the first and second amplifiers. And a output terminal for supplying a combined current of the third current and the fourth current.

[0066]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Six embodiments in which the present invention is applied to an OTA will be described below with reference to the drawings.

<First Embodiment> FIG. 1 is a circuit diagram showing a first embodiment of a variable gain amplifier circuit according to the present invention. The variable gain amplifier circuit of FIG. 1 includes a transconductance setting circuit 100 and OTA3. The transconductance setting circuit 100 includes OTA1 and OTA2, MOS transistors M101 and M101.
OS type transistor M102, gain setting voltage output unit Vd1
And a gain setting voltage output unit Vd2.

OTA1 has an input terminal V + and an input terminal V-
The voltage from the gain setting voltage output unit Vd1 is applied between the MOS transistor M1 and the gain control terminal G.
02 is applied. The output terminal I + is connected to the output terminal I− of the OTA2, and the output terminal I +
− Is connected to the output terminal I + of OTA2. OTA
2, a voltage from the gain setting voltage output unit Vd2 is applied between the input terminal V + and the input terminal V-. The output terminal I + is connected to the output terminal I− of the OTA2, and the output terminal I− is connected to the output terminal I + of the OTA2. M
The OS type transistor M101 is connected to the output terminal I of the OTA1.
The drain is connected to the connection point between + and the output terminal I- of OTA2, and the source is grounded. The drain and the gate are connected, and this gate is
It is connected to the gate of OS-type transistor M102. The MOS transistor M102 has a drain connected to a connection point between the output terminal I + of the OTA1 and the output terminal I− of the OTA2, and a source grounded. Also,
The gate is connected to the gate of the MOS transistor M101. Further, the drain voltage is output to the gain control terminal G of the OTA 1 and the gain control signal S 1
Is output to the gain control terminal G of the OTA3.

OTA3 has an input terminal V + and an input terminal V-
An input signal voltage Vin is applied between the input and output terminals, and a gain control signal S1 from the transconductance setting circuit 100 is input to the gain control terminal G.

Here, the internal configuration of OTA1 to OTA3 will be described in more detail.

FIG. 2 is a circuit diagram of OTA1 and OTA3 in the first embodiment of the present invention. O shown in FIG.
The TA has MOS transistors M11 to M13, an output unit 11, a constant current circuit I11, and a constant current circuit I12.

The MOS transistor M11 has a gate connected to the terminal V +, and outputs a current i11 flowing from the output section 11 from the drain to the source through the constant current circuit I11.
And the drain of the MOS transistor M13. The MOS transistor M12 has a gate connected to the terminal V
The current i12 which is connected to
Flows from the drain to the source through the source to the constant current circuit I12 and the source of the MOS transistor M13. M
The OS transistor M13 has a gate connected to the terminal G, and a drain and a source connected to the source of the MOS transistor M11 and the source of the MOS transistor M12, respectively.

The constant current circuit I11 receives a current from the source of the MOS transistor M11 and a current from the drain of the MOS transistor M13 and passes a constant current to the ground potential. The constant current circuit I12 is a MOS
From the source of transistor M12 and MO
Upon receiving a current from the source of the S-type transistor M13,
A constant current is flowing to the ground potential.

The output section 11 is connected to a MOS transistor M1
Output current i + of a magnitude corresponding to the drain current i11
To the terminal I +. Further, an output current i− having a magnitude corresponding to the drain current i12 of the MOS transistor M12 is output to the terminal I−.

OTA1 and OTA having the above configuration
Operation 3 will be described.

When a differential voltage v is applied between the terminal V + and the terminal V-, the drain current i11 and the drain current i12 change according to the voltage, and the terminal I
The magnitude of the current i1 of + and the current i− of the terminal I− change. For example, when the voltage at the terminal V + is higher than the voltage at the terminal V−, the drain current i11 of the MOS transistor M11 becomes larger than the drain current i12 of the MOS transistor M12, and the node N11 to the node N
The current i13 flows toward. If the magnitudes of the currents by the constant current circuit I11 and the constant current circuit I12 are equal, the magnitude of the current i13 and the magnitude of the drain current i11
And the drain current i12 have the same current (differential current). That is, the differential current between the drain current i11 and the drain current i12 changes according to the differential voltage v, and the differential current between the output current i + and the output current i- also changes accordingly.

The drain of the MOS transistor M13
When the resistance between the sources increases, the current i13 decreases, so that the drain current i11 according to the change in the differential voltage v
And the change in the differential current between the drain current i12 and the
The change in the differential current between the output current i + and the output current i- is also small. Conversely, when the resistance between the drain and the source of the MOS transistor M13 decreases, the current i13 increases.
11 and the drain current i12 increase, and the differential current between the output current i + and the output current i- also increases.

FIG. 3 is a circuit diagram of the OTA 2 according to the first embodiment of the present invention. The difference between the OTA shown in FIG. 3 and the OTA shown in FIG. 2 is that the MOS transistor M1 shown in FIG.
3 is that the resistor R11 is replaced in FIG. The OTA shown in FIG. 3 is a MOS transistor M14
And a MOS transistor M15, a resistor R11, an output unit 12, a constant current circuit I13, and a constant current circuit I14.

The MOS transistor M14 has a gate connected to the terminal V +, and outputs a current i14 flowing from the output unit 12 to a constant current circuit I13 from the drain to the source via the source.
And the resistor R11. The MOS transistor M15 has a gate connected to the terminal V−, and allows a current i15 flowing from the output unit 12 to flow from the drain to the source to the constant current circuit I14 and the resistor R11. The resistor R11 is connected between the source of the MOS transistor M14 and M
It is connected between the source of the OS type transistor M15.

The constant current circuit I13 receives a current from the source of the MOS transistor M14 and a current from the resistor R11 and passes a constant current to the ground potential. The constant current circuit I14 receives a current from the source of the MOS transistor M15 and a current from the resistor R11,
A constant current is flowing to the ground potential.

The output section 12 is a MOS type transistor M1
4 has an output current i + corresponding to the drain current i14.
To the terminal I +. Further, an output current i− having a magnitude corresponding to the drain current i15 of the MOS transistor M15 is output to the terminal I−.

The operation of the OTA 2 having the above configuration will be described.

When a differential voltage v is applied between the terminal V + and the terminal V-, the drain current i14 and the drain current i15 change according to the voltage, and the terminal I
The magnitude of the current i1 of + and the current i− of the terminal I− change. For example, when the voltage at the terminal V + is higher than the voltage at the terminal V−, the drain current i14 of the MOS transistor M14 becomes larger than the drain current i15 of the MOS transistor M15, and the node N13 to the node N
A current flows through the resistor R11 toward. If the magnitudes of the currents by the constant current circuit I11 and the constant current circuit I12 are equal, the magnitude of the current flowing through the resistor R11 is:
The magnitude of the difference current (differential current) between the drain current i14 and the drain current i15 becomes equal. That is, the drain current i14 and the drain current i15 depend on the differential voltage v.
And the differential current between the output current i + and the output current i− changes accordingly.

The mutual conductance has a constant value proportional to the reciprocal of the resistance value of the resistor R11. Resistance R11
Increases, the current flowing through the resistor R11 decreases, so that the change in the differential current between the drain current i14 and the drain current i15 according to the change in the differential voltage v decreases, and the output current i + and the output current i The change of the differential current of-is also small. That is, the transconductance decreases. Conversely, when the resistance value of the resistor R11 decreases, the current flowing through the resistor R11 increases, so that the drain current i14 and the drain current i15 corresponding to the change in the differential voltage v are changed.
Of the output current i + and the output current i−
Also increases the differential current. That is, the transconductance increases.

Here, the operation of the first embodiment shown in FIG. 1 having the above-mentioned OTA1 to OTA3 will be described.

MOS transistor M101 and MOS transistor M102 whose gates are connected to each other
Constitutes a general current mirror circuit. That is, between the drain and the source of the MOS transistor M102, the MOS transistor M102 and the MOS transistor M101 operate as a constant current source such that the drain currents thereof are equal. Accordingly, the sum i10 of the current flowing from the output terminal I + of OTA1 and the output terminal I− of OTA2 to the drain of the MOS transistor M101 is obtained.
1 and the sum i102 of currents flowing from the output terminal I− of the OTA1 and the output terminal I + of the OTA2 to the drain of the MOS transistor M102 are equalized.
The drain-source resistance of the S-type transistor M102 changes.

When the current i101 is larger than the current i102, the drain-source resistance of the MOS transistor M102 decreases, and accordingly, the drain voltage of the MOS transistor M102 decreases and is input to the gain control terminal G of the OTA1. Voltage drops. This gives M
Since the drain-source resistance of the OS-type transistor M13 increases, the transconductance of the OTA1 decreases, and the output differential current decreases. Therefore, the output current of the output terminal I- increases, and the current i102 increases. When the current i101 is smaller than the current i102, the drain-source resistance of the MOS transistor M102 increases, and accordingly, the drain voltage of the MOS transistor M102 increases and is input to the gain control terminal G of the OTA1. The voltage rises. This gives M
Since the drain-source resistance of the OS-type transistor M13 is reduced, the transconductance of the OTA1 is increased, and the output differential current is increased. Therefore, the output current of the output terminal I− decreases, and the current i102 decreases. In this way, control is performed such that the current i101 and the current i102 become equal.

The output differential current Δi1 of OTA1 is represented by the following equation by the output voltage vd1 of the gain setting voltage output unit Vd1 and the transconductance gm1 of OTA1.

[0089]

Δi1 = gm1 × vd1 (11)

Similarly, the output differential current Δi2 of OTA2
Are the output voltage vd2 of the gain setting voltage output unit Vd2 and O
The transconductance gm2 of TA2 is represented by the following equation.

[0091]

Δi2 = gm2 × vd2 (12)

Further, from the condition that the current i101 and the current i102 become equal, the output current ip1 from the output terminal I + of the OTA1 and the output current i− from the output terminal I− of the OTA1 are obtained.
n1, the output current ip2 from the output terminal I + of OTA2,
And the output current in1 from the output terminal I− of OTA2 has the following relationship.

[0093]

(13) in1 + ip2 = ip1 + in2 ip1-in1 = ip2-in2 ∴ Δi1 = Δi2 (13)

Equation (13) is replaced by equations (11) and (12).
Is substituted, the following equation is established.

[0095]

Gm1 = gm2 × (vd2 / vd1) (14)

As can be seen from equation (14), the transconductance gm1 of OTA1 is equal to the voltage vd2 and the voltage vd1.
And the transconductance gm2 of OTA2
Is determined by OTA2 transconductance g
If m2 is a fixed value, the mutual conductance gm1 can be varied by varying the output voltages of the gain setting voltage output unit Vd1 and the gain setting voltage output unit Vd2. Then, the same voltage as the OTA1 is applied to the gain control terminal G.
The transconductance of OTA3 received by OTA
1 is substantially equal to the mutual conductance gm1.

As described above, according to the first embodiment, the transconductance can be controlled by the voltage ratio, and there is no need to control a minute differential current as in the conventional method shown in FIG. Setting accuracy can be improved.

Further, the output voltage ratio (vd2 / vd1) between the gain setting voltage output unit Vd1 and the gain setting voltage output unit Vd2 is generated according to the ratio of the internal resistance by a circuit as described below, so that the temperature characteristic can be obtained. And the variation of the output voltage ratio (vd2 / vd1) due to the variation for each individual.

FIG. 4 is a diagram showing one embodiment of the gain setting voltage output section Vd1 and the gain setting voltage output section Vd2 in the present invention. The gain setting voltage output unit Vd1 and the gain setting voltage output unit Vd2 illustrated in FIG. 4 include a constant current circuit I21 and a constant current circuit I22, a plurality of resistors R21, a plurality of analog switches SW21, and an analog switch SW22.

The analog switch SW21 and the analog switch SW22 are switches constituted by, for example, MOS transistors, and are turned on or off by a digital switch signal (not shown).
The constant current circuit I21 and the constant current circuit I22
This is a constant current circuit composed of OS type transistors and the like, and has substantially the same constant current value.

The constant current flowing from the power supply Vdd of the circuit through the constant current circuit I21 flows to the ground potential through the constant current circuit I22 through the circuit in which the resistor R21 is connected in series. At each connection point of the series circuit of the resistor R21, one analog switch SW21 and one analog switch SW22
Are connected to each other. All the other terminals of the analog switch SW21 are connected to the terminal T21, and all the other terminals of the analog switch SW22 are connected to the terminal T22. The connection point between the series circuit of the resistor R21 and the constant current circuit I22 is connected to a terminal T23.
It is connected to the. Terminal T21 is connected to the input terminal V + of OTA1, and terminal T22 is connected to the input terminal V + of OTA2.
Connected to +. The terminal T23 is connected to the input terminals V- of OTA1 and OTA2, respectively.

Since the input terminal of OTA1 to which the terminals T21 and T23 are connected is connected to the gate of the MOS transistor, the impedance between the terminals T21 and T23 is smaller than the impedance of the series circuit of the resistor R21. Big enough. Therefore, the output voltage of the gain setting voltage output unit Vd1 is determined according to the resistance value of the series circuit of the resistor R21 between the terminal T21 and the terminal T23, and the current of the constant current circuit I21 and the constant current circuit I22. It is not affected by the impedance between the terminal and the terminal T23. Similarly, the output voltage Vd2 of the gain setting voltage output unit Vd2 is determined according to the resistance value of the series circuit of the resistor R21 between the terminal T22 and the terminal T23, and the current from the constant current circuit I21 and the constant current circuit I22.

As described above, the gain setting voltage output unit Vd1
And the output voltage of the gain setting voltage output unit Vd2 is equal to the resistance R2
1 and the currents of the constant current circuit I21 and the constant current circuit I22, the output voltage ratio (vd2 / vd1) is determined by the resistance value between the terminals T21 and T23 and the terminals T22 and T23. It is determined by the ratio with the resistance value between them. Since the currents of the constant current circuit I21 and the constant current circuit I22 are common, the output voltage ratio (vd2 / vd1)
In this case, the fluctuation of the current by the constant current circuit I21 and the constant current circuit I22 has no effect.

Generally, the ratio of the temperature characteristics of the resistors formed inside the same IC is extremely small, and the variation in the ratio of the resistance values among the individual ICs is also small. Therefore, the output voltage ratio (vd2 / vd1) determined by the resistance value ratio is less susceptible to fluctuations due to temperature characteristics of the resistance and variations in the resistance value for each individual. That is, the voltages vd1 and vd2 are supplied by the gain setting voltage output units Vd1 and Vd2 shown in FIG.
The transconductance of A1 and OTA3 hardly fluctuates due to the output voltage ratio (vd2 / vd1), and is exclusively affected by the fluctuation of the transconductance gm2 of OTA2.

The transconductance gm2 of OTA2 is
It is determined according to the resistance value r11 of the resistor R11 in FIG. 3, and becomes (1 / r11). Therefore, a load connected to the output terminal I + and the output terminal I− of the OTA3 is connected to the resistor R11.
If the same internal resistance of the IC is used, the mutual conductance g
The change in m2 and the change in load resistance can be offset by the ratio of the resistance. For example, the output voltage Vou of OTA3
t is represented by the following equation using the load resistance RL.

[0106]

Vout = RL × (gm3 × Vin) = RL × gm2 × (vd2 / vd1) × Vin = (RL / r11) × (vd2 / vd1) × Vin (15)

As can be seen from equation (15), the output voltage Vout of OTA3 is determined according to the output voltage ratio (vd2 / vd1) and the resistance ratio (RL / r11). Thus, FIG.
The voltage vd1 and the voltage vd2 are supplied by the gain setting voltage output unit Vd1 and the gain setting voltage output unit Vd2, and the output voltage Vout of the OTA3 is obtained by a resistive load. It is less susceptible to fluctuations due to variations in resistance value for each, and the accuracy of gain setting is improved.

The gain setting voltage output section Vd1 shown in FIG.
By using the gain setting voltage output unit Vd2, the transconductance gm3 of the OTA3 can be set with high accuracy when the load of the OTA3 is not a resistor.

FIG. 5 is a diagram showing another embodiment of the gain setting voltage output section Vd1 and the gain setting voltage output section Vd2 in the present invention. The gain setting voltage output unit Vd1 and the gain setting voltage output unit Vd2 shown in FIG. 5 include a reference voltage source 21, a voltage / current converter 22, a voltage / current converter 23, a resistor R24 inside the IC, a plurality of resistors R22 inside the IC, Resistance R2
3. It comprises a reference resistor R25 outside the IC, a plurality of analog switches SW23 and an analog switch SW24.

The reference voltage source 21 is a voltage source that outputs a highly accurate voltage by, for example, a band gap circuit or the like.

The voltage-to-current converter 22 and the voltage-to-current converter 23 convert the voltage input from the reference voltage source 21 into a current corresponding to a predetermined resistance value and output it. For example, it is constituted by a circuit as shown in FIG. FIG. 6 is a circuit diagram showing one embodiment of the voltage-current converter 22. The voltage-to-current converter 22 shown in FIG.
4. It is composed of a MOS transistor M221.

The input terminal + of the operational amplifier 221 is applied with a reference voltage from the reference voltage source 21 using the power supply voltage Vdd as a reference potential.
Is connected to a connection point between the resistor R24 and the source of the MOS transistor M221. The source of the MOS transistor M221 is connected to the power supply voltage Vdd via the resistor R24.
To the gate, the output voltage of the differential amplifier 221 is applied to the gate, and the drain current is
Is output as the output current.

The MOS transistor M221 is, for example, a p-channel MOS transistor, and the source current increases as the gate potential decreases.
When the source current increases, the voltage drop due to the resistor R24 increases, and the voltage at the input terminal − of the operational amplifier 221 decreases, the output voltage of the operational amplifier 221 increases,
The gate potential of the MOS transistor M221 increases. As a result, the source current of the MOS transistor M221 decreases. Conversely, when the source current decreases, the voltage drop due to the resistor R24 decreases, and the voltage at the input terminal − of the operational amplifier 221 increases, the output voltage of the operational amplifier 221 decreases, and the gate of the MOS transistor M221 decreases. The potential drops. As a result, the source current of the MOS transistor M221 increases. Thus, the source current of the MOS transistor M221 is controlled to a constant current.

The output current i22 of the voltage-current converter 22 is
The output voltage Vr of the reference voltage source 21 and the resistance value r of the resistor R24
24 is represented by the following equation.

[0115]

I16 = Vr / r24 (16)

The voltage-current converter 23 is also a voltage-current converter 22.
And a voltage-current converter 23.
Is represented by the following equation by the output voltage Vr of the reference voltage source 21 and the resistance value r25 of the external reference resistor R25.

[0117]

I23 = Vr / r25 (16)

The output current i of the voltage-current converter 22 described above
22 flows to the ground potential through the series circuit of the resistor R22. An analog switch SW2 is connected to each connection point of the resistor R22.
3 is connected to one terminal, and all the other terminals are connected to a terminal T24. One of the connection points of the resistor R22 is connected to the terminal T25. The voltage generated between the terminal T24 and the terminal T25 is output to the OTA2 as the output voltage vd2 of the gain setting voltage output unit Vd2. That is, the terminal T24 and the terminal T25 are connected to the input terminal V + and the input terminal V- of the OTA2, respectively.

The output current i23 of the voltage-current converter 23 flows to the ground potential through a series circuit of the resistor R23. One terminal of the analog switch SW24 is connected to each connection point of the resistor R23, and all the other terminals are connected to the terminal T26. One of the connection points of the resistor R23 is connected to the terminal T27. Terminal T2
6 and the terminal T27 are output to the OTA1 as the output voltage vd1 of the gain setting voltage output unit Vd1. That is, the terminals T26 and T27
1 input terminal V + and input terminal V-.

The resistance value r22a between the terminals T24 and T25 determined by the opening and closing of the analog switch SW23 gives
The output voltage vd2 of the gain setting voltage output unit Vd2 is represented by the following equation.

[0121]

Vd2 = i22 × r22a = Vr × (r22a / r24) (18)

The output voltage vd1 of the gain setting voltage output unit Vd1 is expressed by the following equation based on the resistance r23a between the terminals T26 and T27 determined by the opening and closing of the analog switch SW24.

[0123]

(19) vd1 = i23 × r23a = Vr × (r23a / r25) (19)

Equations (18) and (19) are replaced by equation (14)
, The mutual conductance gm1 is expressed by the following equation.

[0125]

Gm1 = gm2 × (r22a / r24) × (r23a / r25) = (r23a / r11) × (r22a / r24) / r25 (20)

As can be seen from equation (20), the transconductance gm1 is determined by the ratio of the internal resistance (r23a / r11)
And (r22a / r24) and the conductance (1 / r25) of the external reference resistance. Therefore, by using a highly accurate resistor for the external reference resistor R25, the transconductance gm1 can be set with high accuracy.

The embodiment of the gain setting voltage output unit Vd1 and the gain setting voltage output unit Vd2 according to the present invention is the same as that of the above-described 2
It is not limited to one example, and various other forms are possible. In the above-described embodiment, the voltage is generated in the series resistor using the current source. For example, the voltage of the voltage source is divided by an analog switch and a series resistor circuit as shown in FIG. And voltage vd2
Can also be generated. Also, the resistor R1 of the OTA2
If a high-precision external reference resistor is used for 1, the circuit shown in FIG. 4 can be used instead of the circuit shown in FIG. 5.

As described above, according to the first embodiment of the present invention, it is possible to reduce a change in gain due to a temperature characteristic, individual variation, and the like by using a simpler circuit than the conventional method. Further, since the transconductance can be controlled by the voltage ratio, it is not necessary to control a minute differential current as in the conventional method, so that the setting accuracy of the transconductance can be improved.

<Second Embodiment> Next, a second embodiment of the present invention will be described. In the second embodiment, the differential output of the OTA in the first embodiment is changed to a single output.

FIG. 7 is a circuit diagram showing a second embodiment of the variable gain amplifier circuit according to the present invention. The variable gain amplifier circuit shown in FIG.
It has TA6. The transconductance setting circuit 101 includes OTA4 and OTA5, a MOS transistor M103 and a MOS transistor M104,
Gain setting voltage output section Vd4 and gain setting voltage output section Vd5
have.

OTA4 has an input terminal V + and an input terminal V-
The voltage from the gain setting voltage output unit Vd4 is applied between the MOS transistor M1 and the gain control terminal G.
04 is applied. The output terminal I is connected to the drain of the MOS transistor M103. In the OTA5, a voltage from the gain setting voltage output unit Vd5 is applied between the input terminal V + and the input terminal V-. The output terminal I is a MOS transistor M10
4 is connected to the drain. The MOS transistor M103 has a drain connected to the output terminal I of the OTA4 and a source grounded. The drain and gate are connected, and this gate is
It is connected to the gate of the type transistor M104. M
The OS type transistor M104 is connected to the output terminal I of the OTA5.
Is connected to the drain, and the source is grounded. The gate is connected to the gate of the MOS transistor M103. Furthermore, when the drain voltage is OTA
4 and is output to the gain control terminal G of the OTA 6 as a gain control signal S1.

The OTA 6 has an input terminal V + and an input terminal V−
And an input signal voltage Vin is applied between the two, and a gain control signal S1 from the transconductance setting circuit 101 is input to the gain control terminal G.

The internal configuration of OTA4 and OTA6 will be described.

FIG. 8 is a circuit diagram of OTA4 and OTA6 in the second embodiment of the present invention. O shown in FIG.
The TA has MOS transistors M16 to M18, an output unit 13, a constant current circuit I15, and a constant current circuit I16.

The output section 13 is connected to a MOS transistor M1
6 and the MOS transistor M1
The output current i having a magnitude corresponding to the differential current with respect to the drain current i17 is output to the terminal I.

OTA MOS type transistors M16 to M18, constant current circuit I15 and constant current circuit I shown in FIG.
16 is an OTA MOS transistor M1 shown in FIG.
1 to M13, constant current circuit I11 and constant current circuit I12
Components having the same function corresponding to
Since they have the same connection relationship, a description thereof will be omitted.

The operation of OTA4 and OTA6 shown in FIG.
Is the same as the operation of the OTA shown in FIG. 2 except that the size of the OTA is the size corresponding to the differential current between the current i16 and the current i17, and the description thereof is omitted.

The OTA5 is the same as the OTA2 shown in FIG. 3 except that the output section 12 of the OTA2 shown in FIG.
It is composed of the same components as. The magnitude of the current output from the terminal I by the output unit of the OTA5 has a magnitude corresponding to the differential current between the current i14 and the current i15.

The change amount Δi of the output current with respect to the change amount Δv of the differential voltage v input to the OTA4 to OTA6 is expressed by the following equation in the same way as the equation (1) by the mutual conductance gm.

[0140]

Δi = gm × Δv (21)

Here, the operation of the second embodiment shown in FIG. 7 will be described.

MOS transistor M103 and MOS transistor M104 whose gates are connected to each other
Constitutes a general current mirror circuit. That is, between the drain and the source of the MOS transistor M104, the MOS transistor M104 operates as a constant current source such that the drain currents of the MOS transistor M103 become equal. Therefore, the current i4 flowing from the output terminal of the OTA4 to the drain of the MOS transistor M103 is equal to the current i5 flowing from the output terminal of the OTA5 to the drain of the MOS transistor M104. The resistance changes.

When the current i4 is larger than the current i5, MO
The drain-source resistance of the S-type transistor M104 is reduced, and accordingly, the MOS-type transistor M10
4 decreases, and the gain control terminal G of OTA4
The voltage input to is reduced. As a result, the drain-source resistance of the MOS transistor M18 increases, so that the transconductance of the OTA4 decreases,
The current i4 decreases. When the current i4 is smaller than the current i5, the drain-source resistance of the MOS transistor M104 increases, and accordingly, the drain voltage of the MOS transistor M104 increases, and the OTA4
, The voltage input to the gain control terminal G increases. As a result, the resistance between the drain and the source of the MOS transistor M18 decreases, so that the transconductance of the OTA4 increases and the current i4 increases. In this way, control is performed so that the current i4 and the current i5 become equal.

Under the condition that the currents i4 and i5 become equal, the gain setting voltage output section Vd4 is obtained in the same manner as in the equation (14).
, The output voltage vd5 of the gain setting voltage output unit Vd5, and the transconductance gm5 of the OTA5, the transconductance gm4 of the OTA4 is expressed by the following equation.

[0145]

Gm4 = gm5 × (vd5 / vd4) (22)

As can be seen from equation (22), the transconductance can be controlled by the voltage ratio also in the second embodiment. Therefore, similarly to the first embodiment, it is not necessary to control a minute differential current as in the conventional method shown in FIG. 19, so that the accuracy of setting the mutual conductance can be improved.

Also, the circuits shown in FIGS. 4 and 5 can be used in the gain setting voltage output section Vd4 and the gain setting voltage output section Vd5 in the second embodiment. Therefore, by using these circuits, as in the first embodiment, the gain of the variable gain amplifying circuit is hardly affected by the temperature characteristics and individual variations, and the accuracy of the gain can be improved.

In the circuit shown in FIG. 7, OT
Although the output currents of A4 to OTA6 are limited to the discharge current, the present invention is not limited to this, and the output currents of OTA4 to OTA6 may be sink currents.

In this case, for example, the MOS transistor M103 and the MOS transistor M104 are p-channel MOS transistors, and their sources are connected to the power supply voltage.
An inverter circuit may be inserted between the drain of OTA4 and the gain control terminals of OTA4 and OTA6. Accordingly, when the current i4 is larger than the current i5, the drain-source resistance of the MOS transistor M104 decreases, and accordingly, the drain voltage of the MOS transistor M104 increases, and the output of the inverter circuit decreases. As a result, the transconductance of OTA4 decreases, and current i4 decreases. Conversely, when the current i4 is smaller than the current i5, the drain of the MOS transistor M104
The source-to-source resistance increases, and accordingly, the drain voltage of the MOS transistor M104 decreases, the output of the inverter circuit increases, the transconductance of the OTA4 increases, and the current i4 increases. In this way, even when the output currents of OTA4 to OTA6 are sink currents, control can be performed so that currents i4 and i5 are equal.

As described above, according to the second embodiment of the present invention, even if the variable gain amplifier circuit has a single output, the same effect as that of the first embodiment can be obtained.

<Third Embodiment> Next, a third embodiment of the present invention will be described.

FIG. 9 is a circuit diagram showing a third embodiment of the variable gain amplifier circuit according to the present invention. The variable gain amplifier circuit in FIG. 9 has OTA11 and OTA12, terminal T1 and terminal T2.

The OTAs 11 and 12 are, for example, OTAs having the same configuration as the OTA shown in FIG. Input signals Vin of the same polarity are input to the input terminals V + and V− of the OTA11 and OTA12. The gain control signal S11 is input to the gain control terminal G of the OTA11, and the gain control signal S12 is input to the gain control terminal G of the OTA12. Further, the output terminal I + of the OTA11 and the output terminal I− of the OTA12 are connected to the terminal T1, respectively, and the output terminal I− of the OTA11 and the output terminal I + of the OTA12 are connected to the terminal T2.

The transconductance gm1 of OTA11
1, the output current i1, O from the output terminal I + of the OTA11.
The output current it1 from the terminal T1 can be represented by the following equation by the differential output current Δi1 of the TA11, the mutual conductance gm12 of the OTA12, the output current i2 from the output terminal I + of the OTA12, and the differential output current Δi2 of the OTA11. it can.

[0155]

## EQU23 ## it1 = i1 + i2-.DELTA.i2 = i1 + i2-gm12.times.Vin (23)

The output current it2 from the terminal T2 can be expressed by the following equation.

[0157]

[Formula 24] it2 = i2 + i1-Δi1 = i2 + i1-gm11 × Vin (24)

From the expressions (23) and (24), the terminal T
1 and the differential current Δi12 output from the terminal T2 are expressed by the following equation.

[0159]

Δi12 = it1-it2 = (gm11−gm12) × Vin (25)

As can be seen from equation (23), the transconductance of the variable gain amplifier circuit composed of OTA11, OTA12, terminal T1 and terminal T2 shown in FIG.
11-gm12). When a small mutual conductance is set in the variable gain amplifier circuit, the mutual conductance may be set so that the difference between the mutual conductance gm11 and the mutual conductance gm12 becomes small, and the OTA11 or OTA1 is set.
It is not necessary to set the transconductance of the second device to a very small value. Therefore, unlike the case of the conventional variable gain amplifier circuit, the setting of the minute transconductance is not limited by the amplitude range of the differential input voltage.

When a large mutual conductance is set in the variable gain amplifier circuit, each mutual conductance may be set so that the difference between mutual conductance gm11 and mutual conductance gm12 becomes large. In this case, there is a possibility that a small transconductance may be set in one OTA, but the terminals T1 and T
Since the current flowing through the OTA 2 is dominated by the current of the OTA having a large transconductance, the waveform distortion generated in the current of the OTA having a small transconductance has a small effect. Therefore, according to the variable gain amplifying circuit according to the third embodiment, the transconductance of a wide variable range can be set without being limited by the amplitude range of the input voltage.

As described above, according to the third embodiment of the present invention, as in the case of the conventional variable gain amplifier circuit, the setting of the minute transconductance is restricted by the amplitude range of the differential input voltage. And the gain can be set in a wide variable range without being limited by the amplitude range of the input voltage.

<Fourth Embodiment> Next, a fourth embodiment of the present invention will be described.

FIG. 10 is a circuit diagram showing a fourth embodiment of the variable gain amplifier circuit according to the present invention. The variable gain amplifier circuit in FIG. 10 has OTA13 to OTA16, a resistor 30, a terminal T1, and a terminal T2.

OTAs 13 to 16 are, for example, OTAs having the same configuration as the OTA shown in FIG. O
Input signals Vin are input to the input terminals V + and V- of the TA13 and OTA14 with the same polarity. The gain control signal S11 is input to the gain control terminal G of the OTA13, and the gain control signal S12 is input to the gain control terminal G of the OTA14. Furthermore, O
Output terminal I + of TA13 and output terminal I of OTA14
Are connected to the terminal T1a, respectively, and the output terminal I− of the OTA13 and the output terminal I + of the OTA14 are connected to the terminal T2a.
Connected to each other. Terminal T1a and terminal T2
a is connected to the ground potential via the resistor 30. Input terminals V + of OTA15 and OTA16 are connected to terminal T1a, respectively, and input terminal V− is connected to terminal T2.
a. The gain control signal S11 is input to the gain control terminal G of the OTA 15, and the OTA 15
A gain control signal S12 is input to the 16 gain control terminals G. Further, the output terminal I + of the OTA 15 and the output terminal I− of the OTA 16 are connected to the terminal T1b, respectively, and the output terminal I− of the OTA 15 and the output terminal I + of the OTA 16 are connected to the terminal T2b.

In the fourth embodiment, the variable gain amplifier circuits in the third embodiment are cascaded in multiple stages via resistors as current-to-voltage conversion means. In the circuit diagram shown in FIG. 10, the variable gain amplifier circuit of FIG. 9 is cascaded only in two stages, but is not limited to this example, and can be cascaded in more stages. OTA15 and O
The differential voltage Vin2 input to the TA16 can be expressed by the following equation by the transconductance gm13 of the OTA13, the transconductance gm14 of the OTA14, and the resistance value r30 of the resistor 30.

[0167]

## EQU26 ## Vin2 = (gm13-gm14) × Vin × r30 (26)

From equation (26), the transconductance gm15 of OTA15 and the transconductance gm of OTA16
The differential current Δi12 output from the terminal T1 and the terminal T2 is represented by the following equation.

[0169]

Δi12 = (gm15−gm16) × Vin2 = (gm13−gm14) × (gm15−gm16) × r30 × Vin (27)

As can be seen from equation (27), according to the fourth embodiment, the transconductance obtained in the third embodiment is obtained by connecting the transconductance of each cascaded OTA to the OTA of each stage. It is the product of the resistance value of the resistor 30 and the resistance value. As described above, since the total transconductance is the product of the mutual conductance of each stage, the total transconductance can be varied over a wider range than the mutual conductance obtained in the third embodiment.

In the fourth embodiment shown in FIG. 10, a gain control signal S11 common to the gain control terminals G of the OTA13 and OTA15 is input, and a gain control signal common to the gain control terminals G of the OTA14 and OTA16. Although S12 is input, the present invention is not limited to this example, and a different gain control signal can be given to each.

In the third and fourth embodiments described above, the gain control signal S11 and the gain control signal S12 can be generated by the mutual conductance setting circuit described in the first embodiment.

FIG. 11 is a circuit diagram showing a transconductance control circuit for generating a gain control signal S11 and a gain control signal S12 in the third and fourth embodiments of the present invention. The transconductance control circuit shown in FIG. 11 includes a transconductance setting circuit 102, a transconductance setting circuit 103, and a gain setting circuit 2
00. This mutual conductance setting circuit 1
02 denotes OTA101 and OTA2, MOS transistor M101 and MOS transistor M102,
It has a gain setting voltage output section 20A. Further, the transconductance setting circuit 103 includes OTA103 and OTA103.
TA4, a MOS transistor M103 and a MOS transistor M104, and a gain setting voltage output unit 20B.

The mutual conductance setting circuit 102 and the mutual conductance setting circuit 103 have the same components as those in the first embodiment described with reference to FIG. 1, and a description thereof will be omitted. Further, since the gain setting voltage output section 20A and the gain setting voltage output section 20B have the same components as the circuit described in FIG. 4, the description thereof will be omitted. Note that the gain setting signal S201 and the gain setting signal S2 input to the gain setting voltage output section 20A and the gain setting voltage output section 20B, respectively.
02 is a digital signal for controlling the opening and closing of the analog switch.

The gain setting circuit 200 has a gain setting signal S20 having a difference corresponding to the digital gain setting signal S200.
1 and a logic circuit that generates a gain setting signal S202. In transconductance setting circuit 102 and transconductance setting circuit 103, gain control signal S11 and gain control signal S12 corresponding to gain setting signal S201 and gain setting signal S202 are generated, and according to the difference between these gain control signals, 9 and the transconductance of the variable gain amplifying circuit shown in FIG. 10 are determined, so that the gain setting signal S20 depends on the gain setting signal S200.
By controlling the difference between 1 and the gain setting signal S202, the mutual conductance of the variable gain amplifier circuit is controlled. That is, the mutual conductance of the variable gain amplifier circuit shown in FIGS. 9 and 10 is controlled according to gain setting signal S200.

The gain control signal S11 and the gain control signal S12 are supplied to the variable gain amplifying circuits shown in FIGS. 9 and 10 by the transconductance control circuit shown in FIG. 11, so that the variable gain range of the variable gain amplifying circuit can be increased. In addition to being able to be expanded, the gain to be set is less likely to be affected by fluctuations in temperature and individual variation, and the accuracy of gain setting can be improved.

<Fifth Embodiment> Next, a fifth embodiment of the present invention will be described. In the fifth embodiment, the OTA in the third embodiment is changed from a differential output to a single output.

FIG. 12 is a circuit diagram showing a fifth embodiment of the variable gain amplifier circuit according to the present invention. The variable gain amplifier circuit of FIG. 12 has OTA17 and OTA18, and a terminal T.

The OTAs 17 and 18 are, for example, OTAs having the same configuration as the OTA shown in FIG. The input signals Vin are input to the input terminals V + and V− of the OTA 17 and OTA 18 so as to have opposite polarities. The gain control signal S11 is input to the gain control terminal G of the OTA 17, and the OTA 18
The gain control signal S12 is input to the gain control terminal G of the. Further, the output terminal of the OTA 17 and the output terminal of the OTA 18 are connected to the terminal T, respectively.

The transconductance gm1 of OTA17
7. The output current it from the terminal T can be expressed by the following equation by the output current i17 of the OTA 17, the transconductance gm18 of the OTA 18, and the output current i18 of the OTA 18.

[0181]

## EQU28 ## it = i17-i18 = (gm17-gm18) × Vin (28)

As can be seen from equation (28), the transconductance of the variable gain amplifier circuit including the OTA 17, the OTA 18 and the terminal T shown in FIG. 12 is (gm17-gm).
18). To set a small mutual conductance in the variable gain amplifier circuit, the mutual conductance gm17 and the mutual conductance gm1 are set.
The mutual conductance of the OTA 17 or the OTA 18 need not be independently set to a very small value. Therefore, unlike the case of the conventional variable gain amplifier circuit, the setting of the minute transconductance is not limited by the amplitude range of the differential input voltage.

When a large mutual conductance is set in the variable gain amplifier circuit, the mutual conductance may be set so that the difference between mutual conductance gm17 and mutual conductance gm18 becomes large. In this case, a small transconductance may be set in one of the OTAs. However, since a current flowing through the terminal T is dominated by a current of the OTA set with a large transconductance, a small transconductance is set. The effect of the waveform distortion generated on the OTA current is small. Therefore, according to the variable gain amplifier circuit of the fifth embodiment, it is possible to set the transconductance in a wide variable range without being limited by the amplitude range of the input voltage.

As described above, according to the fifth embodiment of the present invention, even when the variable gain amplifier circuit has a single output, the same effect as that of the third embodiment can be obtained.

<Sixth Embodiment> Next, a sixth embodiment of the present invention will be described.

FIG. 13 is a circuit diagram showing a sixth embodiment of the variable gain amplifier circuit according to the present invention. The variable gain amplifier circuit of FIG. 13 includes OTA19 to OTA22, a resistor R30,
It has a terminal T.

The OTAs 19 to 22 are, for example, OTAs having the same configuration as the OTA shown in FIG. O
The input terminals V + and V- of TA19 and OTA20 have input signals Vin so as to have polarities opposite to each other.
Is entered. Also, the gain control terminal G of the OTA 19
, A gain control signal S11 is input, and a gain control terminal S of the OTA 20 is input with a gain control signal S12. Further, the output terminals of OTA19 and OTA20 are connected to terminal Ta, respectively. The terminal Ta is connected to the resistor 30
To the ground potential. The input terminal V + of the OTA 21 and the input terminal V− of the OTA 22 are connected to the terminal Ta, respectively, and the input terminals V− and O of the OTA 21 are connected.
The input terminals V + of TA22 are grounded. Further, a gain control signal S1 is supplied to a gain control terminal G of the OTA 21.
1 is input, and the gain control signal S12 is input to the gain control terminal G of the OTA22. In addition, OTA21
And the output terminals of the OTA 22 are connected to the terminal Tb.

In the sixth embodiment, the variable gain amplifier circuits in the fifth embodiment are cascaded in multiple stages via current-voltage conversion means. In the circuit diagram shown in FIG. 13, the variable gain amplifier circuit of FIG. 12 is cascaded only in two stages, but is not limited to this example, and can be cascaded in more stages. The differential voltage Vin2 input to the OTA 21 and the OTA 22 is based on the transconductance gm19 of the OTA19 and the transconductance gm of the OTA20.
20, can be represented by the following equation by the resistance value r30 of the resistor R30.

[0189]

[Expression 29] Vin2 = (gm19−gm20) × Vin × r30 (29)

From the equation (29), the transconductance gm21 of OTA21 and the transconductance gm of OTA22 are obtained.
According to 22, the current it output from the terminal T is expressed by the following equation.

[0191]

It = (gm21−gm22) × Vin2 = (gm19−gm20) × (gm21−gm22) × r30 × Vin (30)

As can be seen from equation (30), according to the sixth embodiment, the transconductance obtained in the fifth embodiment is obtained by connecting the transconductance of each cascaded OTA to the OTA of each stage. And the resistance of the resistor R30. As described above, since the total transconductance is the product of the mutual conductances of the respective stages, the total transconductance can be varied over a wider range than in the fifth embodiment.

In the sixth embodiment shown in FIG. 13, the common gain control signal S11 is input to the gain control terminals G of the OTA19 and OTA21, and the common gain control signal S11 is applied to the gain control terminals G of the OTA20 and OTA22. Although S12 is input, the present invention is not limited to this example, and a different gain control signal can be given to each.

In the fifth and sixth embodiments described above, the gain control signal S11 and the gain control signal S12 can be generated by the mutual conductance setting circuit described in the second embodiment.

FIG. 14 is a circuit diagram showing a transconductance control circuit for generating gain control signal S11 and gain control signal S12 in the fifth and sixth embodiments of the present invention. The transconductance control circuit of FIG. 14 includes a transconductance setting circuit 104, a transconductance setting circuit 105, and a gain setting circuit 2.
00. This mutual conductance setting circuit 1
04 denotes OTA105 and OTA6, MOS transistor M105 and MOS transistor M106,
It has a gain setting voltage output section 20C. Further, the transconductance setting circuit 105 includes the OTA 107 and O
TA8, a MOS transistor M107 and a MOS transistor M108, and a gain setting voltage output unit 20D.

The mutual conductance setting circuit 104 and the mutual conductance setting circuit 105 have the same components as those in the second embodiment described with reference to FIG. 7, and therefore description thereof will be omitted. The gain setting voltage output section 20C and the gain setting voltage output section 20D have the same components as the gain setting voltage output section 20C and the gain setting voltage output section 20D described with reference to FIG. Is also omitted. The gain setting circuit 200 is the same as the gain setting circuit 20 described in FIG.
0 is the same component.

By supplying the gain control signal S11 and the gain control signal S12 to the variable gain amplifier circuits of FIGS. 12 and 13 by the transconductance control circuit shown in FIG. 14, the gain variable range of the variable gain amplifier circuit can be conventionally reduced. In addition to being able to be expanded, the gain to be set is less likely to be affected by fluctuations in temperature and individual variation, and the accuracy of gain setting can be improved.

[0198]

According to the variable gain amplifier circuit of the present invention, it is possible to reduce the fluctuation of the gain due to the temperature characteristic and the variation of each individual by a simple circuit, and to set the gain with high accuracy.
Further, the gain can be varied over a wide range without being limited by the amplitude range of the input voltage.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a variable gain amplifier circuit according to the present invention.

FIG. 2 is a circuit diagram of OTA1 and OTA3 in the first embodiment of the present invention.

FIG. 3 is a circuit diagram of OTA2 according to the first embodiment of the present invention.

FIG. 4 is a diagram showing one embodiment of a gain setting voltage output unit Vd1 and a gain setting voltage output unit Vd2 in the present invention.

FIG. 5 is a diagram showing another embodiment of the gain setting voltage output unit Vd1 and the gain setting voltage output unit Vd2 in the present invention.

FIG. 6 is a circuit diagram showing one embodiment of a voltage-current converter 22.

FIG. 7 is a circuit diagram showing a second embodiment of the variable gain amplifier circuit according to the present invention.

FIG. 8 is a circuit diagram of OTA4 and OTA6 in the second embodiment of the present invention.

FIG. 9 is a circuit diagram showing a third embodiment of the variable gain amplifier circuit according to the present invention.

FIG. 10 is a circuit diagram showing a fourth embodiment of the variable gain amplifier circuit according to the present invention.

FIG. 11 shows a gain control signal S11 and a gain control signal S according to a third embodiment and a fourth embodiment of the present invention.
FIG. 9 is a circuit diagram showing a transconductance control circuit that generates a circuit 12;

FIG. 12 is a circuit diagram showing a fifth embodiment of the variable gain amplifier circuit according to the present invention.

FIG. 13 is a circuit diagram showing a sixth embodiment of the variable gain amplifier circuit according to the present invention.

FIG. 14 shows a gain control signal S11 and a gain control signal S according to a fifth embodiment and a sixth embodiment of the present invention.
FIG. 9 is a circuit diagram showing a transconductance control circuit that generates a circuit 12;

FIG. 15 is a diagram illustrating an integral element of a filter circuit configured using OTA.

FIG. 16 is a diagram illustrating a first-order low-pass filter configured using OTA.

FIG. 17 is a diagram illustrating a sine wave oscillation circuit configured using OTA.

FIG. 18 is a diagram showing a conventional first circuit for setting transconductance.

FIG. 19 is a diagram showing a conventional second circuit for setting transconductance.

[Explanation of symbols]

OTA1 to OTA22 ... OTA, M11 to M108 ... M
OS type transistors, 11 to 13... Output part, R11 to R
Reference numerals 30, 30: resistor, SW21 to SW24: analog switch, I11 to I22: constant current circuit, 21: reference voltage source, 22, 23: voltage / current converter, Vd1 to Vd5, 20A
２０20D: gain setting voltage output unit, 200: gain setting circuit, T, T1, T2 ... terminals.

Continued on the front page F term (reference) 5J090 AA01 AA12 AA22 AA51 CA02 CA15 CA21 CA32 CA61 CA88 CN04 FA09 FA10 FN01 FN06 FN07 HA10 HA25 HA29 HA38 HN15 HN17 KA02 KA05 KA09 KA12 KA42 KA48 KA49 MA19 A02A01 CA32 CA61 CA88 FA09 FA10 HA10 HA25 HA29 HA38 KA02 KA05 KA09 KA12 KA42 KA49 MA19 TA01 5J100 AA02 AA03 AA14 AA18 BA06 BB02 BB09 BB15 BB22 BC02 CA02 CA05 CA11 CA19 CA33 DA06 EA02

Claims (7)

[Claims] 1. A first and a second transistor, to which a differential input voltage is inputted to a control terminal, connected between the first transistor and the second transistor, and a gain control signal at a control terminal. A third transistor that is input and outputs a differential current between a first output current and a second output current corresponding to a current flowing through the first transistor and a current flowing through the second transistor, respectively. A first amplifier circuit having an output unit, fourth and fifth transistors each receiving a first and a second voltage at a control terminal, and between the fourth transistor and the fifth transistor. And a control terminal to which the gain control signal is input, corresponding to a current flowing through the fourth transistor and a current flowing through the fifth transistor, respectively. A second amplifier circuit having an output unit for outputting a differential current between the first current and a second current smaller than the first current; and a third and fourth voltage input to the control terminal, respectively. Seventh and eighth transistors, a resistance element connected between the seventh transistor and the eighth transistor, a current flowing through the seventh transistor, and a current flowing through the eighth transistor. A third amplifier circuit having an output unit for outputting a differential current between a third current corresponding to the third current and a fourth current smaller than the third current, respectively, and the first current and the fourth current. And a current mirror circuit that generates the gain control signal in accordance with a combined current of the second current and the second current and the third current. 2. A first and a second transistor, to which a differential input voltage is inputted to a control terminal, connected between the first transistor and the second transistor, and a gain control signal at a control terminal. A first amplifier circuit including a third transistor to be input, and an output unit that outputs an output current corresponding to a current flowing through the first transistor and a current flowing through the second transistor; Fourth and fifth transistors, each having a second voltage input to a control terminal, connected between the fourth transistor and the fifth transistor, and the gain control signal input to a control terminal. A second amplifier circuit having a sixth transistor and an output unit for outputting a first current corresponding to a current flowing through the fourth transistor and a current flowing through the fifth transistor A seventh and an eighth transistor, the third and fourth voltages of which are respectively input to control terminals, a resistive element connected between the seventh and the eighth transistors, A third amplifier circuit having an output unit for outputting a second current corresponding to the current flowing through the transistor and the current flowing through the eighth transistor; and the first current and the second current. A current mirror circuit for generating the gain control signal in response to the current mirror circuit. 3. The method according to claim 1, wherein the first amplifier circuit includes the first and second amplifiers.
Having first and second current sources for supplying current to the respective transistors, and wherein the second amplifier circuit includes the fourth amplifier.
And third and fourth current sources for supplying current to the fifth and fifth transistors, respectively, and the third amplifier circuit supplies fifth and fourth current sources for supplying current to the seventh and eighth transistors, respectively. The variable gain amplifier circuit according to claim 1, further comprising a sixth current source. 4. A first transistor connected between the first and second transistors for receiving a differential input voltage to a control terminal and a first gain connected to the control terminal. A third transistor to which a control signal is input; and a differential current between a first current and a second current corresponding to a current flowing through the first transistor and a current flowing through the second transistor, respectively. A first amplifier circuit having an output unit that performs the differential input voltage, and a fourth and a fifth terminals that receive the differential input voltage at a control terminal.
Transistor, the fourth transistor and the fifth transistor
And a current flowing through the fourth transistor and a current flowing through the fifth transistor, the sixth transistor being connected between the other transistors and having a control terminal to which the second gain control signal is input, respectively. Third current and fourth
A second amplifying circuit having an output unit for outputting a differential current with respect to the currents of the first and second currents; a gain control circuit for generating the first and second gain control signals; A variable gain amplifier circuit comprising: a first output terminal for supplying a combined current with a current; and a second output terminal for supplying a combined current of the second current and the third current. . 5. A first transistor connected between a first transistor and a second transistor for receiving a differential input voltage to a control terminal, a first gain connected to the control terminal, and a first gain connected to the control terminal. A third transistor to which a control signal is input; and a differential current between a first current and a second current corresponding to a current flowing through the first transistor and a current flowing through the second transistor, respectively. A first amplifier circuit having an output unit that performs the differential input voltage, and a fourth and a fifth terminals that receive the differential input voltage at a control terminal.
Transistor, the fourth transistor and the fifth transistor
A sixth transistor connected between the first and second transistors and having a control terminal to which a second gain control signal is input, and corresponding to a current flowing through the fourth transistor and a current flowing through the fifth transistor, respectively. Third current and fourth
A second amplifier circuit having an output unit that outputs a differential current with the current of the second current, a composite current of the first current and the fourth current, the second current, and the third current. A voltage generating circuit that generates a differential voltage according to the combined current of the first and second transistors, seventh and eighth transistors to which the differential voltage is input to a control terminal, the seventh transistor and the eighth transistor, And a fifth terminal corresponding to a current flowing through the seventh transistor and a current flowing through the eighth transistor, the ninth transistor being connected between the first and second transistors and having the control terminal receiving the first gain control signal. Current and sixth
A third amplifier circuit having an output unit for outputting a differential current with respect to the currents of the first and second current sources;
, A twelfth transistor connected between the tenth transistor and the eleventh transistor, the control terminal receiving the second gain control signal, and a current flowing through the tenth transistor. And the first
A fourth amplifier circuit having an output unit for outputting a differential current between a seventh current and an eighth current respectively corresponding to the current flowing through the first transistor; and the first and second gain control signals. , A first output terminal for supplying a combined current of the fifth current and the eighth current, and a combined current of the sixth current and the seventh current And a second output terminal for supplying: a. 6. A first and a second transistor, to which a differential input voltage is inputted to a control terminal, connected between the first transistor and the second transistor, and a first gain connected to the control terminal. A first amplifier circuit including a third transistor to which a control signal is input, and an output unit that outputs a first current corresponding to a current flowing through the first transistor and a current flowing through the second transistor And a fourth and a fifth in which the differential input voltage is inputted to a control terminal.
Transistor, the fourth transistor and the fifth transistor
A sixth transistor connected between the first and second transistors and having a control terminal to which a second gain control signal is input; and a sixth transistor corresponding to a current flowing through the fourth transistor and a current flowing through the fifth transistor. A second amplifier circuit having an output unit for outputting the first and second currents; a gain control circuit for generating the first and second gain control signals; and a combination of the first current and the second current. A variable gain amplifier circuit having an output terminal for supplying current. 7. A first and second transistor, to which a differential input voltage is inputted to a control terminal, connected between the first transistor and the second transistor, and a first gain connected to the control terminal. A first amplifier circuit including a third transistor to which a control signal is input, and an output unit that outputs a first current corresponding to a current flowing through the first transistor and a current flowing through the second transistor And a fourth and a fifth in which the differential input voltage is inputted to a control terminal.
Transistor, the fourth transistor and the fifth transistor
A sixth transistor connected between the first and second transistors and having a control terminal to which a second gain control signal is input; and a sixth transistor corresponding to a current flowing through the fourth transistor and a current flowing through the fifth transistor. A second amplifier circuit having an output unit that outputs a second current, a voltage generation circuit that generates a signal voltage corresponding to a combined current of the first current and the second current, Seventh and eighth transistors each having a reference voltage input to a control terminal, connected between the seventh transistor and the eighth transistor, and the first gain control signal input to a control terminal. And a third transistor corresponding to a current flowing through the seventh transistor and a current flowing through the eighth transistor.
A third amplifier circuit having an output unit for outputting a current of the third type, tenth and eleventh transistors each of which receives the signal voltage and the reference voltage at a control terminal, the tenth transistor and the eleventh A twelfth transistor connected between the first and second transistors and the control terminal to which the second gain control signal is input; and a twelfth transistor corresponding to a current flowing through the tenth transistor and a current flowing through the eleventh transistor. And an output unit for outputting a current of 4
And a gain control circuit for generating the first and second gain control signals; and an output terminal for supplying a combined current of the third current and the fourth current. Gain amplification circuit.