JP2002198424A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: In a semiconductor device having a wiring structure using a dual damascene process, a capacitor whose capacitance can be changed by an easy design change is formed. SOLUTION: A lower electrode 18b of a capacitor is connected to a first C electrode.
It is formed simultaneously with the first Cu wiring layer 18a using the u film 18. Opening 2 for forming upper electrode 24b of capacitor
Reference numeral 0b denotes an opening in the interlayer insulating film 19 at the same time as the via hole 20a, and the bottom is used as the dielectric film 25 of the capacitor except for the silicon nitride film 19a which is the lowermost film of the interlayer insulating film 19. The upper electrode 24b is formed simultaneously with the second Cu wiring layer 24a using the second Cu film 24 which is a dual damascene wiring. As described above, the capacitor is simultaneously formed in the wiring process using the dual damascene process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a multilayer wiring structure using a dual damascene process.

[0002]

2. Description of the Related Art In a damascene process for forming a wiring layer of a semiconductor device, fine high-density wiring can be formed without using an etching process for a metal film. In particular, the dual damascene process, in which via holes and interconnects are formed simultaneously, is the most promising process for achieving higher performance by miniaturizing and increasing reliability of multilayer interconnects and lowering costs by reducing the number of processes. is there. Also, as a wiring material, the specific resistance is small,
Copper (Cu), which has a high resistance to stress migration and electromigration, has been difficult to process for use in forming wiring by etching. However, copper (Cu) has attracted attention and is being developed as a wiring material using a damascene process.

On the other hand, a capacitor for coupling wiring and storing electric charges is formed by using the capacitance of a dielectric film between upper and lower electrode layers. In order to obtain a certain capacitance, the area of the dielectric film must be secured. It is necessary to reduce the thickness. FIG. 29 is a cross-sectional view showing the structure of a conventional semiconductor device, in which a capacitor formed in a gate step is provided. In the figure, 1 is a semiconductor substrate (hereinafter referred to as a substrate), 2 is a trench type insulating film for element isolation, 3 is an N ⁺ diffusion layer formed in a predetermined region of the substrate 1, and 4 is a gate oxide on the substrate 1. Membrane 4
a, a gate electrode film formed via a, 5 an interlayer insulating film,
Reference numeral 6 denotes a tungsten plug in which a connection hole provided in the interlayer insulating film 5 is buried, and 7 denotes a wiring layer formed on the interlayer insulating film 5 so as to connect to the tungsten plug 6. As shown in the figure, a capacitor is constituted by using the N ⁺ diffusion layer 3 and the gate electrode film 4 as a lower electrode and an upper electrode of the capacitor, respectively, and using the gate oxide film 4a as a dielectric film. Using the gate oxide film 4a, which is a thin oxide film, a capacitor is formed by a gate process capable of increasing the capacity per unit area.

[0004]

In the semiconductor device, the capacitance required for the capacitor is set for each individual product. However, in the conventional capacitor having the above structure, when the capacitance is changed for each product, Since the lower electrode is composed of the N ⁺ diffusion layer 3, a significant change is required. Therefore, generally, as shown in the plan view of FIG. 30, extra circuits 8a to 8d serving as capacitors are formed in advance, and the wiring layer 9 is changed as necessary. That is, when a large capacitance is required, the wiring 9a is formed and the capacitor circuits 8a to 8a are formed.
When a small capacity is sufficient, the wiring 9b is formed and the capacitor circuits 8a to 8c are used. Therefore, since a redundant capacitor is required, there is a problem that the chip area becomes large. If you need more capacity than expected,
Significant design changes are required. At this time, since the capacitors are formed in the gate process, the arrangement of active elements such as transistors is restricted, and the design cannot be easily changed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is intended to provide a semiconductor device using dual damascene wiring which can realize fine high-density wiring at high performance and at low cost. It is an object of the present invention to provide a structure of a capacitor whose capacitance can be changed by a simple design change. Another object of the present invention is to provide a manufacturing method suitable for this.

[0006]

Means for Solving the Problems Claim 1 according to the present invention.
According to the semiconductor device described above, a first wiring layer formed on a semiconductor substrate, an interlayer insulating film formed over the entire surface covering the first wiring layer, a via hole and a wiring groove provided in the interlayer insulating film And a second wiring layer having a dual damascene structure formed to be connected to the first wiring layer by embedding the first wiring layer at the same time.
A second electrode forming the second wiring layer in an opening that is deeper than the wiring groove provided in the interlayer insulating film on the lower electrode and does not reach the lower electrode. The capacitor has a capacitive element composed of an upper electrode formed by embedding a conductive film and a dielectric film sandwiched between the upper electrode and the lower electrode and constituting a lower layer of the interlayer insulating film.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the interlayer insulating film is a laminated film including a plurality of films having different etching selectivity, and the dielectric film of the capacitor is formed by the interlayer insulating film. This is constituted by the lowermost film of the insulating film.

According to a third aspect of the present invention, in the semiconductor device according to the second aspect, the first conductive film is a copper film, and a lowermost film of the interlayer insulating film is a silicon nitride film.

According to a fourth aspect of the present invention, there is provided a semiconductor device, comprising: a first wiring layer formed on a semiconductor substrate; an interlayer insulating film formed on the entire surface to cover the first wiring layer; A second wiring layer having a dual damascene structure connected to the first wiring layer by simultaneously burying a via hole and a wiring groove provided in an interlayer insulating film, wherein the first wiring A lower electrode made of a first conductive film forming a layer, and a second conductive film forming a second wiring layer is buried in an opening provided in the interlayer insulating film on the lower electrode. And a dielectric element formed on the inner wall of the opening and sandwiched between the upper electrode and the lower electrode at the bottom of the opening.

According to a fifth aspect of the present invention, in the semiconductor device according to the fourth aspect, the dielectric film is formed also on a side wall of the second wiring layer.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device, a step of forming an interlayer insulating film over the entire surface of the semiconductor substrate on which the first conductive film is formed; An opening is formed by anisotropic etching using the first resist mask, leaving a lower layer portion of the interlayer insulating film, a via hole and an opening for filling the second conductive film are formed, and the opening remaining in the lower layer of the opening is formed. Forming a dielectric film of a capacitive element by a lower layer portion of the interlayer insulating film,
A step of forming a wiring groove by burying an organic material in the via hole and the opening and opening the interlayer insulating film by anisotropic etching using a second resist mask; and a third step of covering the opening. By etching using a resist mask, a lower layer portion of the interlayer insulating film remaining in the lower layer of the via hole is removed to remove the via hole from the first layer.
And a second wiring layer connected to the first conductive film by burying a second conductive film in the wiring groove, the via hole, and the opening by a dual damascene process. And forming an upper electrode of the capacitive element.

According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth aspect, when the anisotropic etching of the interlayer insulating film is performed using the first resist mask,
The lower part of the interlayer insulating film serving as the dielectric film functions as an etching stopper.

According to a eighth aspect of the present invention, in the method of manufacturing a semiconductor device, a step of forming an interlayer insulating film over the entire surface of the semiconductor substrate on which the first conductive film is formed; Forming a via hole and an opening for filling the second conductive film by anisotropic etching using the first resist mask, filling an organic material in the via hole and the opening, Forming a wiring groove by opening the insulating film by anisotropic etching using a second resist mask; and forming a dielectric on the entire surface of the interlayer insulating film where the wiring groove, the via hole and the opening are opened. After forming the body film, the dielectric film is removed by etching using a third resist mask covering the opening, and the dielectric film at the bottom of the via hole is removed and the dielectric film is removed. Leaving a second conductive layer in the wiring groove, the via hole and the opening by a dual damascene process, leaving a second wiring layer connected to the first conductive film; Forming an upper electrode of the capacitive element.

According to a ninth aspect of the present invention, in the method of the eighth aspect, the etching of the dielectric film using the third resist mask is anisotropic etching, and the inner wall of the opening is formed. The dielectric film is left on the side wall of the via hole and the side wall of the wiring groove.

According to a tenth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the sixth to ninth aspects, the third resist mask covering the opening is cured only at a portion irradiated with light. It is formed of a negative type resist.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention. In the figure, reference numeral 11 denotes a semiconductor substrate (hereinafter, referred to as a substrate 11), 12 denotes an insulating film formed on the substrate 11, 13 denotes a plug electrode formed by burying a connection hole provided in a predetermined region of the insulating film 12, 14 is an insulating film composed of a silicon oxide film 14b / silicon nitride film 14a, 15a and 15b are wiring grooves provided in the insulating film 14, respectively.
a, 18b) are the barrier metal 1 in the wiring grooves 15a, 15b.
6. A first Cu film as a first conductive film embedded by a plating method via a seed layer 17 at the time of plating, in particular, 18a is a first Cu wiring layer, and 18b is a lower electrode of a capacitor. . 19 is a silicon oxide film 19b, 19c /
An interlayer insulating film made of a silicon nitride film 19a; 20a, a via hole opened in the interlayer insulating film 19 so as to reach the first Cu wiring layer 18a; 20b, a silicon nitride film 19a on a lower electrode 18b of the interlayer insulating film 19; Are formed in the silicon oxide film 19 c of the interlayer insulating film 19. 24 (24a, 2
4b) a second Cu film as a second conductive film embedded in the via hole 20a, the opening 20b, and the wiring groove 21 via the barrier metal 22 and the seed layer 23 at the time of plating by plating, particularly 24a Is the second Cu wiring layer, 2
4b is an upper electrode of the capacitor. Numeral 25 is a dielectric film of the capacitor formed of the silicon nitride film 19a sandwiched between both electrodes of the capacitor.

A method of manufacturing a semiconductor device having such a configuration will be described below with reference to FIGS. First, an insulating film 12 made of a silicon oxide film is formed on the entire surface of a substrate 11 on which elements such as a transistor, a resistive element, and a capacitive element are formed and planarized, and then a connection hole is provided in a predetermined region. Then, for example, tungsten is embedded to form the plug electrode 13. Thereafter, an insulating film 14 of silicon oxynitride 14c / silicon oxide film 14b / silicon nitride film 14a formed by controlling the composition ratio of silicon, nitrogen and oxygen is formed on the entire surface (FIG. 2). Next, a photoresist film 26 is formed on the entire surface of the flattened insulating film 14 and patterned by lithography (FIG. 3). After the silicon oxynitride 14c and the silicon oxide film 14b are sequentially etched by anisotropic etching using the resist pattern 26 as a mask (FIG. 4), the photoresist film 26 is removed by ashing using oxygen plasma, and wet processing is performed. To remove the polymer (FIG. 5). Subsequently, the underlying silicon nitride film 14a is etched by anisotropic etching, and the silicon oxynitride 14c on the surface is etched.
To form wiring grooves 15a and 15b to a desired depth, for example, about 300 nm (FIG. 6).

Next, a wiring layer made of, for example, Cu is formed by filling the wiring grooves 15a and 15b. As a forming method, a sputtering method, a CVD method, a plating method, or the like is used. Here, an example of forming by using a plating method is described. First, a barrier metal layer 16 for preventing diffusion into an insulating film (silicon oxide film) 12 and improving adhesion, and a seed layer 17 made of a Cu film serving as an electrode during plating are formed on the entire surface of the substrate 11. Are continuously formed by a sputtering method. Barrier metal layer 1
For example, tantalum (TaN) is formed to a thickness of about 30 nm by sputtering tantalum (Ta) by a reactive sputtering method of sputtering metal in a nitrogen atmosphere. The barrier metal layer 16 is made of, for example, Ti
Any conductive material having a stopping power for Cu, such as N, Ti, or Ta, may be used, and its film thickness is determined by the stopping power for thermal diffusion for Cu. The seed layer 17 is formed in the wiring groove 15.
A Cu film is formed to have a thickness of, for example, about 200 nm so as to be formed also in the portions having poor coverage in a and 15b (FIG. 7).

Next, a Cu film is grown by an electrolytic plating method for supplying a charge to the seed layer 17 in a copper sulfate solution.
After being formed to a thickness of 00 nm, the crystallinity of Cu is adjusted by, for example, low-temperature annealing not exceeding 400 ° C.
Is formed. Note that this film thickness may be determined in consideration of film removal by a chemical mechanical polishing method (CMP method) performed in a later step (FIG. 8). Next, the first Cu film 18, the seed layer 17, and the barrier metal layer 1 are formed by the CMP method.
6 is polished so as to remain only in the wiring grooves 15a and 15b, and the first Cu wiring layer 18 connected to the plug electrode 13 is formed.
a and the lower electrode 18b of the capacitor are formed (FIG. 9).

Next, a silicon nitride film 19a, which is the lowermost film of the interlayer insulating film 19, is coated on the entire surface with, for example, monosilane (S
Plasma CVD using iH ₄ ) and ammonia (NH ₃ )
The wafer temperature is reduced by about 2 Torr to 40
The film is formed at a thickness of about 50 nm by controlling the temperature to about 0 ° C.
By forming the silicon nitride film 19a on the surface of the first Cu film 18, the oxidation of the Cu film 18 can be prevented (FIG. 10). Subsequently, a silicon oxide film 19b to be a wiring interlayer insulating film and a silicon oxide film 19c for forming a wiring groove are formed thereon. Here, after a silicon oxide film 19b having excellent moisture resistance is formed by a plasma CVD method, an oxide film CMP is applied to flatten a projection formed by the surface of the lower first Cu film 18. Thereafter, the normal silicon oxide film is doped with fluorine to form a low dielectric constant silicon oxide film 19c.
Is formed. Here, the silicon oxide film 19b and the silicon oxide film 19c are different films, but may have the same composition. This is performed by a plasma CVD method using SiH ₄ , N ₂ O, and CF ₄ to form a film with a thickness of about 700 nm while controlling the wafer temperature to about 400 ° C. at a low pressure of about 2 Torr. Thereby, an interlayer insulating film 19 is formed.
1).

Next, an antireflection film 27 is formed on the entire surface of the interlayer insulating film 19. Here, a SiON film in which the composition ratio of Si, O, and N is controlled is formed by a plasma CVD method.
By changing the composition ratio, the refractive index and absorption coefficient can be controlled,
By adjusting the film thickness, an anti-reflection film 27 suitable for the wavelength of light used in lithography in a later step can be formed.
2). Next, a photoresist film 28 is formed on the entire surface of the antireflection film 27, and is patterned by lithography to form a first resist pattern 28 (FIG. 13). Using the first resist pattern 28 as a mask, the underlying antireflection film 27 and the interlayer insulating film 19 are sequentially etched by anisotropic etching. Thereby, the via hole 20 a and the upper electrode 2 of the capacitor are formed in the interlayer insulating film 19.
The opening 20b for forming the silicon nitride film 19
The opening is made in a state where a remains. At this time, the silicon nitride film 1
Since 9a functions as an etching stopper, opening can be performed with high reliability while the silicon nitride film 19a remains (FIG. 14). Next, the photoresist film 28 is removed by ashing using oxygen plasma, and the polymer is removed by wet processing (FIG. 15).

Next, an organic film 29 as an organic material is applied to the entire surface of the substrate 11. The material of the organic film 29 may be a resist itself or a resin not containing a photosensitive agent. The material of the organic film 29 has a high etching selectivity at the time of processing the wiring groove 21 in a later step, and the via hole 20a and the opening 2
0b as long as it has good embedding characteristics (see FIG. 1).
6). Subsequently, the organic film 29 is left only in the via hole 20a and the opening 20b by overall etch back (FIG. 17). Next, a photoresist film 30 is formed on the entire surface and patterned by lithography to form a second resist pattern 30 (FIG. 18). Using the second resist pattern 30 as a mask, the underlying anti-reflection film 2
7 and the interlayer insulating film 19 are sequentially etched by anisotropic etching. As a result, a wiring groove 21 having a depth of about 300 nm is formed in the silicon oxide film 19c of the interlayer insulating film 19. In this etching, the via hole 2
0a and the bottom of the opening 20b are protected from damage by etching by the organic film 29 (FIG. 19). next,
The photoresist film 30 is removed by ashing using oxygen plasma, and the polymer is removed by wet processing (FIG. 20).

Next, a negative-type photoresist film 31 is formed on the entire surface, in which only the light-irradiated portions are cured, and is patterned by lithography to form a third resist pattern 31. At this time, the third resist pattern 3
1 is formed only with a pattern covering the opening 20b for forming the upper electrode 24b of the capacitor. (FIG. 21).
Subsequently, the silicon nitride film 19a at the bottom of the via hole 20a is removed by anisotropic etching using the third resist pattern 31 as a mask, and the antireflection film 27 is further removed. Here, since the negative type photoresist film 31 was used, the silicon nitride film 19a in the via hole 20a was used.
Can be completely removed. If a positive resist is used,
Due to the attenuation of light in the via hole, the resist may remain in the via hole where the resist is not desired to be left, and the reliability of the subsequent etching deteriorates. After this,
The photoresist film 31 is removed by ashing using oxygen plasma, and the polymer is removed by wet processing. Thereby, the via hole 20a is formed in the silicon nitride film 1 at the bottom.
9a is removed to reach the surface of the first Cu film 18, and the silicon nitride film 19a to be the dielectric film 25 of the capacitor remains at the bottom of the opening 20b (FIG. 22).

Next, a dual damascene wiring for simultaneously filling the wiring groove 21, the via hole 20a and the opening 20b is formed as follows using, for example, the plating method described above. First, a barrier metal layer 22 and a seed layer 23 made of a Cu film serving as an electrode during plating are continuously formed on the entire surface of the substrate 11 by a sputtering method, and charges are applied to the seed layer 23 in a copper sulfate solution. After the Cu film is grown by the supplied electrolytic plating method, the crystallinity of Cu is adjusted by, for example, low-temperature annealing not exceeding 400 ° C. to form the second Cu film 24 (FIG. 23). Next, the second Cu
The film 24, the seed layer 23, and the barrier metal layer 22 are polished to form the wiring groove 21, the via hole 20a, and the opening 20b.
Leave only inside. As a result, the wiring groove 21 and the via hole 20a are simultaneously buried and the first Cu wiring layer 1 is formed.
8a, a second Cu wiring layer 24a connected to
0b, and the lower electrode 18 is interposed through the dielectric film 25.
and the upper electrode 24b of the capacitor formed on the substrate b (see FIG. 1). Thereafter, predetermined processing is performed to complete the semiconductor device.

In this embodiment, the lower electrode 18b of the capacitor is formed simultaneously with the first Cu wiring layer 18a using the first Cu film 18, and the upper electrode 24b of the capacitor is formed.
Was formed simultaneously with the second Cu wiring layer 24a using the second Cu film 24 which is a dual damascene wiring. Further, an opening 20b for forming the upper electrode 24b is opened at the same time as the via hole 20a, and the interlayer insulating film 19
The remaining silicon nitride film 19a, which is the lowermost film, was used as the dielectric film 25 of the capacitor. As described above, the capacitor can be formed simultaneously in the wiring process using the dual damascene process.

Further, as shown in FIG.
a, silicon nitride film 19a (25) and upper electrode 24
Since the capacitor composed of b is formed in the wiring step, the N ⁺ diffusion layer 33 formed on the substrate 11, the gate oxide film 34, the gate electrode film 35, and the like are formed via the insulating film 36 more than the layer formed thereon. Formed in the upper layer. For this reason, when changing the capacitance of a capacitor for a product, it is not restricted by the arrangement of active elements such as transistors.
It can be easily realized by changing the area of the capacitor region 40 independently. At this time, the change can be easily made only by changing the mask in the lithography step of forming the wiring without increasing the number of steps. In FIG. 24, 32 is a trench-type insulating film for element isolation, 37 and 38 are tungsten plugs embedded in connection holes provided in the insulating film 36, and 39 is formed so as to be connected to the tungsten plug 37. This wiring layer does not contribute to the configuration of the capacitor.

In this embodiment, a Cu film is used for the first conductive film 18, and the lowermost layer of the interlayer insulating film 19 used for the dielectric film 25 of the capacitor is a silicon nitride film 19a.
And For this reason, the silicon nitride film 19a can prevent the underlying Cu film 18 from being oxidized and provide a dielectric film 25 of a capacitor having a high dielectric constant (dielectric constant 9).
Although the dielectric constant is lowered, SiC, C, or the like, which can prevent oxidation of the Cu film, can be used instead of the silicon nitride film 19a.

In the above embodiment, the first Cu film 18 is formed by using the single damascene process. However, the present invention is not limited to this, and the Cu film can be formed by using the dual damascene process. After the film is formed, it may be formed by etching using a resist mask.

Embodiment 2 Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. FIG. 25 is a sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention. In the figure, 11 to 19 and 21 to 24 are the same as those in the first embodiment, 41a is a via hole provided in the interlayer insulating film 19 so as to reach the first Cu film 18, 41b
Is an opening for forming the upper electrode 24b of the capacitor, which is also provided in the interlayer insulating film 19 so as to reach the first Cu film 18, and 42 (42a, 42b) are silicon nitride as a dielectric film of the capacitor. In particular, 42a is a silicon nitride film formed on the side wall of the via hole 41a and the wiring groove 21, and 42b is formed on the inner wall of the opening 41b. This is a silicon nitride film constituting a capacitor.

A method of manufacturing a semiconductor device having such a structure will be described below with reference to FIGS. As in the first embodiment, after forming the first Cu film 18, an interlayer insulating film 19 composed of the silicon oxide films 19b and 19c / the silicon nitride film 19a is formed. Further, an anti-reflection film 27 is formed, and a first resist pattern 28 is formed in the same manner as in the first embodiment (see FIGS. 2 to 13). Next, the first
The underlying antireflection film 27 and interlayer insulating film 19 are sequentially etched by anisotropic etching using the resist pattern 28 as a mask. Thereby, the interlayer insulating film 19 is formed.
Then, a via hole 41a and an opening 41b reaching the first Cu film 18 are opened (FIG. 26). Next, after removing the photoresist film 28, as in the first embodiment,
The organic film 29 is buried only in the via hole 41a and the opening 41b, and the wiring groove 21 is formed by anisotropic etching using the second resist pattern 30 as a mask (see FIGS. 16 to 20).

Next, a silicon nitride film 42 to be a dielectric film of the capacitor is formed on the entire surface of the substrate 11. The thickness of the silicon nitride film 42 is appropriately determined independently of the wiring formation so that the capacitance of the capacitor becomes a desired value (FIG. 2).
7). Thereafter, as in the first embodiment, a negative type photoresist film 31 is formed in which only the light-irradiated portions are cured on the entire surface, and is patterned by lithography to form a third resist pattern 31. At this time, the third resist pattern 31 is formed on the upper electrode 2 of the capacitor.
4b is formed only with a pattern covering the opening 20b (see FIG. 21). Subsequently, after the silicon nitride film 42 is removed by anisotropic etching using the third resist pattern 31 as a mask, the antireflection film 27 is further removed. Thereafter, the photoresist film 31 is removed by ashing using oxygen plasma, and the polymer is removed by wet processing. Thereby, the silicon nitride film 42 (42
a, 42b) are the inner wall of the opening 41b and the via hole 42.
a and remains only on the side wall of the wiring groove 21 (FIG. 28). Thereafter, as in the first embodiment, the barrier metal layer 22 and the seed layer 23 are formed by a dual damascene process.
A second Cu film 24 is formed through the substrate, and a second Cu wiring layer 24a and an upper electrode 24 of a capacitor are formed.
5).

In this embodiment, the lower electrode 18b of the capacitor is formed simultaneously with the first Cu wiring layer 18a using the first Cu film 18, and the upper electrode 24b of the capacitor is formed.
Was formed simultaneously with the second Cu wiring layer 24a using the second Cu film 24 which is a dual damascene wiring. Further, an opening 41b for forming the upper electrode 24b is opened at the same time as the via hole 41a. After a silicon nitride film 42 serving as a dielectric film of the capacitor is formed on the entire surface, the silicon nitride film 42 at the bottom of the via hole 41a is removed. Opening 41
b Leave on the inner wall. This silicon nitride film 42b is formed at the bottom of the opening 41b at both electrodes 18b and 24b of the capacitor.
To form a capacitor. As described above, the capacitor can be formed simultaneously in the wiring process using the dual damascene process. Further, similarly to the first embodiment,
The capacitance of the capacitor can be easily changed by a design change without being restricted by the arrangement of active elements such as transistors.

In this embodiment, since the interlayer insulating film 19 is formed independently of the dielectric film 42 of the capacitor without using the same, the material, the film pressure and the like can be determined independently. Further, the lowermost film 19a of the interlayer insulating film 19 may be any insulating film that prevents oxidation of the Cu film regardless of the dielectric constant. The silicon nitride film 42 serving as a dielectric film of the capacitor is also formed on the via holes 42a and the side walls of the wiring grooves 21. That is, the silicon nitride film 42 is formed so as to cover the side wall of the second Cu film 24 which is a dual damascene wiring, protects the side wall of the second Cu film 24, and removes gas from the interlayer insulating film 19. It also has the effect of suppressing.

In the first and second embodiments, Cu is used for the wiring layer. However, other metal films such as aluminum can be used. In this case, a film for preventing oxidation is not formed on the surface. Is also good.

[0035]

As described above, in the semiconductor device according to the first aspect of the present invention, a first wiring layer formed on a semiconductor substrate and an interlayer formed over the entire surface covering the first wiring layer are provided. A semiconductor device comprising: an insulating film; and a second wiring layer having a dual damascene structure formed by simultaneously filling a via hole and a wiring groove provided in the interlayer insulating film and connected to the first wiring layer. A lower electrode made of a first conductive film constituting the first wiring layer, and an opening not reaching the lower electrode deeper than the wiring groove provided in the interlayer insulating film on the lower electrode; The second forming the second wiring layer
Having a dual damascene structure because it has a capacitive element composed of an upper electrode formed by embedding a conductive film of the above, and a dielectric film sandwiched between the upper electrode and the lower electrode and constituting a lower layer portion of the interlayer insulating film. It is possible to provide a structure of a semiconductor device including a capacitor element which can be formed at the same time as wiring formation and whose capacitance can be changed by an easy design change.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the interlayer insulating film is a laminated film including a plurality of films having different etching selectivity, and the dielectric film of the capacitor is formed by the interlayer insulating film. Since the lowermost layer of the insulating film is formed, the lowermost layer can be left on the lower electrode of the capacitor with good controllability, and the reliability of the capacitor is improved.

According to a third aspect of the present invention, in the semiconductor device according to the second aspect, the first conductive film is a copper film and the lowermost layer of the interlayer insulating film is a silicon nitride film. Of the conductive film can be prevented, and a dielectric film having a high dielectric constant can be formed.

According to a fourth aspect of the present invention, there is provided a semiconductor device, comprising: a first wiring layer formed on a semiconductor substrate; an interlayer insulating film formed on the entire surface to cover the first wiring layer; A second wiring layer having a dual damascene structure connected to the first wiring layer by simultaneously burying a via hole and a wiring groove provided in an interlayer insulating film, wherein the first wiring A lower electrode made of a first conductive film forming a layer, and a second conductive film forming a second wiring layer is buried in an opening provided in the interlayer insulating film on the lower electrode. The upper electrode and a dielectric element formed on the inner wall of the opening and formed at the bottom of the opening with a dielectric film sandwiched between the upper electrode and the lower electrode. Can be formed simultaneously Structure of a semiconductor device having a capacitor element can be changed in capacity by facilitating design changes can be provided.

According to a fifth aspect of the present invention, in the semiconductor device according to the fourth aspect, since the dielectric film is also formed on the side wall of the second wiring layer, the side wall of the second wiring layer is protected and the interlayer is formed. Degassing from the insulating film can be suppressed.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device, a step of forming an interlayer insulating film over the entire surface of the semiconductor substrate on which the first conductive film is formed; An opening is formed by anisotropic etching using the first resist mask, leaving a lower layer portion of the interlayer insulating film, a via hole and an opening for filling the second conductive film are formed, and the opening remaining in the lower layer of the opening is formed. Forming a dielectric film of a capacitive element by a lower layer portion of the interlayer insulating film,
A step of forming a wiring groove by burying an organic material in the via hole and the opening and opening the interlayer insulating film by anisotropic etching using a second resist mask; and a third step of covering the opening. By etching using a resist mask, a lower layer portion of the interlayer insulating film remaining in the lower layer of the via hole is removed to remove the via hole from the first layer.
And a second wiring layer connected to the first conductive film by burying a second conductive film in the wiring groove, the via hole, and the opening by a dual damascene process. And a step of forming an upper electrode of the capacitive element, the capacitive element can be easily formed at the same time when forming the wiring of the dual damascene structure, and the semiconductor having the capacitive element whose capacitance can be changed by a simple design change. A device is obtained.

According to a seventh aspect of the present invention, in the method for manufacturing a semiconductor device according to the sixth aspect, when the anisotropic etching of the interlayer insulating film is performed using the first resist mask,
Since the lower layer portion of the interlayer insulating film serving as the dielectric film functions as an etching stopper, the dielectric film can remain with good controllability, and a highly reliable capacitive element can be formed.

According to a eighth aspect of the present invention, in the method of manufacturing a semiconductor device, there is provided a step of forming an interlayer insulating film on the entire surface of the semiconductor substrate on which the first conductive film is formed; Forming a via hole and an opening for filling the second conductive film by anisotropic etching using the first resist mask, filling an organic material in the via hole and the opening, Forming a wiring groove by opening the insulating film by anisotropic etching using a second resist mask; and forming a dielectric on the entire surface of the interlayer insulating film where the wiring groove, the via hole and the opening are opened. After forming the body film, the dielectric film is removed by etching using a third resist mask covering the opening, and the dielectric film at the bottom of the via hole is removed and the dielectric film is removed. Leaving a second conductive layer in the wiring groove, the via hole and the opening by a dual damascene process, leaving a second wiring layer connected to the first conductive film; Forming the upper electrode of the capacitive element, the capacitive element can be formed simultaneously when forming the wiring of the dual damascene structure,
A semiconductor device having a capacitor whose capacitance can be changed by an easy design change can be obtained.

According to a ninth aspect of the present invention, in the manufacturing method of the eighth aspect, the etching of the dielectric film using the third resist mask is anisotropic etching, and the inner wall of the opening is formed. Since the dielectric film is left on the side wall of the via hole and the side wall of the wiring groove, the side wall of the second wiring layer can be protected by the dielectric film, and outgassing from the interlayer insulating film can be suppressed.

According to a tenth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the sixth to ninth aspects, the third resist mask covering the opening is cured only at a portion irradiated with light. Because it was formed with a negative resist, the unnecessary film at the bottom of the via hole can be completely removed,
A stable connection in the via hole is made possible, and the reliability of the semiconductor device is improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a sectional view showing one step of a method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a sectional view showing one step of a method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a sectional view showing one step of a method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a step of a method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 13 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 14 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 15 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 16 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 17 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 18 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 19 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 20 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 21 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 22 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 23 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 24 is a cross-sectional view illustrating an effect of the semiconductor device according to the first embodiment of the present invention;

FIG. 25 is a sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention;

FIG. 26 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 27 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 28 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 29 is a cross-sectional view illustrating a structure of a conventional semiconductor device.

FIG. 30 is a plan view showing the structure of a conventional capacitor.

[Explanation of symbols]

Reference Signs List 11 semiconductor substrate, 18 first Cu film as first conductive film, 18a first Cu wiring layer as first wiring layer, 18b lower electrode, 19 interlayer insulating film, 19a silicon nitride film, 20a via hole, 20b opening,
21 wiring groove, 24 second Cu as second conductive film
Film, 24a a second Cu wiring layer as a second wiring layer,
24b upper electrode, 25 dielectric film, 28 first resist pattern, 29 organic film as organic material, 30
Second resist pattern, 31 Third resist pattern, 41a Via hole, 41b opening, 42, 42
a, 42b Silicon nitride film as dielectric film.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 21/822 H01L 27/04 DV VF term (Reference) 4M104 AA01 BB04 BB14 BB17 BB18 BB30 BB32 CC01 DD04 DD15 DD16 DD17 DD18 DD20 DD22 DD37 DD43 DD52 DD75 DD78 FF13 FF17 FF18 FF22 GG13 GG19 HH01 HH02 HH05 HH11 HH14 HH16 5F033 HH08 HH11 HH18 HH21 HH32 HH33 JJ01 JJ08 JJ11 JJ18 KK13 KK18 KK18 PP15 PP27 PP33 QQ04 QQ08 QQ09 QQ16 QQ25 QQ31 QQ37 QQ48 QQ73 QQ92 QQ96 RR04 RR06 RR08 RR11 RR21 SS15 TT04 TT07 VV10 XX00 XX03 XX05 XX06 XX08 XX20 XX24 XX33 XX34 AC18 EZ34 XX34

Claims (10)

[Claims] 1. A semiconductor device comprising: a first wiring layer formed on a semiconductor substrate; an interlayer insulating film formed on the entire surface covering the first wiring layer; and via holes and wiring grooves provided in the interlayer insulating film. In a semiconductor device including a second wiring layer having a dual damascene structure, which is simultaneously buried and connected to the first wiring layer, a lower electrode made of a first conductive film constituting the first wiring layer; An upper portion formed by embedding a second conductive film forming the second wiring layer in an opening that does not reach the lower electrode and is deeper than the wiring groove provided in the interlayer insulating film on the lower electrode. A semiconductor device, comprising: a capacitive element including an electrode and a dielectric film sandwiched between the upper electrode and the lower electrode and constituting a lower layer of the interlayer insulating film. 2. The method according to claim 1, wherein the interlayer insulating film is a laminated film composed of a plurality of films having different etching selectivity, and a dielectric film of the capacitor is constituted by a lowermost film of the interlayer insulating film. 13. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 2, wherein the first conductive film is a copper film, and the lowermost film of the interlayer insulating film is a silicon nitride film. 4. A semiconductor device comprising: a first wiring layer formed on a semiconductor substrate; an interlayer insulating film formed on the entire surface covering the first wiring layer; and via holes and wiring grooves provided in the interlayer insulating film. In a semiconductor device including a second wiring layer having a dual damascene structure, which is simultaneously buried and connected to the first wiring layer, a lower electrode made of a first conductive film constituting the first wiring layer; An upper electrode formed by embedding a second conductive film constituting the second wiring layer in an opening provided in the interlayer insulating film on the lower electrode, and an upper electrode formed on an inner wall of the opening. A semiconductor device comprising: a capacitive element formed by a dielectric film sandwiched between the upper electrode and the lower electrode at the bottom of the opening. 5. The semiconductor device according to claim 4, wherein the dielectric film is formed also on the side wall of the second wiring layer. 6. A step of forming an interlayer insulating film over the entire surface of a semiconductor substrate on which a first conductive film is formed, and said interlayer insulating film is anisotropically etched using a first resist mask. An opening is formed leaving a lower layer portion of the film, a via hole for filling the second conductive film and an opening are formed, and a lower layer portion of the interlayer insulating film remaining under the opening forms a dielectric film of a capacitor. Forming a wiring groove by burying an organic material in the via hole and the opening, and opening the interlayer insulating film by anisotropic etching using a second resist mask; The lower portion of the interlayer insulating film remaining under the via hole is removed by etching using a third resist mask covering the portion, and the via hole is removed from the first via hole.
And a second wiring layer connected to the first conductive film by burying a second conductive film in the wiring groove, the via hole, and the opening by a dual damascene process. And forming an upper electrode of the capacitive element.
3. The method for manufacturing a semiconductor device according to any one of 3. 7. The method according to claim 6, wherein when the interlayer insulating film is anisotropically etched using the first resist mask, a lower layer of the interlayer insulating film serving as a dielectric film functions as an etching stopper. The manufacturing method of the semiconductor device described in the above. 8. A step of forming an interlayer insulating film over the entire surface of the semiconductor substrate on which the first conductive film is formed, and opening the interlayer insulating film by anisotropic etching using a first resist mask; Forming a via hole and an opening for filling the second conductive film, filling an organic material in the via hole and the opening, and anisotropically etching the interlayer insulating film using a second resist mask Forming a wiring groove by forming a dielectric film over the entire surface of the interlayer insulating film where the wiring groove, the via hole and the opening are opened, and then forming the dielectric film in the opening Removing the dielectric film at the bottom of the via hole and leaving the dielectric film on the inner wall of the opening by etching using a third resist mask covering the wiring groove and the via hole. Forming a second conductive layer in the opening and the opening by a dual damascene process to form a second wiring layer connected to the first conductive film and an upper electrode of the capacitor. The method for manufacturing a semiconductor device according to claim 4, wherein: 9. The etching of the dielectric film using the third resist mask is anisotropic etching, and the dielectric film remains on the inner wall of the opening, the side wall of the via hole, and the side wall of the wiring groove. The method for manufacturing a semiconductor device according to claim 8. 10. The semiconductor device according to claim 6, wherein the third resist mask covering the opening is formed of a negative resist that cures only a portion irradiated with light. Production method.