JP2002190574A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) Abstract: Provided is a semiconductor integrated circuit device including a clock generation circuit that operates stably even when elements are miniaturized. SOLUTION: The phase of an input clock signal inputted from an external terminal is compared with the phase of a clock signal formed inside, and the internal clock signal is corresponded to a voltage held in a capacitor charged / discharged by the comparison output. In the case where a wiring capacitance or a dynamic memory cell is mounted as the above-mentioned capacitor in the clock generating circuit forming the above, the configuration is made using the capacitor of the dynamic memory cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technology effective when used in a device having a clock generating circuit for generating an internal clock signal corresponding to a clock signal supplied from an external terminal. It is.

[0002]

2. Description of the Related Art An example of an integrated circuit using a PLL (Phase Locked Loop) circuit as a clock generating circuit for generating an internal clock signal corresponding to a clock signal supplied from an external terminal is disclosed in Japanese Patent Laid-Open No. 2000-35463.
No. publication.

[0003]

In the above-described PLL circuit, the gate of the MOSFET is connected to a low-pass filter that forms a control voltage corresponding to a phase (frequency) difference between a clock signal supplied from an external terminal and an internal clock signal. A capacitor using capacitance is used. With the advance of semiconductor technology, miniaturization of devices has been promoted, and with such miniaturization of devices, the gate oxide film of MOSFET has also been reduced in thickness.

In the present inventors, when a gate oxide film is thinned by miniaturization of a device, a tunnel current that penetrates through the gate oxide film and flows to a substrate is generated, and the phase (frequency) of the internal clock signal is reduced. It has been noticed that the control voltage to be controlled fluctuates to stabilize the operation of the PLL circuit, that is, to cause non-negligible jitter (fluctuations in phase and frequency) in the internal clock signal. For example, a tunnel current in a gate oxide film in a MOSFET having a gate width up to the 0.2 μm generation is almost negligible, whereas a tunnel leakage current is generated in a 0.14 generation or later, which has been miniaturized. Becomes remarkable, and the PL
When used as a capacitor of an L low-pass filter, it reaches a level that cannot be ignored.

An object of the present invention is to provide a semiconductor integrated circuit device provided with a clock generation circuit that operates stably even when elements are miniaturized. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. Compare the phase between the input clock signal input from the external terminal and the internally formed clock signal,
In a clock generation circuit that forms the internal clock signal corresponding to the voltage held in the capacitor charged / discharged by the comparison output, a wiring capacity or a dynamic memory cell is mounted as the capacitor in the clock generation circuit. It is configured using the capacitor of the memory cell.

[0007]

FIG. 1 is a block diagram showing one embodiment of a PLL circuit provided in a semiconductor integrated circuit device according to the present invention. Each circuit block of this embodiment includes one circuit together with other circuits constituting the semiconductor integrated circuit device.
Formed on one semiconductor substrate. P of this embodiment
The LL circuit includes the following circuit blocks.

The external terminal is supplied with a reference clock f _IN . This reference clock f _IN is supplied to one input of a phase comparator through a delay circuit formed by an input circuit. The feedback clock f _FB from the clock distribution system forming the internal clock signal is supplied to the other input of the phase comparator through the variable M frequency dividing circuit. Although not particularly limited, the frequency division ratio (M) of the variable M frequency divider is set by a multiplication ratio M supplied from an external terminal. The division ratio M is 1,
2, 3, 4, etc. By setting the frequency division ratio M in the PLL circuit, a plurality of frequencies of the internal clock signal can be set.

The charge pump circuit operates according to the phase comparison result formed by the phase comparator, and forms a charge-up current or a discharge current according to the phase difference. The charge-up current or discharge current is transferred to the capacitor C _F, the control voltage V _F is generated. The control voltage V _F is transmitted to the current control oscillator through the voltage-current converter, to control its oscillation frequency. Although not particularly limited, an output signal of the phase comparator is transmitted to the current controlled oscillator through a pulse width current converter. With this pulse width current converter, when the phase difference increases sharply, the pulse width current converter detects and controls the frequency (phase) of the current control oscillator, thereby improving the high frequency response of the PLL loop. Can be

The output signal of the current controlled oscillator is output through a divide-by-2 circuit. This frequency dividing circuit also serves as a level amplifying circuit, and forms a pulse signal with a duty of 50%. The output signal of the frequency divider is transmitted to an internal circuit (not shown) via a clock distribution system. Such a P
The LL circuit compares the phase of the reference clock f _IN with the frequency of the feedback clock f _FB divided by M (frequency comparison), and forms a low-pass filter with a phase output corresponding to the phase difference (frequency difference). Since the current controlled oscillator is controlled via the circuit, the capacitor C _F and the voltage / current converter (pulse width current converter), the oscillation of the current controlled oscillator is controlled so that the phases (frequency) of both clocks f _IN and f _FB match. The operation is performed.

FIG. 2 is a block diagram showing an embodiment of a capacitor used in the PLL circuit of FIG. In this embodiment, the wiring capacitance is used so as not to cause a leakage current in the capacitor accompanying the miniaturization of the element. Although not particularly limited, a multilayer wiring technique is used for the wiring capacitance. That is, as shown in FIG. 1B, a first gate layer FG constituting a gate electrode of a MOSFET, metal layers M0 to M5 formed thereon, and a through hole connecting these metal wiring layers to each other. The contacts formed in S0 to S5 form electrodes that are directed in the direction perpendicular to the main surface of the semiconductor substrate. In this way, the electrodes are arranged alternately in the vertical direction to form a capacitor.

FIG. 2A shows each of the wiring layers FG and M0.
Of ~M5 and S0-S5, as the wiring layer M4 are typically illustrated, a wiring layer control voltage V _F of the capacitor C _F is applied, the "eyes" state kanji It is formed. In other words, a plurality of electrodes provided in parallel so as to extend in the horizontal direction in the figure are connected to each other on both left and right sides. On the other hand, a plurality of wiring layers of the capacitor C _F to which the ground potential VSSA of the circuit is applied are provided in parallel adjacent to the respective electrodes to which the control voltage V _F is applied. The electrodes to which the ground potential VSSA is applied are connected to each other by a PWELL formed on the uppermost wiring layer M5 and the semiconductor substrate as shown in FIG. 2B. Therefore, electrodes in which the control voltage V _F is given, the S5 and M5 and SGI and PWEL not connected.

[0013] In the structure of the capacitor C _F of this embodiment,
Since the surfaces of the electrodes are arranged in the height direction of the semiconductor integrated circuit device, a desired capacitance value can be efficiently obtained with a relatively small occupied area. The insulating film (dielectric film) provided between the electrodes can be formed irrespective of the thickness of the gate electrode FG of the MOSFET.
Even if the thickness of the gate electrode FG is reduced with the miniaturization of the OSFET, the generation of the leak current can be maintained at a negligible level without being affected by the thickness.

[0014] Then, thus when using the a wiring capacitance, it is possible to obtain a stable control voltage V _F to a constant capacitance value without depending on the voltage V _F. That, MOS capacitor gate electrode - to have also acts as a variable capacitance element the capacitance value by a voltage applied between the substrates is changed, the capacitance value is slightly changed by the change of the voltage V _F, it holds voltage Motaraseru a change in V _F is, in the case of using a wiring capacitance as in this embodiment, such a problem does not occur.

[0015] FIG. 8 have been shown characteristic diagram for explaining the relationship between the leakage current and the jitter in the capacitor C _F. FIG. 8A shows a circuit simulation result when the gate capacitance of the MOSFET having the gate width of 0.14 um is used for the capacitor _CF , and the phase fluctuation when a tunnel leak current occurs is shown. As a result of the numerical analysis, the jitter becomes 60 ps. On the other hand, as shown in FIG. 8B, the phase fluctuation in the PLL circuit when there is no tunnel leak current can be reduced to a jitter of 5 ps or less in the result of the numerical analysis under the same conditions.

For example, in a semiconductor integrated circuit device which performs input / output of data in synchronization with a clock signal at a frequency of 500 MHz or more, a clock signal input from an external terminal for a clock cycle is stored in the integrated circuit. The ratio of the signal delay in the input circuit to be taken cannot be ignored, and by using a PLL circuit or a DLL circuit as described later, an internal clock signal in which the signal delay in the input circuit is compensated can be formed. However,
If the jitter is large, a time margin is set correspondingly, and the meaning of providing a PLL circuit or a DLL circuit is diminished. Therefore, the capacitor C _F according to the present invention is
When a PLL circuit or a DLL circuit is configured using
The frequency of the clock signal can be increased, and the semiconductor integrated circuit device can operate at high speed.

FIG. 3 is a block diagram showing one embodiment of the semiconductor integrated circuit device according to the present invention. Each circuit block in the figure is drawn according to a geometrical arrangement on an actual semiconductor substrate. Each circuit block in the figure is formed on a semiconductor substrate such as single crystal silicon by a known CMOS integrated circuit manufacturing technique.

In FIG. 1, reference numeral 9 denotes a semiconductor chip;
Reference numeral 10 denotes an internal circuit, reference numeral 11 denotes a clock signal generation circuit, which includes an on-chip RAM including 12 and 13 and a logic circuit unit other than the on-chip RAM. The clock signal generation circuit 11 includes a PLL (DLL) circuit, and forms an internal clock signal corresponding to a clock signal ECLK supplied from an external terminal.

Although not particularly limited, the above-mentioned on-chip RA
M12 and M13 are configured by RAM macros. The area other than the RAM block in the area where the internal circuit 10 is formed is a spread gate area, and the respective functions are realized by the connection design. The MOSFETs are spread all over like the enlarged pattern 16 in this area. Wiring layer constituting the above wiring is composed of a multilayer wiring layer, such as the M0-M5, by utilizing such a multi-layer wiring, a capacitor C _F provided in the clock generation circuit is formed. A bonding pad 15 is provided around the semiconductor chip 9, and the input / output circuit unit 1 is provided between the bonding pad 15 and the internal circuit 10.
4 are provided. In the logic circuit portion, a circuit for performing signal processing for realizing a function corresponding to each application is formed.

FIG. 4 shows a DDR to which the present invention is applied.
SDRAM (Double Data Rate Synchronous Dynamic R
An overall block diagram of one embodiment of the andom Access Memory is shown. Although the DDR SDRAM of this embodiment is not particularly limited, four memory arrays 200A to 200D are provided corresponding to four memory banks. The memory arrays 200A to 200D respectively corresponding to the four memory banks 0 to 3 include dynamic memory cells arranged in a matrix, and according to the drawing, the selection terminals of the memory cells arranged in the same column are words for each column. The data input / output terminals of the memory cells arranged on the same row are connected to complementary data lines (not shown) for each row.

One of the word lines (not shown) of the memory array 200A is driven to a selected level in accordance with the result of decoding a row address signal by a row decoder (Row DEC) 201A. Complementary data lines (not shown) of the memory array 200A are coupled to I / O lines of a sense amplifier (Sense AMP) 202A and a column selection circuit (Column DEC) 203A. The sense amplifier 202A is an amplifier circuit that detects and amplifies a minute potential difference appearing on each complementary data line by reading data from a memory cell. The column selection circuit 203A includes a switch circuit for selecting each of the complementary data lines individually and conducting to the complementary I / O line. The column switch circuit is a column decoder 203A
Is selected in accordance with the result of decoding of the column address signal.

Similarly, memory arrays 200B to 200D also have row decoders 201B to 201D and sense amplifier 203.
B to D and column selection circuits 203B to 203D are provided.
The complementary I / O line is shared by each memory bank, and has a data input circuit (Din Buffer) having a write buffer.
The output terminal 210 is connected to an input terminal of a data output circuit (Dout Buffer) 211 including a main amplifier. Although not particularly limited, the terminal DQ is a data input / output terminal for inputting or outputting data D0 to D15 consisting of 16 bits. The DQS buffer (DQS Buffer) 215 forms a data strobe signal of data output from the terminal DQ.

The address signals A0 to A14 supplied from the address input terminals are used as address buffers (Address Buffer).
er) 204, of which the row address signal is held in a row address buffer 205, and the column address signal is held in a column address buffer (Column).
(Address Buffer) 206. A refresh counter 208 generates a row address at the time of Automatic Refresh and Self Refresh.

The output of the column address buffer 206 is a column address counter (Column Address Counter) 20.
The column address counter 207 supplies the column address signal as the preset data or a value obtained by sequentially incrementing the column address signal as the preset data in a burst mode specified by a command or the like described later. 203A
To 203D.

Mode Register 213
Holds various operation mode information. The above row decoder
As for (Row Decoder) 201A to 201D, only those corresponding to the bank specified by the bank select (Bank Select) circuit 212 operate, and the word line is selected.
The control circuit (Control Logic) 209 includes, but is not limited to, clock signals CLK and / CLK (symbol / means that a signal attached thereto is a row enable signal), a clock enable signal CKE, and a chip select signal. / CS, column address strobe signal /
External control signals such as CAS, row address strobe signal / RAS, and write enable signal / WE;
M and DQS and an address signal via the mode register 213 are supplied, and an internal mode for controlling the operation mode of the DDR SDRAM, the test mode, and the operation of the above-described circuit block based on a change or timing of the level of those signals. It forms timing signals, each having an input buffer equal to the signal.

Clock signals CLK and / CLK are input to DLL circuit 214 via a clock buffer, and an internal clock is generated. Although the internal clock is not particularly limited, the data output circuit 211 and the DQS buffer 2
Used as 15 input signals. The clock signal passed through the clock buffer is supplied to the data input circuit 210.
Or to a clock terminal supplied to the column address counter 207.

Other external input signals are made significant in synchronization with the rising edge of the internal clock signal. The chip select signal / CS instructs the start of a command input cycle by its low level. Chip select signal / C
When S is at the high level (the chip is not selected) and other inputs have no meaning. However, internal operations such as a memory bank selection state and a burst operation, which will be described later, are not affected by the change to the chip non-selection state. / RAS, / CA
The S and / WE signals have different functions from the corresponding signals in a normal DRAM, and are significant signals when defining a command cycle described later.

The clock enable signal CKE is a signal for instructing the validity of the next clock signal.
If E is at the high level, the next rising edge of the clock signal CLK is valid, and if it is at the low level, it is invalid. In the read mode, when an external control signal / OE for controlling output enable for the data output circuit 211 is provided, the signal / O
E is also supplied to the control circuit 209, and when the signal is at a high level, for example, the data output circuit 211 is brought into a high output impedance state.

The row address signal is a clock signal C
It is defined by the levels of A0 to A11 in a later-described row address strobe / bank active command cycle synchronized with the rising edge of LK (internal clock signal).

The address signals A12 and A13 are regarded as bank selection signals in the row address strobe / bank active command cycle. That is, A12
And A13, four memory banks 0 to
One of the three is selected. The selection control of the memory bank is not particularly limited, but only the row decoder of the selected memory bank is activated, all the column switch circuits of the unselected memory bank are not selected, the data input circuit 210 and the data of only the selected memory bank are selected. This can be performed by processing such as connection to an output circuit.

In the case where the column address signal has a configuration of 256 Mbits and 16 bits as described above, a read or write command (column address / read command described later) synchronized with the rising edge of the clock signal CLK (internal clock) is used. , Column address / write command) cycle. The column address defined in this way is used as a start address for burst access.

In the DDR SDRAM, when a burst operation is performed in one memory bank, another memory bank is designated in the middle of the burst operation and a row address strobe / bank active command is supplied, and the execution is performed. The operation of the row address system in the other memory bank is enabled without affecting the operation in the other memory bank.

The read operation of the DDR SDRAM is as follows. Chip select / CS, / RAS, / C
AS and write enable / WE signals are input in synchronization with the CLK signal. A row address and a bank selection signal are input at the same time as / RAS = 0, and are held by the row address buffer 205 and the bank select circuit 212, respectively.
The row decoder 210 of the bank specified by the bank select circuit 212 decodes the row address signal, and data of the entire row is output from the memory cell array 200 as a minute signal. The output small signal is applied to the sense amplifier 202.
Amplified and retained by The designated bank becomes active.

After 3 CLK from the row address input, CAS =
At the same time as 0, a column address and a bank selection signal are input, and these are held by the column address buffer 206 and the bank selection circuit 212, respectively. If the designated bank is active, the held column address is output from the column address counter 207, and the column decoder 203 selects a column. The selected data is stored in the sense amplifier 202
Output from The data output at this time is for two sets (8 bits in the × 4 bit configuration, 32 bits in the × 16 bit configuration).

The data output from the sense amplifier 202 is output from the data output circuit 211 to the outside of the chip. The output timing is synchronized with both the rising and falling edges of QCLK output from DLL 214. At this time,
As described above, the data of two sets is converted from parallel to serial, and becomes data of one set × 2. At the same time as the data output, the data strobe signal D
QS is output. When the burst length stored in the mode register 213 is 4 or more, the column address counter 207 automatically increments the address, and
The next column data is read.

The role of the DLL 214 is as follows: the data output circuit 211 and the operation clock QC of the DQS buffer 215.
Generate LK. The data output circuit 211 and the DQS buffer 215 take time from the input of the internal clock signal QCLK generated by the DLL 214 to the actual output of the data signal or the data strobe signal. Therefore, the phase of the data signal or the data strobe signal is made to coincide with the external clock CLK by using the replica circuit to advance the phase of the internal clock signal QCLK with respect to the external clock CLK. Therefore, in this case, the data signal and the data strobe signal are brought into phase with the external clock signal.

FIG. 5 is an overall block diagram of one embodiment of the DLL circuit of FIG. FIG. 2 shows an overall view of the DLL centering on the DLL digital unit 4.
The DLL digital unit 4 controls the DLL analog unit 3 so that the external clock signal ECLK_T and the internal clock signal ICLK input via the clock input circuit 2091 have the same phase.

In the DLL of this embodiment, the external clock signal ECLK_T and the internal clock signal ICLK are each frequency-divided by 4 in the frequency dividing circuit 401 in order to prevent harmonic lock. As described above, the external clock signal ECLK
_T divided by 4 and ECLK4 and internal clock signal ICL
The phase of ICLK4 obtained by dividing K by 4 is compared by the phase comparator 402. The state control circuit 403 checks the waveform of EARLY_INT, which is the result of the phase comparison, and
An RBO signal and a TURBO1 signal are output. The pulse generation circuit 404 outputs an up (UP) signal and a down (DOW) signal.
N) output a signal to control the operation of the charge pump provided in the DLL analog unit 3;

In this embodiment, a charge pump test pulse generation circuit 405 is provided, and the CP_PULSE signal output from this circuit is provided in the DLL analog section 3 instead of the up signal UP and the down signal DOWN. The operation is controlled by controlling the operation of the charge pump. The DLL analog section 3 is an analog variable delay circuit that controls the operating current of a MOS differential amplifier circuit that receives complementary signals (T and B), and changes the delay time in an analog manner in response to a change in the operating current. Variable delay circuit.

A clock signal ECLK passed through the clock input circuit 2091 is supplied to the frequency dividing circuit 401. T and
An internal clock signal ICLK through a replica (Replica Delay) 406 is supplied. As a result, ECLK4 and ICLK4, each of which has been frequency-divided by 4, are compared in phase by the phase comparator 402. The replica circuit 406 is a delay circuit composed of the same circuit as the clock input circuit 2091 and the data output circuit 211 or the DQS buffer (output circuit) 215. Since the internal clock signal QCLK having a phase advanced by the circuit 2091 and the data output circuit 211 (or the DQS buffer 215) is generated, the external clock signal CLK is generated. T and, for example, the data output circuit 21
1 and the clock signal output through the DQS buffer 215 are in phase.

FIG. 6 is a circuit diagram showing one embodiment of the variable delay circuit included in the DLL analog section 3.
The variable delay circuit 303 includes a variable delay element and a bias circuit. The variable delay element has a configuration in which two differential inverters are connected in series, and varies the delay amount by controlling the current of the current source by NBIAS. The circuit of the above-mentioned two differential inverters is shown, and the circuit of the preceding stage with a circuit symbol will be described as an example.
N-channel MOSFETs Q7 and Q as variable current sources whose current is changed by the NBIAS between the common source of SFETs Q1 and Q2 and the ground potential of the circuit.
8 are provided in a side-by-side configuration.

Between the drains of the differential MOSFETs Q1 and Q2 and the power supply voltage VDD, diode-connected P-channel MOSFETs Q3 and Q4 as load circuits are provided, respectively. Further, in order to make the change of the differential output signal sharp, latch-type P-channel MOSFETs Q5 and Q6 in which the gate and the drain are connected to each other are provided in parallel with the diode-connected MOSFETs Q3 and Q4. . The differential MOSFETs Q1 and Q
2 outputs the differential signal M as the input signal of the next stage circuit.
It is supplied to the gate of the OSFET. By connecting the two differential inverters as described above in a multi-stage cascade, a variable delay circuit 303 is formed.
Output taps TAPN0, TAPP0 to TAPN
N, TAPPN are provided.

The bias circuit applies the control voltage VB to the MOSF
The current signal is converted into a current signal by ETQ9, and the current signal is converted to a current source MOSFE of each differential inverter by using a simple current mirror.
Although connected to T, a buffer circuit or the like for correcting the control voltage-delay amount characteristic may be used. The output of the variable delay circuit is provided with a plurality of (for example, six sets) output taps as described above, and by selecting one of these outputs, the number of stages of the variable delay circuit can be changed. I can do it.

In the variable delay circuit as described above, the number of stages is set in accordance with the oscillation frequency, and the delay signal is fed back to the input side, whereby a current control oscillation circuit can be formed. That is, the DLL can be replaced with a PLL circuit.

FIG. 7 is a circuit diagram showing one embodiment of the charge pump circuit included in the DLL analog section 3. As shown in FIG. In this example, as a capacitor for forming the control voltage VB (V _F in FIG. 1), the capacity of the memory cell MC is used. The storage capacitor of the memory cell MC is formed so that a leakage current does not occur regardless of miniaturization of the element so as to secure the data holding time. Therefore, even in a DRAM using a miniaturized MOSFET, the capacitor of the memory cell is changed to DLL (or PLL).
By being used for a low-pass filter of a circuit, a stable DLL or PLL operation can be performed. Since the capacitance value of the capacitor of one memory cell is minute, the capacitor of a plurality of memory cells is connected in parallel.

The charge pump circuit of this embodiment is not particularly limited, but in order to shorten the lock-in cycle of the DLL, a current source for a ΔDelay small mode comprising a P-channel MOSFET Q11 supplied with a signal ENB to the gate, ΔDelay medium mode current source consisting of an N-channel MOSFET Q22 supplied with a signal TURBO to the gate, ΔDelay large mode current source consisting of a P-channel MOSFET Q21 supplied with a signal TURBO1B to the gate, and the ΔDelay small mode current source , And current mirror biases Q12 to Q20 for transmitting the currents and bidirectional switches Q23 to Q26.

When the signal ENB is at a high level and ENT is at a low level and the DLL is not operating, the switch M
When the OSFETs Q15 and Q16 are turned off, the switch MO
SFETs Q17 and Q18 are turned on, and ΔDelay
The operation of the small mode current source and the current mirror circuit is stopped, and a low power consumption operation is performed. At this time, the signal TURB
MOSFET Q22 and Q21 by O and TURBO1B
Is turned off. The high-speed lock-in cycle operation using these three ΔDelay small mode current sources, ΔDelay medium mode current sources, and ΔDelay large mode current sources is as follows.

When the DLL is reset, the initial phase error is made to lead the phase. Therefore, the charge down control in the ΔDelay large mode is started. This ΔDe
In the large lay mode, since the phase error is advanced, the phase comparison output becomes high level, and two charge-up control signals are formed for one phase comparison operation. The phase error is sharply changed toward the target value by the charge-up control signal.

When the phase error exceeds the target value of the phase error 0, the mode is switched to the ΔDelay middle mode. ΔDela above
y Since the large mode is only charge-down control, ΔDe
In the lay mode, only charge-up control is performed. Therefore, the charge-up current source for ΔDelay large mode and ΔDelay
There is no charge mode current source for mid-lay mode. Of course, both may be required depending on how the initial phase error is given, and in that case, it is necessary to prepare them.

In order to correct the phase error that has been delayed beyond the delay error 0 in the large ΔDelay mode, the signal T
URBO goes high to turn on N-channel MOSFET Q22, which allows medium current to flow. Therefore, in order to correct the above-mentioned delay, the phase comparison output goes to a low level, and the high level of the up signal UP and the UP By the low level of B, the N-channel MOSFET Q23 and the P-channel MOSFET Q2
5 is turned on, and the signals UP and UP The control voltage VB is decreased stepwise correspondingly to B. As the control voltage VB falls as described above, the current formed by the P-channel MOSFET Q9 in FIG. 6 increases, and the operating current of the differential inverter forming the variable delay circuit increases, thereby reducing the delay time. Then, the phase is changed in a direction to correct the delay.

When the phase error exceeds the target value of the phase error 0 in the ΔDelay medium mode, the mode is switched to the ΔDelay small mode. ΔDelay small mode is MOSFET Q1
The charge-up control and the charge-down control using the small current formed in step 1 are performed according to the phase comparison output. At this time, ΔDelay
As in the large mode and ΔDelay medium mode, two pulses (U
Instead of forming (P / DOWN), one pulse is generated. As a result, in the small ΔDelay mode,
The error with respect to the phase error 0 is minimized.

The operation and effect obtained from the above embodiment are as follows. (1) Clock generation for forming the internal clock signal corresponding to a voltage held in a capacitor charged or discharged by a phase comparison output between an input clock signal input from an external terminal and an internally generated clock signal By providing a circuit and configuring such a capacitor using wiring capacitance, it is possible to generate a stable and stable jitter-free clock signal by suppressing leakage current due to miniaturization of elements. This has the effect of achieving an extremely high frequency.

(2) In addition to the above, a pair of electrodes of the above-mentioned wiring capacitance is formed in a multilayer structure by a multi-layer wiring technique, and extends in a direction perpendicular to the main surface of the semiconductor substrate by wiring and a contact portion connecting them. By forming, an effect that a large capacitance value can be secured with a small occupied area can be obtained.

(3) Forming the internal clock signal corresponding to the voltage held in the capacitor charged or discharged by the phase comparison output between the input clock signal input from the external terminal and the internally generated clock signal A clock generation circuit and a dynamic memory cell are provided, and a plurality of capacitors having the same structure as the storage capacitor of the dynamic memory cell are connected in parallel to each other. It is possible to generate a stable clock signal with reduced suppressed jitter, thereby obtaining an effect of substantially increasing the frequency of the clock signal.

(4) In addition to the above, as the clock generation circuit, an input clock signal input from an external terminal and an oscillation circuit for forming an internal clock signal are controlled so that the two coincide with each other. By using the PLL circuit for controlling the oscillation operation, an effect is obtained that an internal signal having an arbitrary frequency synchronized with the input clock signal can be formed.

(5) In addition to the above, as the clock generating circuit, a variable delay circuit for forming an internal clock signal obtained by delaying an input clock signal input from an external terminal by a predetermined delay time; By using a DLL circuit including a control circuit that compares the phase of the internal clock signal with the internal clock signal and controls the delay time so that the two coincide with each other, an internal clock signal synchronized with the input clock signal can be obtained. Is obtained.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, PL
Various embodiments can be adopted for a specific circuit forming the L circuit or the DLL circuit. The wiring capacitance is the same as that of FIG.
When using vertically formed electrodes by stacking multiple wiring layers as in the embodiment of FIG.
And two electrodes corresponding to VF and VF, respectively, and may be combined so as to overlap each other. Alternatively, it may be configured by stacking via an interlayer insulating film in a multilayer wiring. In this case, the odd-numbered wiring layers M1, M
3, M5 and the even-numbered wiring layers M0, M2, and M4 are mutually connected by the through holes.

When a capacitor is formed using a dynamic memory cell, a storage capacitor and an address selection MOSFET may be used. In the address selection MOSFET, the gate insulating film is formed relatively thick to increase the threshold voltage, and the leak current between the source and the drain (sub-threshold leak current) in the off state, that is, when the information charge of the memory is held, is small. Is done. Therefore, it is possible to gate capacitance of the address selection MOSFET is also used as a capacitor C _F which constitutes the low-pass filter of the PLL or DLL. The present invention provides a PL
It can be widely used in various semiconductor integrated circuit devices provided with a clock generation circuit such as an L circuit or a DLL circuit.

[0059]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. A clock generation circuit that forms the internal clock signal in accordance with a voltage held in a capacitor that is charged or discharged by a phase comparison output between an input clock signal input from an external terminal and a clock signal generated internally; By configuring such a capacitor using the wiring capacitance, it is possible to generate a stable and stable clock signal with a small amount of jitter, which suppresses a leak current due to miniaturization of the element. Is also planned.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a PLL circuit provided in a semiconductor integrated circuit device according to the present invention.

FIG. 2 is a configuration diagram showing one embodiment of a capacitor used in the PLL circuit of FIG. 1;

FIG. 3 is a block diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention.

FIG. 4 is an overall block diagram showing an embodiment of a synchronous DRAM to which the present invention is applied.

FIG. 5 is an overall block diagram showing one embodiment of a DLL of FIG. 4;

FIG. 6 is a circuit diagram showing one embodiment of a variable delay circuit included in the DLL analog unit of FIG. 5;

FIG. 7 is a circuit diagram showing one embodiment of a charge pump circuit included in the DLL analog unit of FIG. 5;

8 is a characteristic diagram for explaining a leakage current and the jitter of the relationship between the capacitor C _F in the PLL circuit.

[Explanation of symbols]

9 semiconductor chip, 10 internal circuit, 11 internal voltage generation circuit, 12-13 RAM macro cell (on-chip R
AM), 14 input / output circuit, 15 bonding pad, 16 internal circuit (enlarged pattern), 200A to 200D
Memory array, 201A-D ... row decoder, 202A
~ D: sense amplifier, 203A ~ D: column decoder,
204: address buffer, 205: row address buffer, 206: column address buffer, 207: column address counter, 208: refresh counter,
209: control circuit, 210: data input circuit,
211 data output circuit, 212 bank select circuit, 213 mode register, 214 DLL, 214
... DQS buffer.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03L 7/093 H01L 27/04 C 7/08 H03L 7/08 EZ F term (Reference) 5B024 AA03 AA15 BA02 BA21 BA23 CA01 CA07 CA21 5B079 BC03 CC03 DD08 DD13 5F038 AC04 AC05 BG05 CD13 DF05 DF06 DF11 EZ10 EZ20 5J106 AA04 CC01 CC24 CC52 CC53 CC58 CC59 DD01 DD32 GG01 HH03 JJ01 JJ04 KK02 KK25 KK37 KK38

Claims (5)

[Claims] 1. A phase comparison between an input clock signal input from an external terminal and a clock signal generated inside, and a capacitor charged / discharged by the comparison output and a voltage corresponding to the voltage held in the capacitor. A clock generation circuit for generating the internal clock signal, wherein the capacitor is configured using a wiring capacitance. 2. The semiconductor device according to claim 1, wherein the pair of electrodes of the wiring capacitor are formed in a multilayer structure by a multilayer wiring technique, and extend in a direction perpendicular to the main surface of the semiconductor substrate by wiring and a contact portion connecting the wiring to each other. A semiconductor integrated circuit device formed. 3. A phase comparison between an input clock signal input from an external terminal and a clock signal formed inside, and a capacitor charged / discharged by the comparison output and a voltage corresponding to the voltage held in the capacitor. A clock generation circuit in which the internal clock signal is formed, and a memory circuit configured using a dynamic memory cell, wherein the capacitor has the same structure as a storage capacitor configuring the dynamic memory cell. A semiconductor integrated circuit device comprising a plurality of devices connected in parallel. 4. The clock generating circuit according to claim 1, wherein the clock generating circuit controls an input clock signal input from an external terminal and an oscillation circuit forming an internal clock signal so that the input clock signal and the internal clock signal match. A semiconductor integrated circuit device including a PLL circuit that controls an oscillation operation of the oscillation circuit. 5. The variable delay circuit according to claim 1, wherein the clock generation circuit forms an internal clock signal obtained by delaying an input clock signal input from an external terminal by a predetermined delay time; A semiconductor integrated circuit device, comprising: a DLL circuit including a control circuit that compares the phase of a clock signal with the internal clock signal and controls the delay time so that the two match.