JP2002181899A - Method of calibrating timing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To calibrate timing to make a signal containing a jitter conform to other signal in their phases. SOLUTION: Fluctuation values Ta, Tb generated by the jitter contained in an input signal are measured to find an average value thereof, the phases of the both signals are made to conform to a phase position of the average value, and the timing is calibrated thereby, in timing calibration in which a voltage having about one-half of amplitude value compared with that of the input signal is impressed to a comparator as a reference voltage, in which a strobe pusle is impressed to the comparator, in which a level of the input signal in the impressing timing of the strobe pulse is classified into an H logic and an L logic while bounded by the reference voltage, to determine a relative phase difference between the input signal and the strobe pulse, and by which the phases of the input signal and the strobe pulse are made to conform to a prescribed relation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing calibration method used in a semiconductor device test apparatus for determining the quality of a semiconductor device such as a semiconductor memory or a logic IC.

[0002]

2. Description of the Related Art FIG. 2 shows an outline of a generally used semiconductor device test apparatus. Generally, a semiconductor device test apparatus includes a timing generator 11 and a pattern generator 12.
And a waveform shaper 13, a driver group 14, a comparator group 15, a logical comparator 16, a fail counter 17, and the like, and tests whether or not the device under test DUT operates normally. That is, the pattern generator 12 generates an address signal, test pattern data, and a control signal for the device under test DUT according to the reference clock generated by the timing generator 11. These signals are applied to a waveform shaper 13, shaped into a waveform required for a test, and applied to a device under test DUT through each driver DR constituting a driver group 14.

The device under test DUT is controlled to write and read test pattern data by a control signal. The test pattern data read from the device under test DUT is determined by each of the comparators CP constituting the comparator group 15 to determine whether or not a normal H logic voltage and a L logic voltage are provided. If a voltage is provided, the comparison result is input to the logical comparator 16. The logical comparator 16 compares the expected value data output from the pattern generator 12 with the read data, and determines the quality of the device under test DUT based on whether the data matches or not. The fail counter 17 counts the number of failures each time the logical comparator 16 detects a mismatch (fail), and determines whether or not rescue is possible based on the counted value.

In the comparator group 15, it is necessary to compare the logic levels of the read signals read from the device under test DUT at the timing of the strobe pulse, and to take the comparison results into the logic comparator 16. For this purpose, each comparator CP of the comparator group 15 is provided with a strobe pulse STB from the timing generator 11, and this strobe pulse STB
The level of the input signal at the time when
The voltage is compared with the logic and L logic voltages, and the comparison result is input to the logic comparator 16.

Therefore, the timing of applying the strobe pulse STB to the comparator CP needs to be calibrated to a certain known timing. This calibration will be referred to herein as strobe pulse timing calibration. FIG. 3 shows the timing calibration of the strobe pulse. The timing generator 11 applies a generation command of an input signal CAL, which is input to the comparator CP for timing calibration, to the pattern generator 12. The pattern generator 12 converts the generated data of the input signal CAL into the waveform shaper 1
3 to apply the input signal CAL to the signal input / output pin PN of the test apparatus through the waveform shaper 13 and the driver DR.

A comparator CP is connected to the signal input / output pin PN.
Is connected, and the input signal CAL and the strobe pulse STB are simultaneously output from the timing generator 11 (the generation timing of the signal of the timing generator 11 is defined as the reference phase of each test cycle here). The time T1 until the input signal CAL is input to the comparator CP via the signal input / output pin PN and the time T2 until the strobe pulse STB is input to the comparator CP are T1 = T2 as shown in FIG. Need to be.

When calibrating the timing of the strobe pulse STB, the calibration is completed by making the application timing of the strobe pulse STB substantially coincide with the center of the rising edge of the input signal CAL serving as a reference. That is, a variable delay circuit 18 (see FIG. 3) is provided on the supply path of the strobe pulse STB, and the strobe pulse STB is adjusted by adjusting the delay time of the variable delay circuit 18.
The calibration is performed by matching the application timing with the timing of the input signal CAL. FIG. 5 shows an actual calibration method. FIG. 5A
Represents expected value data given to the logical comparator 16, FIG. 5B shows a reference input signal CAL, and FIG. 5C shows a strobe pulse STB applied to the comparator CP. Input signal CAL
The expected value of the H logic near the rise timing of
Assuming that the comparison voltage of the comparator CP is set to the voltage VOH substantially at the center of the rising edge of the input signal, and the strobe pulse STB is gradually moved (searched) in the delay direction from the L logic side of the input signal CAL, the strobe pulse STB is input. If the signal CAL is on the L logic side, the output of the comparator CP is L logic, and this L logic does not match the expected value shown in FIG. 5A. Therefore, in this case, it is determined as fail (defective).

On the other hand, assuming that the strobe pulse STB gradually approaches the rising center of the input signal CAL from the H logic side of the input signal CAL, the comparator CP outputs H logic at first, and this H logic is shown in FIG. 5A. It is determined as a pass (good) because it matches the expected value. Eventually, the timing Tx (time from the reference phase position of the test cycle) determined by the comparison voltage VOH set in the comparator CP
, The leading phase side can be sorted into the fail area and the lagging phase side can be sorted into the pass area.

In order to detect that the strobe pulse STB matches the timing Tx to be calibrated, the following judgment is made. Each time the phase of the strobe pulse STB is changed, the comparison operation in the comparator CP and the logic comparator 16 is respectively executed a known number N times. Fail counter 1 counts the number of passes or failures during N comparison operations.
Count at 7. In a state where the timing of the strobe pulse STB is located on the L logic side of the input signal CAL, all fail during N comparison operations. In other words, if the number of comparison operations N is known, during the N comparison operations, if N failures are detected, it can be understood that the strobe pulse STB has missed the position of the L logic of the input signal CAL.

On the other hand, during N comparison operations, N passes (0
(N passes are known from the number of failures), it is understood that the phase of the strobe pulse STB exists on the H logic side of the input signal CAL. Assuming that the phase of the strobe pulse STB matches the target timing Tx,
Approximately half of the N comparison operations are passed, and the other half are failed. This phenomenon is considered to mean that the phase of the input signal CAL fluctuates slightly, so that the phase of the strobe pulse STB fluctuates by 1/2 on the leading side and on the lag side on the average on the basis of the position of the strobe pulse STB.

[0011]

As described above, in the semiconductor device test apparatus, the comparator CP and the logical comparator 1 are used.
6 and the strobe pulse S using the fail counter 17
Since the timing is calibrated by a method of detecting that the phase of TB and the input signal CAL match, if a relatively large jitter occurs in the reference signal, for example, the input signal CAL, the logical comparison result is 1/2 the fail
The range of counting each time is widened within the range of the jitter, which causes a problem that calibration cannot be performed correctly.

FIG. 6 shows this state. FIG. 6A shows a state where the rising timing of the input signal CAL fluctuates in the time range Tg due to jitter. FIG. 6B shows a state of the comparison operation when the input signal CAL to which jitter is applied is input to the comparator CP. The input signal CAL crossing the comparison voltage VOH spreads in the jitter range Tg,
Within this range Tg, the number of passes and failures varies according to the jitter, and the number of passes and failures does not converge to 1/2. As a result, the target timing Tx cannot be determined accurately.

In the above description, calibration is performed by using a pulse (referred to as an input signal) output from the driver DR as a reference, and adjusting a strobe pulse to the reference signal is referred to as calibration. ST
A pulse output from the driver DR based on B may be adjusted to the strobe pulse STB. The present invention can be applied to such a calibration. An object of the present invention is to propose a timing calibration method capable of correctly setting the timing of a strobe pulse STB to a target timing even in a situation where the phase of a reference input signal varies due to jitter. Things.

[0014]

According to a first aspect of the present invention, a timing of matching a phase of an input signal input to a comparator with a phase of a strobe pulse for reading a logical value of the input signal in a predetermined relationship. In the calibration method, a voltage within the range of the amplitude value of the input signal is applied as a comparison voltage of the comparator, and the logical value of the input signal is sorted into H logic and L logic based on the comparison voltage, and the rising or falling of the input signal A comparison operation for detecting the falling timing is executed, and a relative phase relationship between the input signal and the strobe pulse is gradually searched in the leading direction from the lagging direction and in the lagging direction from the leading direction, and the comparing operation is known at each search position. The first search position in which a comparison result in which H logic and L logic are mixed is obtained from the counting result of only H logic and the counting result of only L logic The advance calculated by the phase side and the delay phase side, proposes a timing calibration method for determining a calibration position with these advances targets the average value of the search positions calculated by the phase side and the delay phase side.

According to a second aspect of the present invention, in the timing calibration method according to the first aspect, the input signal is a signal input to a comparator after passing through a test pattern signal supply path in a semiconductor device test apparatus. Suggest a method. In claim 3 of the present invention, claim 1
In the described timing calibration method, a timing calibration method for adjusting the phase of the strobe pulse to the phase of the input signal based on the input signal is proposed. According to a fourth aspect of the present invention, there is provided the timing calibration method according to the first aspect, wherein the phase of the input signal is adjusted to the phase of the strobe pulse based on the phase of the strobe pulse.

[0016]

According to the timing calibration method of the present invention, even if jitter is superimposed on the signal to be calibrated, the width of the time range Tg of the jitter is determined, and this time range Tg
Is determined to determine the calibration position, the determined calibration position can be determined to be the center value of the time range Tg caused by jitter. As a result, there is an advantage that the calibration of the correct timing can be performed even for the signal on which the jitter is superimposed.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the embodiment shown in FIG. 1, the phase of a strobe pulse STB is adjusted to the phase of an input signal CAL with reference to the phase of an input signal CAL input to a comparator CP (see FIG. 2). Here is an example. Therefore, the phase of the strobe pulse STB is changed to the target phase position Tx
The phase is set to a more sufficiently delayed phase Tc (time from the reference phase position of the test cycle shown in FIG. 4). Assuming that the expected value data is set to H logic and that the expected value data of H logic is given to the logic comparator 16 (see FIG. 2) in synchronization with the generation of the input signal CAL, the application of the strobe pulse STB is performed. At timing Tc, the comparator CP is at H
Since the logic is output, the logic comparator 16 determines that the path is a pass.

Input signal CAL and strobe pulse STB
Is generated a known number N times, the strobe pulse ST
When the phase position of B is Tc, the count value of the pass of the fail counter 17 is N times. The phase of the strobe pulse STB is advanced slightly by little and a search is performed in the phase direction (indicated as search 1 in FIG. 1), and the comparator CP performs N comparison operations at each search position, and the fail counter 17 counts the number of failures. When the phase position of the strobe pulse STB reaches the trailing edge determined by the rising jitter of the input signal CAL and the phase position Tb crossing the comparison voltage VOH set in the comparator CP, the counting result of the comparison operation in the comparator CP becomes pass and fail. Is a mixed value.

Next, the phase position of the strobe pulse STB is set to a phase Td (FIG. 1D) which is sufficiently advanced from the target position Tx. In this setting state, the logical comparator 16 determines that all the comparison operations N have failed, and the fail counter 17 detects N failures. Strobe pulse S
The phase of the TB is searched slightly in the direction of the delay phase (indicated as search 2 in the figure), and the result of the determination by the logical comparator 16 is counted by the fail counter 17 at each search position. N
If the fail counter 17 has counted N failures during one comparison operation, the phase of the strobe pulse STB is searched in the delay direction.

The phase of the strobe pulse STB is equal to the leading edge generated by the jitter of the input signal CAL and the comparison voltage VO.
When the timing Ta at which H crosses is reached, a counting result in which fail and path coexist is obtained. According to the present invention, the phase positions Ta and Tb of the strobe pulse STB from which the counting result in which the pass and the fail are mixed are obtained first are obtained.
Average value of the phase positions Ta and Tb (Ta + Tb) 1/2
, The average value is determined as the target calibration position Tx.

As described above, the phase of the strobe pulse STB is searched to find the phase positions Ta and Tb where the path and the fail are mixed first, and the average value of the phase positions Ta and Tb is found, so that the jitter exists. Even if the signal is a phase reference signal, the other signal to be adjusted to the reference phase, in this example, the phase of the strobe pulse STB can be calibrated at the correct timing. As a specific example, if Ta is a timing of 5 ns from the reference phase position and Tb is a timing of 7 ns from the reference phase position, Tx = (5 + 7) / 2 =
6 ns, and Tx is 6 ns from the reference phase position.

In the above description, the input signal CAL input to the comparator CP is used as a phase reference signal. However, the present invention can be applied to a case where the strobe pulse STB is used as a phase reference signal. In this case, the phase of the input signal CAL may be searched from the leading phase side to the lagging phase side, and from the lagging phase side to the leading phase side, and the pass and fail may be counted at each search position.

[0023]

As described above, according to the present invention, accurate timing calibration can be performed even for a signal including jitter, and for example, the reliability of a test of a semiconductor device can be improved. Real benefits.

[Brief description of the drawings]

FIG. 1 is a timing chart for explaining a timing calibration method according to the present invention.

FIG. 2 is a block diagram for explaining an example of a device suitable for applying the present invention.

FIG. 3 is a block diagram for explaining a timing calibration method in the apparatus shown in FIG. 2;

FIG. 4 is a timing chart for explaining a relationship between a reference signal of a phase and a timing calibration method of a signal adjusted to the phase of the reference signal in the apparatus shown in FIG. 2;

FIG. 5 is a timing chart for explaining a conventional timing calibration method.

FIG. 6 is a timing chart for explaining inconvenience of the conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Timing generator 12 Pattern generator 13 Waveform shaper 14 Driver group 15 Comparator group DR driver CP comparator 16 Logical comparator 17 Fail counter 18 Variable delay circuit CAL Input signal STB Strobe pulse

Claims (4)

[Claims] 1. A timing calibration method for matching a phase of an input signal input to a comparator and a phase of a strobe pulse for reading a logical value of the input signal to a predetermined relationship, wherein the amplitude of the input signal is within a range of an amplitude value of the input signal. Is applied as a comparison voltage of the comparator, and the logic value of the input signal is sorted into H logic and L logic at the boundary of the comparison voltage to detect the rising or falling timing of the input signal. While performing the comparison operation, the relative phase relationship between the input signal and the strobe pulse is gradually searched from the leading direction to the lagging direction and from the lagging direction to the leading direction. At each search position, the comparing operation is performed a known number of times. From the count result of the logic only and the count result of the L logic only, advance to the first search position where the comparison result in which the H logic and the L logic are mixed can be obtained. A timing calibration method comprising: determining a target calibration position by obtaining an average value of search positions obtained on the advance phase side and the delay phase side. 2. The timing calibration method according to claim 1, wherein said input signal is a signal input to a comparator after passing through a supply path of a test pattern signal in a semiconductor device test apparatus. Method. 3. The timing calibration method according to claim 1, wherein the phase of the strobe pulse is adjusted to the phase of the input signal based on the input signal. 4. The timing calibration method according to claim 1, wherein the phase of the input signal is adjusted to the phase of the strobe pulse based on the phase of the strobe pulse.