JP2002181894A - Burn-in test apparatus and burn-in test method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable burn-in testing device capable of conducting surely screening for a plurality of measured devices (DUT hereinafter), and free from a secondary trouble in the DUT. SOLUTION: The each DUT has an input terminal, an output terminal and an electric power source terminal. At first, the each DUT is kept at a high temperature, and a test pattern is input to the input terminal thereof to operate the DUT. When the test pattern is input to the input terminal, an expected value expected to be output from the output terminal is output to determine whether the each DUT is troubled or not, using the expected value. In the DUT determined as the troubled one, the power source terminal thereof is disconnected from an electric power source to be short-circuited between the power source terminal and the power source. Only an operation of the DUT determined as the troubled one is stopped thereby.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a reliability test apparatus and a failure rate test apparatus, and more particularly to a dynamic burn-in apparatus and a burn-in test method for simultaneously testing a plurality of multi-pin semiconductor devices.

[0002]

2. Description of the Related Art In recent years, the speed, capacity, and number of bits of semiconductor devices have been remarkably increasing. As an example of speeding up, devices such as a CPU having an operation frequency exceeding 1 GHz have been developed. In addition, with the increase in capacity and the number of bits, the number of pins in a semiconductor device package is also rapidly increasing. As described above, even if the development of the semiconductor device progresses and the performance of the semiconductor device becomes higher, the failure rate in the market cannot be increased. In order to maintain and further reduce the failure rate in the market, it is necessary to ensure that screening before shipping does not bring defective products to the market, and to take prompt measures for the cause of failure of defective products dropped by screening. I have.

The change over time of the failure rate of an electronic component is represented by a bath-tub curve, and passes through an initial failure period in the first half, a random failure period in the middle half, and a wear failure period in the second half.
The failure rate during the initial failure period and the wear failure period is higher than the failure rate during the accidental failure period. In semiconductor devices, the time to the wear-out failure period is generally much longer than the service life of a system in which the semiconductor device is incorporated. Therefore, it is important to reduce the failure rate during the initial failure period. For this reason, a screening is performed in which the semiconductor device is used until the end of the initial failure period before the semiconductor device is put on the market, and only the semiconductor device that can be used continuously is put on the market. This screening is performed by a so-called accelerated test at a high temperature to shorten the time. This accelerated test is called a burn-in test and applies thermal and electrical stress to remove short-lived products.

[0004] In addition to the screening, the burn-in test also has a purpose of reducing the failure rate during the initial failure period. The cause of the failure of the failed semiconductor device is determined in the test, and the failure rate can be reduced by improving the production process so as to eliminate the cause.

However, even if a failure occurs due to thermal electric stress, if a stress continues to be applied to the failed semiconductor device, a secondary failure involving destruction due to the primary failure may occur. There is. This destruction hinders the initial investigation of the cause of the failure.

[0006]

Therefore, even when a large number of devices under test (DUTs) are tested simultaneously, each time the DUT fails, stress is not applied to the failed DUT. There is a need to. On the other hand, in order to advance the test efficiently, an unfailed DU
Interruption of the T test is undesirable. Therefore, the failed D
It is desirable to stop the application of the stress applied only to the UT immediately after the failure.

In order to shorten the burn-in test,
During testing, the DUT is heated as high as possible. However, there is an upper limit to the test temperature, since heating should not cause new damage to non-defective products. The burn-in test is performed at a constant temperature at which the acceleration of defective products is justified from such a background.

However, in the burn-in test, the temperature of the DUT becomes high even when current is applied, and the test is accelerated. However, DUT
However, simply energizing the DUT cannot energize the internal circuit of the DUT to generate heat. That is, it cannot be said that the state of actual use of the DUT in the market is accelerating. Therefore, in the burn-in test, a predetermined test pattern having a determined energization pattern is used. That is, the burn-in test requires a test pattern generation circuit. Such a test is particularly called a dynamic burn-in test because an internal circuit of the DUT operates with a signal from the test pattern generation circuit. Since the dynamic burn-in test can raise the temperature of an internal circuit that operates locally, screening according to the actual use situation is possible. That is, in the burn-in test, by performing the dynamic burn-in test, it is considered that reliable screening without leakage can be performed.

FIG. 10 is a circuit diagram of a dynamic burn-in device assumed as a basic structure. In the dynamic burn-in test apparatus, a large number of devices under test DUT1 to DUT3
Is stored in a thermostat 1, an appropriate input pattern signal is applied to the devices under test DUT 1 to 3 by the test apparatus 2 to the input pins IN 1 to IN 3, and the output pattern signals of the output pins OUT 1 to OUT 3 are supplied to an expected value generation circuit in advance. 4 and the pass / fail determination circuit 5 compares the predicted value with the expected value. If the values do not match, the devices under test DUT1 to 3 are determined to be faulty. A DC power supply 6 is connected to the devices under test DUT1 to DUT3.

In the burn-in test apparatus, since the time required for the test ranges from several hours to several tens of hours, a large number of devices under test DUT1 to DUT3 are tested simultaneously. As a result, the input pins IN1 of the devices DUT1 to DUT3 are
If the test apparatus 2 is connected in parallel every 3 to 3, the test apparatus 2 only needs to have one test pattern generation circuit 3 and one expected value generation circuit 4 in order to generate an input pattern signal. On the other hand, the pass / fail judgment circuit 5 determines whether the device under test D
Since the comparison is always made with the expected value for each of the UTs 1 to 3, it is necessary to prepare the same number of devices under test DUTs 1 to 3.

When the number of DUTs to be tested at one time in the thermostat 1 is about 30 and the number of input pins and output pins of the DUT is about 200, signal lines which enter and exit the thermostat 1 are assumed. Will reach 6200.

FIG. 11 is a circuit diagram showing the device under test DUT 1 and the test apparatus 2 shown in FIG. 10 in more detail. First, the devices under test DUT1 to DUT3 will be discussed in detail. At present, it has been found that 95% of semiconductor device integrated circuits (ICs) on the market have a CMOS type structure. Therefore, it is considered that there is sufficient demand even for a burn-in test apparatus specialized for a CMOS type IC. Further, from the viewpoint of the cause of the failure in the burn-in test, even if the CMOS type is a highly integrated IC, the input pins IN1 to IN3 and the output pins OUT1 to OUT3 are used.
It has been found that the period can be represented by a simple circuit as shown in FIG. For example, the input pin IN1 is connected to the anode of the diode D11, the cathode of the diode D12, and the p-channel MO.
SFET (T11) and n-channel MOSFET (T1
2) connected to the gate. The output pin OUT1 is T
11 and the drain of T12. T
The drain of D11 and the cathode of D11 are connected to the VDD pin. The source of T12 and the anode of D12 are VS
It is connected to the S pin and the GND pin. Other input pins I
The same applies to the circuit between N and the output pin OUT. Also, V
The capacitor C connected between the DD pin and the VSS pin is connected to the FETs T11, 12, 21, 22, 31, 3, and 3.
2 is equivalently showing a capacitance including a junction capacitance, a wiring capacitance, and the like. D11 and D12 are connected to the input pin IN1 and the like so that when a signal of a nonstandard voltage is applied to the input pin IN1 or the like, the voltage is applied to the gate insulating film so as not to be broken.
And a current flows in the direction of the VDD terminal via D12 and returns the voltage to within the standard.

A resistor Ri11 connected to the input pin IN1 or the like
Function to prevent the occurrence of overcurrent. Resistance Ri11
Are connected to the test pattern generation circuit 3. Thus, the test patterns 7 to 9 can be input to the input pin IN1 and the like. A DC power supply 6 of a voltage V is connected between the VDD pin and the VSS pin. This allows T1
Switching operations of 1, 12, 21, 22, 31, and 32 can be performed. The output pin OUT1 or the like is connected to an input terminal such as an exclusive OR ExOR1 of the pass / fail determination circuit 5. The other input terminal of the exclusive OR ExOR1 or the like is connected to a terminal of the expected value generation circuit 4 which outputs the expected value of OUT1.

The expected value generation circuit 4 is connected to the test pattern generation circuit 3 and outputs the signal OUT1 according to the test pattern 7 or the like.
Output the expected value 1 and the like output from. That is, the circuit 4 may be a device that operates normally with the same semiconductor device as the DUT 1. As a result, 1 can be set to the output terminal such as ExOR1 only when the output such as OUT1 is different from the expected value. Exclusive OR ExOR
Output terminals such as 1 are connected to the input terminal of the logical OR.
Thus, when the output differs from the expected value in at least one or more places such as OUT1, 1 can be set to the output terminal of the OR. Then, it can be determined that the DUT 1 has failed by the fact that "1" is set at the output terminal of the OR.

It is also possible to determine whether or not the DUT 1 has failed by monitoring the current flowing through the VDD pin and determining whether an overcurrent has flown or the power consumption is within a specified value. Can be.

However, in the burn-in test apparatus shown in FIGS. 10 and 11, for example, even if a failure of the DUT 1 is detected, the voltage V of the power supply 6 and the test patterns 7 to 9 are continuously applied to the DUT 1. That is, the DUT 1 continues to operate.

Therefore, as shown in FIG. 12, switching circuits 11, 21, 31 are connected on the connection between the VDD pin and the power supply 6.
Was provided. In the burn-in test, first, the DUTs 2 and 3 are tested in the ON state as in the switching circuits 21 and 31. Then, for example, when the DUT 1 fails, the switching circuit 11 receives a signal indicating this from the pass / fail determination circuit 5, and changes to the OFF state as shown in FIG.

However, even when the switching circuit 11 is in the OFF state, the test patterns 7 to 9 are applied as shown in FIG.
A current flows through the capacitors 1 and 31, the electric charge is accumulated in the capacitor C, and the potential VD is boosted. As a result, a situation arises for T11 and the like as if the switching circuit 11 is in the ON state, and a signal is output from the output pin OUT1 and the like. That is, even if the switching circuit 11 is turned off, the DUT 1 continues to operate.

Therefore, as shown in FIG. 14, switching circuits 13, 23, and 33 are provided after branching to the test apparatus 2 and each input pin on the connection such as the input pin IN11. The switching circuit 13 and the like have switches in all connections connected to the input pins IN1 to IN3 of the DUT1 and the like, and all of these switches open and close in conjunction with each other. In the burn-in test, first, the switching circuits 21, 2
The test is performed in the ON state as in 3, 31, and 33. For example, when the DUT 1 has failed, a signal indicating this is sent from the pass / fail determination circuit 5 to the switching circuits 11 and 13.
Changes to the OFF state as shown in FIG.

Indeed, the switching circuits 11 and 13 are
In the FF state, as shown in FIG. 15, the test patterns 7 to 9 are not applied, and the operation of the DUT 1 can be stopped. However, in the burn-in test apparatus as shown in FIG. 14, switches are required by the number of input pins. Since the number reaches several thousands, it is necessary to increase the reliability of the switch and the switching circuit 13 and the like. In order to improve the reliability, it is effective to integrate the switches. It is desirable that the switching circuit 13 and the like be integrated on a semiconductor substrate to form a single chip.

Furthermore, the inventors have thought that the number of switches should be drastically reduced to provide a more reliable burn-in test apparatus.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a burn-in test apparatus which reliably screens a plurality of DUTs, has high reliability, and does not cause a secondary failure in the DUT. To provide.

Another object of the present invention is to provide a plurality of DUTs.
The present invention provides a burn-in test method that reliably screens, does not cause a secondary failure in a DUT, and has high reliability.

[0024]

In order to achieve the above-mentioned object, a first feature of the present invention is to provide a thermostat capable of holding a plurality of DUTs having an input terminal, an output terminal, a power supply terminal and a ground terminal at a high temperature. A test pattern generating circuit that generates a test pattern that can be connected to the input terminal and that can operate the DUT, and that the test pattern is input to the test pattern generating circuit and the test pattern is input to the input terminal A test apparatus having an expected value generation circuit that outputs an expected value expected to be output from an output terminal, and a pass / fail determination circuit that determines whether or not the DUT has failed using the expected value; A first switching circuit that is connected to the pass / fail determination circuit and opens between the power supply terminal and the power supply when the determination is faulty; To, in burn-in test apparatus and a second switching circuit for short-circuiting between the power supply terminal and the ground terminal. As a result, the DUT determined to be faulty
Only the operation of can be stopped.

A first feature of the present invention is that a pass / fail judgment circuit is
It is more effective to determine that the DUT is faulty when the output of the output terminal does not match the expected value.

According to a first feature of the present invention, there is further provided an overcurrent detection circuit connected to a pass / fail judgment circuit for detecting an overcurrent flowing through a power supply terminal or a ground terminal, and a pass / fail judgment circuit when an overcurrent is detected. Is more effective in determining that the DUT has failed.

A first feature of the present invention is that a first overcurrent, which is connected to a pass / fail determination circuit and detects a first overcurrent flowing through a power supply terminal, is provided.
An overcurrent detection circuit, and an overcurrent detection circuit connected to the pass / fail determination circuit and detecting a second overcurrent flowing through the ground terminal. The expected value can be output to the output terminal. It is more effective to determine that a failure has occurred when the first overcurrent or the second overcurrent is detected. A signal appearing at the output terminal of a normal LSI is uniquely determined while an evaluation signal (test vector) for performing a functional test is applied to the input terminal. That is, what value the output terminal of the normal DUT (LSI) takes can be uniquely determined and described by the input test vector. In the present invention, the value of the described signal is applied to the output terminal of the LSI serving as the DUT. If the function of the DUT is normal, since the signal level applied to the output terminal of the DUT is equal to the signal level of the output of the internal circuit of the DUT, the voltages are balanced and no current flows. In a normal CMOS, no current flows at all in a quiescent state, and a DC current called a through current and a capacitive charge / discharge current flow only when the logic is inverted. Therefore, if the internal circuit of the DUT has a CMOS type structure and a predetermined expected value is applied to the output terminal of the DUT, a DC current should not substantially flow through the DUT. Therefore, a failure of the DUT can be detected by detecting a current that should not flow as an overcurrent.

A second feature of the present invention is that a plurality of DUTs having an input terminal, an output terminal, a power supply terminal, and a ground terminal are maintained at a high temperature, a test pattern is input to the input terminal, and these DUTs are operated. Causing the DUT to output an expected value expected to be output from the output terminal when a test pattern is input to the input terminal; and determining whether each of the DUTs has failed using the expected value. And, if the determination is a failure, open between the power supply terminal and the power supply of the DUT determined to be a failure,
And a step of short-circuiting between the power terminal and the ground terminal.

[0029]

Embodiments of the present invention will be described below with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals.

(First Embodiment) FIG. 1 is a circuit diagram of a dynamic burn-in device according to a first embodiment of the present invention. In the burn-in device shown in FIG. 1, in addition to the burn-in device shown in FIG. 14, switching circuits 12, 2 are provided between the VDD terminals and the VSS terminals of the DUTs 1 to 3, respectively.
2, 32 were provided. In the burn-in test, first, the test is performed with the switching circuits 21 and 31 in the ON state and the switching circuits 22 and 32 in the OFF state. For example, when the DUT 1 fails, the switching circuits 11 and 12 receive a signal indicating this from the pass / fail determination circuit 5, and the switching circuit 11 changes to the OFF state and the switching circuit 12 changes to the ON state as shown in FIG. I do.

FIG. 2A shows a burn-in test.
FIG. 3 is a diagram for explaining a situation in which stress is applied to Since the switching circuit 21 is in the ON state and the switching circuit 22 is in the OFF state, the voltage V can be applied from the power supply 6 between the VDD terminal and the VSS terminal. This allows the FET, T11, 12, 21, 22, 3,
1 and 32 are capable of performing a switching operation, and output outputs according to test patterns 7 to 9 to output terminals OUT1 to OUT3.
Generate from.

FIG. 2B shows a burn-in test.
FIG. 4 is a diagram for explaining a situation in which application of stress to the substrate is stopped. The switching circuit 11 is off and the switching circuit 12 is on. First, since the switching circuit 11 is in the OFF state, the voltage V from the power supply 6 is not applied between the VDD terminal and the VSS terminal. In addition, unlike the case of FIG. 13, when the switching circuit 12 is in the ON state, the test patterns 7 to 9 are applied, so that the diodes D11,
Even if a current flows through 1 and 31, a current flows through the switching circuit 12 without accumulating charge in the capacitor C,
The potential VD is not boosted. This allows F
For ET, T11, T12, T21, T22, T31, T32, the switching operation is disabled, and the test patterns 7 to 9 are disabled.
Regardless, the operation of the DUT 1 can be stopped.
The current values of the currents flowing through the diodes D11, D21, D31 can be adjusted by the resistance values of the resistors Ri11, R12, D13 so that an overcurrent does not flow.

That is, there are the following two methods for shutting off the power supply 6 from the DUT 1 or the like. The first method is a method in which a switch is provided on the power supply side of the DUT 1 as in the case of the switching circuit 11, and the switch is opened to cut off. In the second method, as in the switching circuit 12, D
This is a method in which a switch is provided in parallel with the UT 1 and closed by closing the circuit.

In the burn-in device, since the signal is given to all the DUTs 1 to 3, application of the signal is continued even after the power supply 6 is cut off. DUT1 to DUT3 have protection diodes D11 and D12 for destruction prevention inserted in parallel with input terminals IN1 to IN3. Therefore, the drive signal charges the power supply line inside the DUT 1 and the like through the diode D11 and the like.

Therefore, in the first method in which the power supply terminal of the DUT 1 is opened, the specimen continues to operate even when power is not supplied. Therefore, the purpose of stopping the application of stress cannot be satisfied. On the other hand, also in the second method, when the switches provided in parallel to the DUT 1 are shut off by closing, the power supply is short-circuited. Therefore, the first and second methods are used together. That is, the switching circuit 11 and the like are provided independently in series between the power supply 6 and the DUT 1 and the like, and the switching circuit 12 and the like are independently provided in parallel with the DUT 1 and the like. When the DUT 1 and the like are operating normally, the switching circuits 11 and the like connected in series are ON,
The switching circuits 12 and the like connected in parallel are turned off. When the DUT 1 or the like abnormally operates, it is necessary to turn off the switching circuits 11 and the like connected in series and turn on the switching circuits 12 and the like connected in parallel.

FIG. 3 shows a detailed circuit diagram of the switching circuits 11 and 12 and their peripheral circuits. Switching circuit 1
1 denotes n-channel FETs T1 and T3 and an operational amplifier O
P1, a resistor R1, and a power supply V for generating a reference voltage Vr.
r. T1 is a series switch and further has a source / drain electrode connected to the VDD terminal of the DUT1 and the positive terminal of the power supply 6 as a control transistor. The gate electrode of T1 is connected to the output terminal of OP1, one input terminal of OP1 is connected to the VDD terminal, and the other input terminal of OP1 is
It is connected to the VSS terminal of DUT1 via the source / drain electrode of T3, and is connected to the positive terminal of the power supply Vr via the resistor R1.
Connect to pole. The negative pole of the power supply Vr is equal to the negative pole of the power supply 6 and VS.
Connect to S terminal. The gate electrode of T3 is a self-holding circuit 1.
Through 0, it is connected to the output terminal of the logical OR which is the output terminal of the judgment result of the pass / fail judgment circuit 5.

The switching circuit 12 has an n-channel FE
It is composed of T2 of T. T2 is a parallel switch whose source and drain electrodes are connected to the VDD and VSS terminals of DUT1. The gate electrode of T2 is connected via the self-holding circuit 10 to the output terminal of the logical OR which is the output terminal of the judgment result of the pass / fail judgment circuit 5. Note that the output of the OR of the circuit 5 is a logical comparison error of the response of the DUT1,
Even if an error occurs once depending on the state of the failure in T1, the error does not always occur continuously thereafter. A self-holding circuit 10 for holding an error occurrence signal is provided so that the application of subsequent stress can be stopped by the first error.
The circuit 10 can be omitted depending on the DUT 1 and measurement conditions.

Next, the operation of the switching circuits 11 and 12 will be described. First, an operation when applying stress to the DUT 1 will be described. First, a reset signal is input to the self-holding circuit 10, and an output signal is set to L level. Since the gate electrode of T2 becomes L level, T2 and the switching circuit 12 are turned off. Further, when the output signal of the circuit 10 is set to L level, the gate electrode of T3 becomes L level, so that T3 is turned off. The potential at the input terminal of OP1 connected to the resistor R1 rises, which causes OP1 to output an H level from the output terminal. T1
, The switching circuit 11 is turned on.

Next, the operation for stopping the application of stress to the DUT 1 will be described. The pass / fail judgment circuit 5 detects a failure and outputs an H-level signal as a failure signal. An H-level signal is input to the self-holding circuit 10, and the output signal is H-level.
Set to level. Since the gate electrode of T2 becomes H level, T2 and the switching circuit 12 are turned on. In addition, the gate electrode of T3 also becomes H level,
3 is turned on. Since the input terminal of OP1 connected to the resistor R1 is short-circuited to the negative electrode of the power supply Vr, the potential drops,
This causes OP1 to output the L level from the output terminal.
Since the gate electrode of T1 becomes L level, T1 and the switching circuit 11 are turned off. The other switching circuits 21, 22, 31, 32, etc. have the same structure and operate in the same manner.

(Second Embodiment) FIG. 4 is a circuit diagram of a dynamic burn-in device according to a second embodiment of the present invention. In the burn-in device shown in FIG. 4, in addition to the burn-in device shown in FIG.
5 and 16 were provided. Thus, in the burn-in test, for example, when the DUT 1 fails, the VUT of the DUT 1
If an overcurrent flows between the DD terminal and the positive terminal of the power supply 6, the overcurrent is detected by the circuit 14, and a signal {VD
D1 is output to the pass / fail judgment circuit 5 of the test apparatus 2. The circuit 5 determines a failure and outputs the determination result to the switching circuit 1.
1 and 12 and the switching circuit 11 as shown in FIG.
Changes to the OFF state, and the switching circuit 12 changes to the ON state. As described above, the present invention, when a failure occurs in the DUT 1 or the like, shuts off a power supply or the like to the DUT 1 or the like and avoids a secondary failure.

FIG. 5 is a detailed circuit diagram of peripheral circuits such as the switching circuits 11 and 12 and the overcurrent detection circuit 14.
5, an overcurrent detection circuit 14 is newly added as compared with FIG. The circuit 14 includes a current detection resistor R2 and an overcurrent detection differential amplifier OP2. The resistance R2 is DU
It is inserted into the connection between the VDD terminal of T1 and the + pole of the power supply 6. The two input terminals of OP2 are connected to both ends of the resistor R2, and the output terminal is connected to the input terminal of the logical OR of the pass / fail determination circuit 5.

Next, the operation of the overcurrent detection circuit 14 will be described. The operation of the other switching circuits 11, 12, etc. is shown in FIG.
It is omitted because it is the same as First, when a failure occurs in the DUT 1 and an overcurrent flows through the resistor R2, a voltage is generated across the resistor R2. This voltage is amplified by OP2, and if the amplified voltage △ VDD1 reaches a voltage at which the logical OR of the pass / fail determination circuit 5 can be recognized as the H level, the circuit 5 detects a failure and generates a failure signal. An H level signal is output. OP2 may be a differential amplifier having an appropriate offset. It is set so that a signal at which the logical sum OR becomes H level is output only when an overcurrent flows. In addition,
The other overcurrent detection circuits 15 and 16 have the same structure and operate in the same manner.

FIG. 6 shows a method of determining a failure for each specific state of the DUT 1. The structure of the DUT 1 shown in FIG. 6 is equal to the structure of the DUT 1 in FIG. In FIG.
Diode D11 unnecessary in the following description of the failure determination method
Etc. and the description of the condenser C are omitted. In addition, FETs, T41 and T42, have been added to illustrate possible situations. During the burn-in test, the specimen is monitored for proper functioning. Whether the response is correct, or whether the power consumption is within a specified value is the criterion.

(1) First, a normally operating FET, T1
1 and T12 will be described. A test pattern 7 or the like is generated by the test pattern generation circuit 3, and the input terminal IN
Since L is input to 1 and L is input to the gate electrodes of T11 and T12, T11 is turned on and T12 is turned off.
State. Then, the output terminal OUT1 outputs H,
The input terminal of ExOR1 of the pass / fail judgment circuit 5 is set to H. On the other hand, the expected value generating circuit 4 receives the test pattern 7 and the like and outputs H to the input terminal of ExOR1. E
In xOR1, since both input terminals are set to H, the output terminal indicates that no failure has occurred.
Is output.

(2) A case where T22 fails and operates abnormally will be described. The test pattern 8 and the like are generated in the circuit 3, L is input to the input terminal IN2, and L is input to the gate electrodes of T21 and T22. The normal T21 is in the ON state, and the failed T22 cannot be in the OFF state and is in the ON state. Since T21 and T22 are simultaneously turned on, a through current flows, and this through current is detected by the overcurrent detection circuit 14 as an overcurrent. Based on this detection, the circuit 5 determines that a failure has occurred. Further, since T21 and T22 are simultaneously turned on, the output terminal OUT2 cannot output H, and the input terminal of ExOR2 of the circuit 5 cannot be set to H. On the other hand, the circuit 4 outputs H to the input terminal of ExOR2. In ExOR2, the input terminal is set to a non-matching state other than H and H, so that H indicating that a failure has occurred is output from the output terminal.

(3) Normally operating FETs T31 and T31
The case of 32 will be described. The test pattern 9 and the like are generated in the circuit 3, H is input to the input terminal IN3, and T31
And H is input to the gate electrode of T32, so that T31 is turned off and T32 is turned on. The output terminal OUT3 outputs L, and the input terminal of ExOR3 is L.
Set to. On the other hand, the circuit 4 outputs L to the input terminal of ExOR3. In ExOR3, both input terminals are L
, L is output from the output terminal.

(4) A case where T42 breaks down and operates abnormally will be described. The test pattern 8 and the like are generated in the circuit 3, H is input to the input terminal IN4, and H is input to the gate electrodes of T21 and T22. The normal T41 is turned off, and the failed T42 cannot be turned on,
It becomes F state. The output terminal OUT4 cannot output H, and the input terminal of ExOR4 of the circuit 5 cannot be set to L. On the other hand, the circuit 4 outputs L to the input terminal of ExOR4. In ExOR4, the input terminal is set to a non-coincidence state other than L and L, so that H indicating that a failure has occurred is output from the output terminal.

Even when a failure occurs in the p-channel FET T11 or the like, the circuit 14 is switched in the same manner as in (2) and (4).
To detect an overcurrent, or the circuit 5 can determine a failure by comparing the output from the output terminal OUT1 or the like with an expected value.

(Third Embodiment) FIG. 7 is a circuit diagram of a dynamic burn-in device according to a third embodiment of the present invention. The dynamic burn-in device of FIG.
An input signal for operating an internal circuit of each of the DUTs 1 to 3 is applied to input terminals IN1 to IN3 of each of the DUTs 1 to 3 and a constant temperature chamber 1 for storing devices under test DUT1 to 3 such as SIs. Output terminals OUT1
A test device 2 for applying an expected value of an output from an internal circuit of each of the DUTs 1 to 3 to the DUTs 1 to 3;
And a power supply 6 for applying a predetermined power supply voltage V to a VSS terminal via a ground line, and an overcurrent detection circuit 14 disposed on each of the power supply line and the ground line. To 19, the switching circuits 11, 21, 31 arranged on each of the power lines, and the switching circuit 1 arranged between each of the power lines and the ground line
2, 22, 32. Here, a plurality of DUTs 1 to 3 are actually mounted on the DUT board, and a plurality of DUT boards are stored in the thermostatic chamber 1.
FIG. 7 omits the DUT board for simplicity. The thermostat 1 may be set to a predetermined temperature, for example, 125 ° C. to 140 ° C.

In the dynamic burn-in according to the first and second embodiments, an appropriate signal is supplied from the test apparatus 2 to the DUT board, and the signals at the output terminals OUT1 to OUT3 are monitored to determine the pass / fail. For this purpose, if the number of output terminals per DUT is Q and the number of DUTs is n, comparison with expected values is performed using n × Q wirings. However, in the third embodiment, the output terminals OUT1 to OUT3 are individually compared with the expected value to determine whether or not the output terminals OUT1 to OUT3 pass or fail. Therefore, Q lines of output terminals per DUT are connected in parallel to the output terminals OUT1 of each DUT. To 3.

The actual number P of the input terminals IN1 to IN3 and the number Q of the output terminals OUT1 to OUT3 are all 50 to 200 or more. Is simplified as shown in FIG. Similarly, although only three DUTs are shown, it goes without saying that the number n of DUTs may be 30 to 500 or more. All the input terminals IN1 to IN3 can be connected in parallel from the output terminals IN1 to IN3 of the test apparatus 2 via predetermined resistors Ri11 to Ri13. DUT output terminal OU
Since a predetermined expected value only needs to be applied to T1 to T3, it can be connected in parallel with the output terminals OUT1 to OUT3 of the test apparatus 2 via the resistors Ro11 to Ro13 and the like. Does not increase even if the number n of DUTs increases.

FIG. 8 is a detailed circuit diagram of peripheral circuits of the switching circuits 11 and 12 and the overcurrent detection circuits 14 and 17. 8, an overcurrent detection circuit 17 is newly added as compared with FIG. On the other hand, the exclusive OR ExOR1 and the like are omitted from the pass / fail determination circuit 5. Circuit 17 is Circuit 1
4 is configured in the same manner. Other switching circuit 1
1 and 12 and the operations of the overcurrent detection circuits 14 and 17 are shown in FIG.
Therefore, the description is omitted. Overcurrent is present in circuits 14, 17
, H is output from OP2 and OP3. When at least one of the input terminals of the logical OR of the pass / fail determination circuit 5 is set to H, H indicating that the DUT 1 is faulty is output from the output terminal of the OR. As described above, the output of the output terminal of the DUT 1 is not referred to in determining the failure.

FIG. 9 shows a method of determining a failure for each specific state of the DUT 1. The structure and failure state of the DUT 1 shown in FIG. 9 are the same as those of the DUT 1 shown in FIG. During the burn-in test, it is monitored whether the DUT is functioning properly. Whether the power consumption is within a specified value is a criterion. In a CMOS logic circuit, a through current and a capacitive charge / discharge current may flow when the state of an internal circuit changes. Conversely, no DC current flows except when the state is inverted. However, if a failure occurs in a logic circuit due to various reasons such as a failure of a gate oxide film of a MOSFET constituting an internal logic circuit, a failure of a metal wiring due to electromigration, etc. Also, the power supply current IDD of the DC current and the ground current ISS flow.

(1) First, a normally operating FET, T1
1 and T12 will be described. A test pattern is generated by the test pattern generation circuit 3, L is input to the input terminal IN1, and L is input to the gate electrodes of T11 and T12, so that T11 is turned on and T12 is turned off. Then, the output terminal OUT1 outputs H. On the other hand, the expected value generation circuit 4 receives the test pattern and outputs H to the input terminal of the amplifier AMP1 of the pin driver 20. H is output from the output terminal of AMP1 to the output terminal OUT1 of DUT1. In both cases, OUT1 is set to H, so that no current flows through OUT1. Therefore, the circuits 14 and 17 do not detect an overcurrent.

(2) A case where a logic circuit including T21 and T22 fails and operates abnormally will be described. A test pattern is generated in the circuit 3, L is input to the input terminal IN2, and L is input to the gate electrodes of T21 and T22. T
Since the logic circuit including 21 and T22 has failed, T2
1 is turned off and T22 is turned on. As a result, the output terminal OUT2 is set to L. On the other hand, the circuit 4 outputs H to the input terminal of AMP2. H is output from the output terminal of AMP2 to the output terminal OUT2. Since the output level at OUT2 is different from the level set by AMP2, an overcurrent flows through T22 and the circuit 17. This overcurrent is detected by the circuit 17. Based on this detection, the circuit 5 determines that a failure has occurred. As a current source of the overcurrent, a power supply of the pin driver 20 and the like can be considered.

(3) A case where a logic circuit including T31 and T32 operates normally will be described. A test pattern is generated in the circuit 3, H is input to the input terminal IN1, and T3
Since H is input to the gate electrodes of T1 and T32, T31
Is in the OFF state, and T32 is in the ON state. Then, the output terminal OUT3 outputs L. On the other hand, the circuit 4 receives the test pattern and outputs L to the input terminal of the amplifier AMP3 of the pin driver 20. L is output from the output terminal of AMP3 to the output terminal OUT3 of DUT1. In both cases, OUT3 is set to L, so that no current flows through OUT3. Therefore, the circuits 14, 1
7, no overcurrent is detected.

(4) A case where a logic circuit including T41 and T42 fails and operates abnormally will be described. A test pattern is generated in the circuit 3, H is input to the input terminal IN4, and H is input to the gate electrodes of T41 and T42. T
Since the logic circuit including T41 and T42 has failed, T4
1 turns on, and T42 turns off. As a result, the output terminal OUT4 is set to H. On the other hand, the circuit 4 outputs L to the input terminal of AMP4. L is output from the output terminal of AMP4 to the output terminal OUT4. Since the output level at OUT4 is different from the level set by AMP4, an overcurrent flows through T41 and the circuit 14. This overcurrent is detected by the circuit 14. By this detection, the circuit 5 determines that a failure has occurred.

That is, if there is an abnormality in the logic circuit inside the DUT 1, an abnormal current always flows through the circuit 14 or 17. Therefore, DU is detected by detecting the overcurrent.
The failure of T1 can be determined.

As described above, the present invention has been described with reference to the three embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art. For example, in FIGS. 4 and 5, a means for detecting a voltage drop between both ends using a current detecting resistor has been described as a current detecting means. However, a circuit using a Hall element may be used as the current detecting means. Of course.

As described above, it should be understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention is limited only by the matters specifying the invention described in the claims that are reasonable from this disclosure.

[0061]

As described above, according to the present invention,
It is possible to provide a burn-in test apparatus that reliably screens a plurality of DUTs, has high reliability, and does not cause a secondary failure in the DUT.

Further, according to the present invention, it is possible to provide a burn-in test method which reliably screens a plurality of DUTs, has high reliability, and does not cause a secondary failure in the DUT.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a dynamic burn-in device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a part of FIG. 1 in more detail for explaining a method of applying a stress to a DUT and stopping the stress in the dynamic burn-in device according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram for realizing the application of stress to the DUT and its stop in the dynamic burn-in device according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram of a dynamic burn-in device according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram for realizing application of a stress to a DUT and its stop in a dynamic burn-in device according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram for explaining a method of detecting a failure of a DUT of a dynamic burn-in device according to a second embodiment of the present invention.

FIG. 7 is a configuration diagram of a dynamic burn-in device according to a third embodiment of the present invention.

FIG. 8 is a circuit diagram of a dynamic burn-in device according to a third embodiment of the present invention for applying a stress to a DUT and stopping the stress.

FIG. 9 is a circuit diagram for explaining a method of detecting a failure of a DUT of a dynamic burn-in device according to a third embodiment of the present invention.

FIG. 10 is a circuit diagram of a dynamic burn-in device assumed as a basic structure.

FIG. 11 is a circuit diagram showing a part of FIG. 10 in more detail;

FIG. 12 is a circuit diagram of a dynamic burn-in device (part 1) assumed to facilitate understanding of the present invention.

FIG. 13 is a circuit diagram showing a part of FIG. 12 in more detail;

FIG. 14 is a circuit diagram of a dynamic burn-in device (part 2) assumed to facilitate understanding of the present invention.

FIG. 15 is a circuit diagram showing a part of FIG. 14 in more detail;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 constant temperature bath 2 test device 3 test pattern generation circuit 4 expected value generation circuit 5 pass / fail judgment circuit 6 power supply 7, 8, 9 test pattern 10 self-holding circuit 11, 21, 31 switching circuit connected in series 12, 22, 32 parallel Connected switching circuits 13, 23, 33 Switching circuits 14, 15, 16, 17, 18, 19 Overcurrent detection circuit 20 Pin drivers DUT1 to 3 Devices under test IN1 to 4 Input terminals of DUT OUT1 to 4 Output terminals of DUT Ri11 to 13, 21 to 23, 31 to 33 Resistance Ro11 to 14, 21 to 23, 31 to 33 Resistance C Capacitor D11, 12, 21, 22, 31, 32 Diode T11, 21, 31, 41 P-channel FET T12, 22, 32, 42 n-channel FET OR theory ExOR1 to 4 Exclusive OR T1 Control transistor T2 Parallel switch T3 Switch for adjusting potential Vr Reference power supply R1 Resistance R2,3 Current detection resistor OP1 Voltage control operational amplifier OP2,3 Overcurrent detection differential amplifier AMP1,2 3, 4 amplifier

Claims (5)

[Claims] 1. A thermostat capable of holding a plurality of devices under test (hereinafter, referred to as “DUT”) having an input terminal, an output terminal, a power supply terminal, and a ground terminal at a high temperature; and the DUT connectable to the input terminal. A test pattern generation circuit for generating a test pattern capable of operating the test pattern, and connected to the test pattern generation circuit,
An expected value generation circuit that inputs the test pattern and outputs an expected value expected to be output from the output terminal when the test pattern is input to the input terminal;
A test apparatus having a pass / fail judgment circuit for judging whether or not the DUT is faulty; a test apparatus connected to the pass / fail judgment circuit, and opening the power supply terminal and a power supply when the judgment is the fault. A second switching circuit that is connected to the switching circuit and the pass / fail determination circuit and short-circuits the power supply terminal and the ground terminal when the determination is a failure.
And a switching circuit. 2. The burn-in test apparatus according to claim 1, wherein the pass / fail judgment circuit judges the failure when the output of the output terminal does not match the expected value. 3. An overcurrent detection circuit connected to the pass / fail determination circuit for detecting an overcurrent flowing through the power supply terminal or the ground terminal, wherein the pass / fail determination circuit detects the overcurrent. The burn-in test apparatus according to claim 1 or 2, wherein the failure is determined. 4. A first overcurrent detection circuit connected to the pass / fail determination circuit for detecting a first overcurrent flowing through the power supply terminal, and a second overcurrent detection circuit connected to the pass / fail determination circuit and flowing through the ground terminal. And an overcurrent detection circuit that detects an overcurrent of, the expected value can be output to the output terminal, and the pass / fail determination circuit determines whether the first overcurrent or the second overcurrent is The burn-in test apparatus according to claim 1, wherein the failure is determined when the failure is detected. 5. A step of maintaining a plurality of DUTs having an input terminal, an output terminal, a power supply terminal, and a ground terminal at a high temperature; a step of inputting a test pattern to the input terminal to operate the DUT; Outputting an expected value expected to be output from the output terminal when the test pattern is input to the test pattern; and determining whether the DUT has failed using the expected value. A step of opening the power supply terminal and the power supply and short-circuiting the power supply terminal and the ground terminal when the determination is the failure.