JP2002176351A - Level shifter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a level shifter circuit which can perform a high speed operation and in which a consumption current is small when a power supply voltage of a low potential is a very low voltage and when the voltage difference between a power supply voltage of a high potential and the power supply voltage of the low potential is large. SOLUTION: A through-current is caused to flow through the PMOS and the NMOS of a driver on an output stage at the time when the NMOS on the output stage is turned on because the PMOS of the driver on the output stage is turned on when an input terminal is changed from a high level to a low level. However, since a first transistor for compensation is turned on by the output signal of a predriver at the same time with when the NMOS of the driver on the output stage is turned on and the PMOS of the driver on the output stage is quickly turned off, the power consumption of the through- current is reduced, and an output terminal is also quickly discharged and driven to a low level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a level shifter circuit for converting a voltage level of a signal to a circuit for driving an output terminal of a semiconductor device.

[0002]

2. Description of the Related Art A level shifter circuit converts a voltage level of a signal, for example, from a low potential voltage to a high potential voltage or vice versa, and is used in, for example, an output circuit of a semiconductor device.

FIG. 4 is a circuit diagram showing an example of a conventional level shifter circuit. The level shifter circuit 34 shown in FIG.
Is a low potential voltage VCCL applied to the input terminal IN2.
The signal having the amplitude of the converted high-potential voltage VCCH is converted to the output terminal OUT2.
, A driver 12 in the output stage, a pre-driver 14 in the preceding stage, and a P-type M
An OS transistor (PMOS) 16 is provided.

The driver 12 in the output stage is a PMOS
20 and an NMOS 22, and the pre-driver 14
A PMOS 24 and NMOSs 26 and 28 are provided.
The PMOS 20 of the driver 12 at the output stage is connected between the high potential power supply VCCH and the output terminal OUT2, and its gate is connected to the internal node N21. Also, NM
The OS 22 is connected between the output terminal OUT2 and the ground, and has a gate connected to the internal node N22.

The PMOS 24 of the pre-driver 14 is connected between the low potential power supply VCCL and the internal node N22, and the NMOSs 26 and 28 are connected to the internal node N2, respectively.
2, N21 and ground. Also,
The gates of the PMOS 24 and the NMOSs 26 and 28 are all connected to the input terminal IN2. The PMOS 16 of the feedback transistor is connected between the high-potential power supply VCCH and the internal node N21, and its gate is connected to the output terminal OUT2.

In the level shifter circuit 34, when the input terminal IN2 changes from low level to high level or vice versa, the output terminal OUT2 changes from low level to high level or vice versa.

When the input terminal IN2 is at a high level (low potential power supply voltage VCCL), the PMOS of the pre-driver 14
24 is off, NMOSs 26 and 28 are on, and both internal nodes N21 and N22 are at low level. Accordingly, the PMOS 20 of the driver 12 in the output stage is on, the NMOS 22 is off, and the output terminal OUT2 is driven to a high level (high-potential power supply voltage VCCH), so the PMOS 16 of the feedback transistor is off. .

As shown in the waveform diagram of FIG. 2, the input terminal IN
When 2 changes from the high level to the low level, the PMOS 24 of the pre-driver 14 is turned on, the NMOSs 26 and 28 are turned off, and the internal node N22 is charged up. At this point, the internal node N21 is connected to the NMOS 28 of the pre-driver 14 and the PMOS 16 of the feedback transistor.
Are both in a floating low state because they are off, and the PMOS 20 of the driver 12 in the output stage remains on.

The NMOS 22 of the driver 12 in the output stage is
The internal node N22 is charged up and the NMOS2
At the time when the threshold voltage becomes higher than the threshold voltage of No. 2, the output terminal OUT2 is discharged. At this time, as described above, the PMOS of the driver 12 in the output stage is used.
20 is on, and a through current flows from the high-potential power supply VCCH to the ground via the PMOS 20 and the NMOS 22 of the driver 12 in the output stage.

The PMOS transistor 16 as a feedback transistor turns on when the output terminal OUT2 is discharged and becomes lower than the high-potential power supply voltage VCCH by the threshold voltage of the PMOS 16 or more, and the internal node N21 is at a high level (high potential). (The power supply voltage VCCH). At this point, the PMOS 20 of the driver 12 in the output stage
Is completely turned off, and the output terminal OUT2 is driven to a low level by the NMOS 22 of the driver 12 in the output stage.

Subsequently, when the input terminal IN2 changes from low level to high level, the PMOS of the pre-driver 14
24 is off, NMOSs 26 and 28 are on, and internal nodes N21 and N22 are simultaneously discharged. In addition,
At this time, the PMOS transistor 16 of the feedback transistor remains ON, and the high potential power supply VCCH
Through current flows to the ground via the PMOS 16 of the feedback transistor and the NMOS 28 of the pre-driver 14.

The PMOS 20 of the driver 12 at the output stage is
When the internal node N21 is discharged and becomes lower than the threshold voltage of the high potential power supply voltage VCCH-PMOS 20, it is turned on. Thereby, the output terminal OUT2
Is charged up by the PMOS 20. Also,
The NMOS 22 of the driver 12 in the output stage is connected to the internal node N
22 is discharged and turned off when the voltage becomes lower than the threshold voltage of the NMOS 22.

The PMOS 16 of the feedback transistor is turned off when the output terminal OUT2 is charged up and becomes higher than the threshold voltage of the high-potential power supply voltage VCCH-PMOS 16. Thereby, the internal node N21
Is driven to a low level via the NMOS 28 of the pre-driver 14, and accordingly, the output terminal OUT2
Is driven to a high level (high-potential power supply voltage VCCH) by the PMOS 20 of the driver 12 in the output stage.

In the level shifter circuit 34 shown in FIG.
Since the input terminal IN2 changes from a high level to a low level, the output terminal OUT2 is discharged, the PMOS 16 of the feedback transistor is turned on, and the current supplied through the PMOS 16 when the input terminal IN2 changes from the high level to the low level. As a result, P of the driver 12 in the output stage
The PMOS 20 is on until the internal node N21 is charged up to a potential at which the MOS 20 is completely turned off.

Therefore, in addition to the problem that the consumption current increases due to the through current, the low potential power supply voltage VCCL
Is low, or when the voltage difference between the high-potential power supply voltage VCCH and the low-potential power supply voltage VCCL is large, the discharge by the NMOS 22 of the driver 12 in the output stage is hindered by the charge-up by the PMOS 20, and the operating speed becomes extremely high PN (PMOS and NM)
There is a problem that the balance of the OS (OS) is lost and the shape in the layout arrangement becomes unreasonable.

[0016]

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems based on the prior art and to solve the problem when the low-potential power supply voltage is very low, or when the high-potential power supply voltage and the low-potential power supply voltage are low. It is an object of the present invention to provide a level shifter circuit which can operate at high speed and consumes less current even when a voltage difference from a power supply voltage is large.

[0017]

According to the present invention, there is provided a level shifter circuit for converting a voltage level of a signal from a low potential voltage to a high potential voltage. A first transistor connected between the output terminal and a ground, the second transistor being connected between the output terminal and a ground, the first transistor being configured to charge up the output terminal according to a voltage level of a first internal node; A driver of an output stage including a second transistor for discharging the output terminal in accordance with a voltage level of a node; a driver connected between a low-potential power supply and the second internal node; A third transistor that charges up the second internal node in response to the second internal node, and is connected between the second internal node and ground, and is connected to the input terminal according to a voltage level of the input terminal. A fourth transistor that discharges a second internal node, and a fifth transistor that is connected between the first internal node and ground and discharges the first internal node according to a voltage level of the input terminal. A pre-driver including: a transistor; connected between the high-potential power supply and the first internal node;
A feedback transistor that charges up the first internal node in accordance with a voltage level of the output terminal; a second transistor connected between the high-potential power supply and the first internal node; And a compensating transistor for charging up the first internal node according to the voltage level of the level shifter circuit.

Here, in the above-described level shifter circuit, further connected between the high-potential power supply and the output terminal, the output terminal is charged up in accordance with the voltage level of the input terminal. Preferably, a second compensating transistor is provided.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a level shifter circuit according to the present invention will be described in detail with reference to a preferred embodiment shown in the accompanying drawings.

FIG. 1 shows a first example of the level shifter circuit of the present invention.
FIG. 3 is a configuration circuit diagram of the embodiment of FIG. The level shifter circuit 10 shown in FIG. 1 converts a voltage level of a signal for driving an output terminal of a semiconductor device from a low potential voltage to a high potential voltage, and includes a driver 12 in an output stage and a pre-driver 14 in a preceding stage. And a P-type MOS transistor (PMOS) 16 as a feedback transistor and an N-type MOS transistor (NMOS) 18 as a compensation transistor.

In the illustrated level shifter circuit 10,
First, the driver 12 at the output stage drives the output terminal OUT1 according to the output signal of the pre-driver 14, and includes a PMOS 20 and an NMOS 22. P
The MOS 20 includes a high-potential power supply VCCH and an output terminal OUT.
1 and the NMOS 22 is connected to the output terminal OUT
1 and ground. Also, PMOS
The gates of NMOS 20 and NMOS 22 are connected to internal nodes N11 and N12, respectively.

Subsequently, the pre-driver 14 is connected to the input terminal I
In response to the signal applied to N1, internal nodes N11, N
12 and a PMOS 24 and an NMO
S26 and S28 are provided. The PMOS 24 is connected between the low potential power supply VCCL and the internal node N12.
MOSs 26 and 28 are connected to internal nodes N12 and N1 respectively.
1 and ground. Also,
The gates of the PMOS 24 and the NMOSs 26 and 28 are both connected to the input terminal IN1.

The PMOS 16 of the feedback transistor sets the internal node N11 to a high level (high-potential power supply voltage VCCH) in response to the signal driven to the output terminal OUT1.
To drive to. The PMOS 16 is connected between the high-potential power supply VCCH and the internal node N11, and has a gate connected to the output terminal OUT1.

The NMOS 18 of the compensation transistor is connected to the internal node N11 according to the output signal of the pre-driver 14.
At a high level (low potential power supply voltage VCCL-NMOS1
8 threshold voltage). NMO
S18 is connected between the high-potential power supply VCCH and the internal node N11, and its gate is connected to the internal node N11.

Next, referring to the waveform diagram shown in FIG.
The operation of the level shifter circuit 10 will be described using an example in which the input terminal IN1 changes from a high level to a low level. In FIG. 2, the vertical axis represents voltage (V) and the horizontal axis represents time (T).

When the input terminal IN1 is at a high level (low potential power supply voltage VCCL), the PMOS2 of the pre-driver 14
4 is off, NMOSs 26 and 28 are on, and both internal nodes N11 and N12 are at low level. Therefore, the PMOS 20 of the driver 12 in the output stage is turned on,
Since the NMOS 22 is off and the NMOS of the compensating transistor is off, and the output terminal OUT1 is driven to a high level (high-potential power supply voltage VCCH), the PMOS 16 of the feedback transistor is off.

As shown in the waveform diagram of FIG.
When 1 changes from the high level to the low level, the PMOS 24 of the pre-driver 14 is turned on, the NMOSs 26 and 28 are turned off, and the internal node N12 is charged up. The compensation transistor NMOS18 is connected to the internal node N12.
Is turned on when it becomes higher than the threshold voltage of the NMOS 18, whereby the internal node N11 is also charged up.

The NMOS 2 of the driver 12 in the output stage
2, the internal node N12 is charged up and NM
It turns on when the voltage becomes higher than the threshold voltage of OS22, and the output terminal OUT1 is discharged. In addition,
At this time, the internal node N11 is charged up, and the PMOS 20 of the driver 12 in the output stage is transitioning from on to off, and a through current flows from the high-potential power supply VCCH to the ground via the PMOS 20 and the NMOS 22. Flows.

The PMOS 16 of the feedback transistor is turned on when the output terminal OUT1 is discharged and becomes lower than the high potential power supply voltage VCCH by the threshold voltage of the PMOS 16 or more. Then, the internal node N11 is charged up, and the high potential power supply voltage VCCH-PM
At the time when the voltage becomes higher than the threshold voltage of the OS 20, the PMOS 20 of the driver 12 in the output stage is completely turned off, and the output terminal OUT1 is connected to the NMOS 22
Driven low.

The NMOS 18 of the compensation transistor
During the period in which the PMOS 16 of the feedback transistor is turned off, the NMOS 18 itself turns on, and after the PMOS 16 of the feedback transistor is turned on, the N of the compensating transistor is turned off.
The internal node N11 is charged up by both the MOS 18 and the PMOS 16 as a feedback transistor, and is turned off when it becomes higher than the threshold voltage of the low potential power supply voltage VCCL-NMOS 18.

Subsequently, when the input terminal IN1 changes from low level to high level, the PMOS of the pre-driver 14
24 is off, NMOSs 26 and 28 are on, and internal nodes N11 and N12 are simultaneously discharged. In addition,
At this point, the PMOS transistor 16 of the feedback transistor remains on, and the high-potential power supply VCCH
A through current flows to the ground via the MOS 16 and the NMOS 28. Also, the NMO of the compensation transistor
S18 is already off.

The PMOS 20 of the driver 12 in the output stage is
When the internal node N11 is discharged and becomes lower than the threshold voltage of the high-potential power supply voltage VCCH-PMOS 20, it turns on. Thereby, the output terminal OUT1
Is charged up by the PMOS 20. Also,
The NMOS 22 of the driver 12 in the output stage is connected to the internal node N
12 is discharged and turned off when the voltage becomes lower than the threshold voltage of the NMOS 22.

The PMOS 16 of the feedback transistor turns off when the output terminal OUT1 is charged up and becomes higher than the threshold voltage of the high potential power supply voltage VCCH-PMOS 16. Thereby, the internal node N11
Is driven to a low level via the NMOS 28 of the pre-driver 14. The output terminal OUT1 is driven to a high level (high-potential power supply voltage VCCH) by the PMOS 20 of the driver 12 in the output stage.

As described above, in the level shifter circuit 10 of the illustrated example, when the output terminal OUT1 transitions from the high level to the low level, the NMOS 22 of the driver 12 in the output stage
Is turned on and the NMOS of the compensation transistor
18 turns on to charge up the internal node N11. At this point, the PMOS 20 of the driver 12 in the output stage starts to transition from on to off, so that the through current is reduced and the output terminal OUT1 is discharged at high speed. .

Next, a second embodiment of the present invention will be described.

FIG. 2 shows a second example of the level shifter circuit of the present invention.
FIG. 3 is a configuration circuit diagram of the embodiment of FIG. The level shifter circuit 30 shown in FIG. 10 is different from the level shifter circuit 10 shown in FIG. 1 in further including an NMOS 32 of a compensation transistor. The NMOS 32 is connected between the high-potential power supply VCCH and the output terminal OUT1, and has a gate connected to the input terminal IN1. The other configuration of the level shifter circuit 30 is the same as that of the level shifter circuit 10 shown in FIG.
Is exactly the same as

In the level shifter circuit 30 of the illustrated example, when the input terminal IN1 changes from high level to low level, the operation is similar to that of the level shifter circuit 10 shown in FIG.
Is the same as On the other hand, when the input terminal IN1 changes from the low level to the high level, in addition to the operation of the level shifter circuit 10 shown in FIG. 1, the NMOS 32 of the compensating transistor is also turned on, and the output terminal OUT1 is charged up.

In the level shifter circuit 30 in the illustrated example, at the same time when the input terminal IN1 changes from the low level to the high level, the NMOS 32 of the compensating transistor is turned on.
Since the output terminal OUT1 starts to be charged up, the PMOS 16 of the feedback transistor is quickly turned off to reduce the through current, the internal node N11 is driven to a low level, and the PMOS 20 of the driver 12 in the output stage can be quickly turned on. The terminal OUT1 is charged up at a high speed.

The NMOS 32 of the compensation transistor
During the period in which the PMOS 20 of the output stage driver 12 is off, the NMOS 32 itself operates while the output stage driver 1 is turned off.
2 are turned on, the NMOS 32 of the compensating transistor and the PMOS of the driver 12 in the output stage are turned on.
20, the output terminal OUT1 is charged up and turned off when it becomes higher than the low potential power supply voltage VCCL-the threshold voltage of the NMOS 18 of the compensating transistor.

The low-potential power supply voltage VCCL and the high-potential power supply voltage VCCH are connected to the low-potential power supply voltage VCCL.
It is not limited at all except that the voltage level of the high potential power supply voltage VCCH is higher than the voltage level of the power supply voltage VCCH.

The level shifter circuit of the present invention is basically as described above. As described above, the level shifter circuit of the present invention has been described in detail. However, the present invention is not limited to the above-described embodiment, and various improvements and modifications may be made without departing from the gist of the present invention. .

[0042]

As described above in detail, when the input terminal changes from the high level to the low level, the first compensating transistor is turned on at the same time when the NMOS of the driver at the output stage is turned on. Are turned on, the PMOS of the driver at the output stage is quickly turned off, and the output terminal is discharged at high speed by the NMOS of the driver at the output stage to drive it to a low level. At the same time when the input terminal changes from low level to high level, NM of the second compensation transistor
The OS is turned on, the PMOS of the feedback transistor is quickly turned off, the PMOS of the driver at the output stage is quickly turned on, and the output terminal is quickly charged up by the PMOS of the driver at the output stage, and the high level of the high potential voltage is obtained. It is intended to drive to. According to the level shifter circuit of the present invention, when the low-potential power supply voltage is extremely low,
Even when the voltage difference between the low-potential power supply voltage and the high-potential power supply voltage is extremely large, there is an effect that the through current can be stopped quickly to reduce current consumption and to operate at high speed. .

[Brief description of the drawings]

FIG. 1 is a configuration circuit diagram of a first embodiment of a level shifter circuit of the present invention.

FIG. 2 is a waveform diagram illustrating an operation of an example of the present invention and a conventional level shifter circuit.

FIG. 3 is a configuration circuit diagram of a second embodiment of the level shifter circuit of the present invention.

FIG. 4 is a configuration circuit diagram of an example of a conventional level shifter circuit.

[Explanation of symbols]

10, 30, 34 level shifter circuit 12 driver of output stage 14 pre-driver 16, 20, 24 P-type MOS transistor (PMO
S) 18, 22, 26, 28, 32 N-type MOS transistor (NMOS)

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) 5J055 AX02 AX27 AX54 AX64 BX16 CX10 DX22 DX56 DX72 DX83 EX07 EX19 EX21 EY21 EZ07 EZ19 EZ20 FX12 FX17 FX35 GX01 GX04 5J056 AA00 AA32 BB02 BB17 CC19 CC20 KK21 DD

Claims (2)

[Claims] 1. A level shifter circuit for converting a voltage level of a signal from a low potential voltage to a high potential voltage, the level shifter circuit being connected between a high potential power supply and the output terminal, and having a voltage of a first internal node. A first transistor that charges up the output terminal according to a level, and a second transistor that is connected between the output terminal and ground and discharges the output terminal according to a voltage level of a second internal node. A driver in an output stage including a transistor, a third transistor connected between a low-potential power supply and the second internal node, and charging up the second internal node in accordance with a voltage level of the input terminal A fourth transistor connected between the second internal node and ground and discharging the second internal node according to the voltage level of the input terminal. And a pre-driver connected between the first internal node and ground, the pre-driver including a fifth transistor that discharges the first internal node according to a voltage level of the input terminal; A feedback transistor, which is connected between the power supply of the first internal node and the first internal node and charges up the first internal node in accordance with the voltage level of the output terminal; And a compensation transistor that is connected between the internal node and the internal node and charges up the first internal node in accordance with the voltage level of the second internal node. 2. The level shifter circuit according to claim 1, further comprising a power supply connected between the high-potential power supply and the output terminal, and charging the output terminal according to a voltage level of the input terminal. A level shifter circuit comprising a second compensating transistor that rises.