JP2002176349A - Semiconductor device - Google Patents

Abstract

(57) [Summary] In a semiconductor device to which a single or a plurality of power supply potentials are supplied according to a use mode, when a power supply potential is not supplied to some circuits, a through current flows to a next-stage circuit. Provided is a semiconductor device which can reduce power consumption by preventing flow and can uniquely determine an output level of a next-stage circuit. SOLUTION: A first circuit INV1 which outputs an output signal based on an input signal when a first power supply potential is supplied, and sets an output to a high impedance state when the first power supply potential is not supplied, A second circuit which operates by being supplied with a second power supply potential, and includes a second circuit NAND which obtains a logical product of an output of the first circuit and the first power supply potential.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a gate array, an embedded array, and a standard cell, and more particularly to a semiconductor device having an input cell operated by a power supply different from a power supply of an internal circuit.

[0002]

2. Description of the Related Art In general, a device such as a printer may be connected to several types of interfaces operating at various power supply voltages. FIG. 2 shows an example of an input circuit of a semiconductor device used in such a device.

In FIG. 2, an input signal supplied from an interface via an input terminal P is a transistor Q
It is inverted by a first-stage inverter circuit composed of P1 and QN1. The output of the first-stage inverter circuit is inverted by the second-stage inverter circuit constituted by the transistors QP2 and QN2, and supplied to the internal circuit. Here, the power supply potential HVDD on the high potential side is supplied to the first-stage inverter circuit, and the power supply potential LVDD on the low potential side is supplied to the second-stage inverter circuit.

In this semiconductor device, the power supply potential HVDD may not be supplied, for example, because the interface connected to the input terminal P is not used.
In such a case, the output of the first stage inverter circuit becomes high impedance state (indefinite potential) through current I ₀ flows through the transistor QP2 and QN2 constituting the inverter circuit of the second stage There is a possibility that it will. In order to reduce the power consumption of the semiconductor device, even when the power supply potential HVDD is not supplied, the through current I
It is desirable not to let ₀ flow.

Japanese Patent Application Laid-Open Publication No. Hei 9-307421 discloses that when a high-potential power supply potential is not supplied to the first-stage inverter circuit, a low-potential power supply potential is supplied. By inverting the supplied output signal of the second-stage inverter circuit and returning it to the input of the second-stage inverter circuit, the input potential of the second-stage inverter circuit is fixed, and no through current flows. Such a semiconductor integrated circuit is described. However, whether the output signal of the second-stage inverter circuit is at a high level or a low level depends on various conditions at that time and cannot be uniquely determined. Depending on the circuit at the next stage, the circuit may not operate properly unless the level of the input signal is uniquely determined.

[0006]

SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a semiconductor device to which a single or a plurality of power supply potentials are supplied depending on a use mode, wherein some of the circuits have a power supply potential. By providing a semiconductor device capable of reducing power consumption by preventing a through current from flowing to the next-stage circuit when power is not supplied, and uniquely defining the output level of the next-stage circuit. is there.

[0007]

In order to solve the above-mentioned problems, a semiconductor device according to the present invention outputs an output signal based on an input signal when a first power supply potential is supplied. A first circuit for setting an output to a high impedance state when a power supply potential is not supplied, and a second circuit operable to be supplied with a second power supply potential, wherein an output of the first circuit and a first power supply are provided. A second circuit for obtaining a logical product with the potential.

This semiconductor device may have a path for passing a direct current between the first power supply potential and the ground potential. The semiconductor device operates based on the output of the second circuit when the second power supply potential is supplied.
May be further provided. Here, an inversion circuit or a buffer circuit can be used as the first circuit, and a NAND circuit or an AND circuit can be used as the second circuit.

According to the semiconductor device of the present invention configured as described above, even when the power supply potential is not supplied to the first circuit, the second circuit can output the first power supply potential from the output of the first circuit. Is obtained, the power consumption is reduced by preventing a through current from flowing through the second circuit, and the output level of the second circuit can be uniquely determined.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a circuit configuration of a semiconductor device according to one embodiment of the present invention. This semiconductor device has been considered for use in devices such as printers connected to several types of interfaces operating at various power supply voltages.

In FIG. 1, this semiconductor device has an input terminal P1 connected to a first interface and an input terminal P2 connected to a second interface. The first interface connects circuits operating at a first power supply potential (power supply potential HVDD on the high potential side) between a device using the semiconductor device and an external device such as a PC (personal computer). I do. On the other hand, the second
Interface connects circuits operating at the second power supply potential (lower power supply potential LVDD) between a device in which the semiconductor device is used and another external device.

An input terminal P1 has an inverter circuit INV
1 and the input cell 10 including the NAND circuit are connected, and the output of the input cell 10 is supplied to the internal logic circuit 30. On the other hand, the input terminal P2 has an inverter circuit IN
The input cells 20 including V2 and INV3 are connected,
The output of the input cell 20 is supplied to the internal logic circuit 30. Each of the inverter circuits INV1 to INV3 is configured as shown in FIG.
As shown in (1), it is composed of one P-channel transistor and one N-channel transistor.

Here, since the input cell 20 and the internal logic circuit 30 operate by being supplied with the common power supply potential LVDD, the output of the inverter circuit INV2 is in a high impedance state when the internal logic circuit 30 is operating. Never. However, in the input cell 10, the power supply potential HVDD is not used because the first interface connected to the input terminal P1 is not used.
May not be supplied. That is, the wiring from the first power supply circuit becomes open or the first power supply potential drops to the ground potential. In such a case, the output of the inverter circuit INV1 enters a high impedance state, and the output level becomes unstable.

The NAND circuit included in the input cell 10 includes:
The logical product of the output level of the inverter circuit INV1 and the first power supply potential is obtained, and the logical product is inverted to obtain the internal logic circuit 3.
Supply 0. The resistor R1 in FIG. 1 indicates a path through which a direct current flows between the first power supply potential and the ground potential. That is, a large number of transistors, resistance elements, and capacitance elements are connected to the first power supply potential, and a direct current flows due to the impedance of the real component of these elements. Therefore, the first power supply potential naturally goes to a low level after a predetermined time has elapsed since the supply of the power supply potential HVDD is stopped. Alternatively, when the timing at which the first power supply potential goes low is late, a resistance element may be actually formed. Since a resistance element having a relatively high resistance value can be used as the resistance element, current consumption can be reduced.

When the first power supply potential goes low, N
Since the output of the AND circuit is fixed at the low level, there is no possibility that the internal logic circuit 30 malfunctions. On the other hand, when the power supply potential HVDD is supplied as the first power supply potential, the output of the inverter circuit INV1 becomes NA
The signal is inverted by the ND circuit and supplied to the internal logic circuit 30.

In the above embodiment, the first cell is constituted by the inverter circuit and the NAND circuit. However, a buffer circuit and an AND circuit may be used.

[0017]

As described above, according to the present invention, even if the power supply potential is not supplied to some of the circuits, the through current does not flow to the next-stage circuit to reduce the power consumption. In addition, the output level of the next stage circuit can be uniquely determined.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of an input circuit of a conventional semiconductor device.

[Explanation of symbols]

 10, 20 Input cell 30 Internal logic circuit P, P1, P2 Input terminal QP1, QP2 P-channel transistor QN1, QN2 N-channel transistor INV1-INV3 Inverter circuit

Claims (5)

[Claims] 1. A semiconductor device to which one or a plurality of power supply potentials are supplied according to a use mode, wherein an output signal is output based on an input signal when a first power supply potential is supplied, A first circuit for setting an output to a high impedance state when the first power supply potential is not supplied, and a second circuit operating by supplying a second power supply potential, wherein the output of the first circuit is A second circuit for obtaining a logical product with a first power supply potential. 2. The apparatus according to claim 1, further comprising a path for flowing a direct current between the first power supply potential and a ground potential.
13. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, further comprising a third circuit that operates based on an output of the second circuit when the second power supply potential is supplied. 4. The semiconductor device according to claim 1, wherein said first circuit is an inverting circuit or a buffer circuit. 5. The method according to claim 1, wherein the second circuit is a NAND circuit or an A circuit.
The semiconductor device according to claim 1, wherein the semiconductor device is an ND circuit.