JP2002176078A - Probe card - Google Patents

Abstract

(57) [Problem] To provide a low-cost, high-performance probe card capable of enhancing a test function without increasing a chip area. A circuit substrate constituting a probe card is provided.
Is responsible for sending and receiving signals facing the chip area CHIP on the wafer WF, and is mounted on a prober connected to a test head (not shown). In the circuit substrate 10, an opposing connection area (here, an opening) 11 corresponding to the chip area CHIP
A probe 12 is provided on the substrate, and the circuit substrate 10 and the wafer WF are brought close to each other so as to be brought into contact with predetermined external terminals in the chip area CHIP to be measured. On the circuit substrate 10, a test circuit chip 13 for generating and processing a signal related to at least a part of the test to the chip area CHIP is provided in a predetermined signal transmission path near the probe 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a probe card for measuring electrical characteristics by mechanically bringing a probe into contact with an LSI chip pad in a wafer state.

[0002]

2. Description of the Related Art A probe card is used for a test in a wafer state before an assembling process of LSI manufacturing. The probe card has probes (probe pins, needles, etc.) to be brought into contact with terminals (bonding pads, bump electrodes, etc.) in the LSI chip area to be measured.
Having. A test signal or a test pattern is input from the probe to the LSI chip.

[0003] The probe card is connected to a tester and becomes a part of constructing a test system. The tester compares the output value from the LSI with an expected value via a probe card to determine whether the function of the LSI is good or not, and measures input / output signals, analog values such as voltage and current of a power supply, and the like.
An LSI that is selected as a non-defective product through such a wafer probing test is sent to an assembly process.

In recent years, the diameter of wafers has been increasing, and the number of chips obtained per wafer has been increasing. Along with this, the time spent on the wafer probing test as described above increases, and higher efficiency is desired.

[0005] BIS is a technology for improving the efficiency of wafer testing
T (Built in Self Test). BIST is generally known as a method of arranging a tester function in a chip so that the chip can be tested. A real-time test is possible, and the quality of a chip can be determined even when the chip is incorporated in the system.

[0006]

SUMMARY OF THE INVENTION However, BIS
In the case of T, test hardware is provided in the chip, so that the adverse effects of an increase in the chip area and a decrease in the operation speed of the chip are inevitable. Further, since a random pattern test pattern is used, the defect detection rate is not necessarily high. If the tester function is to be enhanced, there is a further concern that the chip area, the operating speed will be adversely affected, and the manufacturing cost will increase.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a low-cost, high-performance probe card capable of enhancing a test function without increasing a chip area. is there.

[0008]

A probe card according to the present invention is a circuit substrate for transmitting and receiving signals by facing a chip region on a wafer. A test circuit chip for generating and processing a signal related to a part of the test is provided.

According to the probe card of the present invention, a simple form in which a test circuit chip is added to an existing probe card is realized. The test circuit chip is provided on a circuit substrate on which the mounting area is not strictly restricted, that is, on a probe card.

A probe card according to a more preferred embodiment of the present invention is a circuit substrate which faces a chip region on a wafer and is responsible for transmitting and receiving signals, and corresponds to at least one of the chip regions in the circuit substrate. An electrical connection that is disposed on a predetermined position in the chip area with respect to the opposite connection area, and that is brought into contact with a predetermined portion of the chip area by approaching the circuit substrate and the wafer. A connection part, and a test circuit mounted and disposed on a predetermined signal transmission path near the electrical connection part on the circuit substrate, for generating and processing a signal related to at least a part of a test to the chip area And a chip.

According to the probe card of the present invention, a test circuit chip is mounted near the electrical connection. Thus, relatively high-speed and low-cost inspection can be expected without incorporating a test circuit into the chip area.

The test circuit chip is mounted and provided with a detachable and replaceable connector connection for convenience such as insertion of a new test point.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic view showing a configuration of a main part of a probe card according to an embodiment of the present invention. The circuit substrate 10 constituting the probe card is responsible for transmitting and receiving signals while facing the chip area CHIP on the wafer WF. The circuit substrate 10 is mounted on, for example, a prober connected to a test head (not shown).

In the chip area CHIP, bump electrodes (not shown) are provided as external terminals. The circuit substrate 10 is provided with an opposing connection region (here, an opening) 11 corresponding to the chip region CHIP. In the opposing connection area 11, a probe 12 extending from the peripheral edge of the opening to a position of a predetermined external terminal in the chip area CHIP is provided. The extension source of the probe 12 may be a multilayer (not shown). These probes 12 are configured to come into contact with predetermined external terminals (for example, bump electrodes) in the chip area CHIP to be measured by bringing the circuit base 10 and the wafer WF close to each other.

In this embodiment, a test circuit chip for generating and processing a signal related to at least a part of a test to a chip area CHIP on a predetermined signal transmission path near a probe 12 on a circuit substrate 10. 13 are deployed.

The test circuit chip 13 includes, for example, a test pattern generator for generating a test signal pattern, an output pattern compressor for fetching and compressing a test result signal from the chip area CHIP, and a comparator for comparing with an expected value. included. The expected value prepared by the tester may be used as the expected value.

According to the above configuration, a simple form of adding the test circuit chip 13 to an existing probe card is realized. The test circuit chip 13 is provided on the circuit substrate 10 (that is, on the probe card) in which the mounting area is not relatively restricted.

As a result, it is possible to provide a margin for the test circuit configuration, and it is possible to expect generation of an extensive test pattern such as generation of an optimum test pattern corresponding to each circuit block in the chip area CHIP. Further, the chip area CHI
A relatively high-speed and low-cost inspection can be expected without incorporating a test circuit on the P side.

FIG. 2 is a schematic diagram of a semiconductor measuring apparatus to which the probe card according to the embodiment of the present invention is applied. FIG. 3 is a schematic diagram illustrating a configuration example of mounting a test circuit chip in the probe card according to the embodiment of the present invention.

In FIG. 2, as a prober 20, for example, a movement control stage 21 on which a semiconductor wafer WF is mounted
Is provided, and the circuit board 2 is used for signal transmission with the tester 24.
2 are deployed. The circuit substrate 22 is divided into a plurality of transmission function circuits such as a test head 221, a performance board 222, a signal relay substrate 223, and a probe card 224. Connected to.

Probe card (probe not shown) 224
Is connected to the tester 24 and is a part of constructing a test system. The tester 24 compares the output value from the LSI configured on the wafer WF with the expected value via the probe card 224 to determine whether the function of the LSI is good or not, such as input / output signals, voltage and current of the power supply part, and the like. Measure analog values and so on. An LSI that is selected as a non-defective product through such a wafer probing test is sent to an assembly process.

In the probe card 224, a test circuit chip 13 for assisting the signal generation / analysis processing of the tester 24 is mounted and provided. Note that the test circuit chip 13 may be mounted and provided with connection by a detachable connector 23 for convenience such as insertion of a new test point (FIG. 3).

According to the above configuration, the test circuit chip 13
Accordingly, a test function can be added to or changed from the probe card 224 at a relatively low cost. The test circuit chip 13 contributes to the generation of an optimal test pattern according to each circuit block in the wafer WF to be measured and the speeding up of the test. The test circuit chip 13
Is not limited at all, such as film-mounted connector connection, bare chip mounting, and mounting with various package products.

The above configuration of the present invention can of course be expected to have the same effect on a multi-cavity probe card. As a result, the time spent for the wafer probing test is further reduced, and higher efficiency can be achieved.

[0025]

As described above, according to the present invention, a test circuit chip is mounted and arranged on a probe card to generate and analyze an optimum test pattern for a chip region of a semiconductor wafer to be measured. Processing can be expected. As a result, it is possible to provide a low-cost, high-performance probe card capable of enhancing the test function without increasing the chip area.

[Brief description of the drawings]

FIG. 1 is a schematic view showing a configuration of a main part of a probe card according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a semiconductor measuring device to which the probe card according to the embodiment of the present invention is applied.

FIG. 3 is a schematic view showing a configuration example of a test circuit chip mounting in the probe card according to the embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Circuit base material (probe card) 11 ... Opposite connection area 12 ... Probe 13 ... Test circuit chip 20 ... Prober 221 ... Test head 222 ... Performance board 223 ... Signal relay base material 224 ... Probe card 23 ... Connector 24 ... Tester WF: Semiconductor wafer CHIP: Chip area

Claims (3)

[Claims] 1. A circuit substrate facing a chip region on a wafer for transmitting and receiving a signal, wherein a signal related to at least a part of a test to the chip region is generated and processed on the circuit substrate. A test circuit chip for performing the test. 2. A circuit substrate facing a chip region on a wafer for transmitting and receiving signals, comprising: a counter connection region provided at least in correspondence with at least one of the chip regions on the circuit substrate; Regarding the connection region, an electric connection portion arranged on a predetermined position in the chip region, and brought into contact with a predetermined portion of the chip region by bringing the circuit substrate and the wafer close to each other; A test circuit chip mounted and arranged in a predetermined signal transmission path near a dynamic connection portion and performing generation and processing of a signal related to at least a part of a test to the chip area. card. 3. The probe card according to claim 1, wherein the test circuit chip is mounted and provided with a detachable and replaceable connector connection.